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* hw/misc: Model KCS devices in the Aspeed LPC controllerAndrew Jeffery2021-03-091-1/+27
| | | | | | | | | | | | | | | | | | | Keyboard-Controller-Style devices for IPMI purposes are exposed via LPC IO cycles from the BMC to the host. Expose support on the BMC side by implementing the usual MMIO behaviours, and expose the ability to inspect the KCS registers in "host" style by accessing QOM properties associated with each register. The model caters to the IRQ style of both the AST2600 and the earlier SoCs (AST2400 and AST2500). The AST2600 allocates an IRQ for each LPC sub-device, while there is a single IRQ shared across all subdevices on the AST2400 and AST2500. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Reviewed-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20210302014317.915120-6-andrew@aj.id.au> Signed-off-by: Cédric Le Goater <clg@kaod.org>
* hw/misc: Add a basic Aspeed LPC controller modelCédric Le Goater2021-03-091-0/+10
| | | | | | | | | | | This is a very minimal framework to access registers which are used to configure the AHB memory mapping of the flash chips on the LPC HC Firmware address space. Signed-off-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Message-Id: <20210302014317.915120-5-andrew@aj.id.au> Signed-off-by: Cédric Le Goater <clg@kaod.org>
* hw/arm: ast2600: Correct the iBT interrupt IDAndrew Jeffery2021-03-091-1/+1
| | | | | | | | | | | | The AST2600 allocates distinct GIC IRQs for the LPC subdevices such as the iBT device. Previously on the AST2400 and AST2500 the LPC subdevices shared a single LPC IRQ. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20210302014317.915120-4-andrew@aj.id.au> Signed-off-by: Cédric Le Goater <clg@kaod.org>
* hw/arm: ast2600: Set AST2600_MAX_IRQ to value from datasheetAndrew Jeffery2021-03-091-1/+1
| | | | | | | | | | | | The datasheet says we have 197 IRQs allocated, and we need more than 128 to describe IRQs from LPC devices. Raise the value now to allow modelling of the LPC devices. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20210302014317.915120-3-andrew@aj.id.au> Signed-off-by: Cédric Le Goater <clg@kaod.org>
* hw/arm: ast2600: Force a multiple of 32 of IRQs for the GICAndrew Jeffery2021-03-091-2/+2
| | | | | | | | | | This appears to be a requirement of the GIC model. The AST2600 allocates 197 GIC IRQs, which we will adjust shortly. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Reviewed-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20210302014317.915120-2-andrew@aj.id.au> Signed-off-by: Cédric Le Goater <clg@kaod.org>
* arm/ast2600: Fix SMP booting with -kernelJoel Stanley2021-03-091-7/+0Star
| | | | | | | | | | | | | | | | | The ast2600 machines do not have PSCI firmware, so this property should have never been set. Removing this node fixes SMP booting Linux kernels that have PSCI enabled, as Linux fails to find PSCI in the device tree and falls back to the soc-specific method for enabling secondary CPUs. The comment is out of date as Qemu has supported -kernel booting since 9bb6d14081ce ("aspeed: Add boot stub for smp booting"), in v5.1. Fixes: f25c0ae1079d ("aspeed/soc: Add AST2600 support") Signed-off-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Cédric Le Goater <clg@kaod.org> Tested-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20210303010505.635621-1-joel@jms.id.au> Signed-off-by: Cédric Le Goater <clg@kaod.org>
* arm: Update infocenter.arm.com URLsPeter Maydell2021-02-111-1/+1
| | | | | | | | | | | | | | | Update infocenter.arm.com URLs for various pieces of Arm documentation to the new developer.arm.com equivalents. (There is a redirection in place from the old URLs, but we might as well update our comments in case the redirect ever disappears in future.) This patch covers all the URLs which are not MPS2/SSE-200/IoTKit related (those are dealt with in a different patch). Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-id: 20210205171456.19939-1-peter.maydell@linaro.org
* ast2600: SRAM is 89KBJoel Stanley2020-12-101-1/+1
| | | | | | | | | | On the AST2600A1, the SRAM size was increased to 89KB. Fixes: 7582591ae745 ("aspeed: Support AST2600A1 silicon revision") Signed-off-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20201112012113.835858-1-joel@jms.id.au> Signed-off-by: Cédric Le Goater <clg@kaod.org>
* hw/arm/aspeed: Map the UART5 device unconditionallyPhilippe Mathieu-Daudé2020-09-181-5/+3Star
| | | | | | | | | | The UART5 is present on the machine regardless there is a character device connected to it. Map it unconditionally. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20200905212415.760452-1-f4bug@amsat.org> Signed-off-by: Cédric Le Goater <clg@kaod.org>
* aspeed_soc: Rename memmap/irqmap enum constantsEduardo Habkost2020-08-271-104/+104
| | | | | | | | | | | | | | | | | | | | | | | | | | | Some of the enum constant names conflict with the QOM type check macros: ASPEED_GPIO ASPEED_I2C ASPEED_RTC ASPEED_SCU ASPEED_SDHCI ASPEED_SDMC ASPEED_VIC ASPEED_WDT ASPEED_XDMA This needs to be addressed to allow us to transform the QOM type check macros into functions generated by OBJECT_DECLARE_TYPE(). Rename all the constants to ASPEED_DEV_*, to avoid conflicts. Reviewed-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Daniel P. Berrangé <berrange@redhat.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com> Tested-By: Roman Bolshakov <r.bolshakov@yadro.com> Message-Id: <20200825192110.3528606-7-ehabkost@redhat.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
* error: Eliminate error_propagate() with Coccinelle, part 1Markus Armbruster2020-07-101-36/+18Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When all we do with an Error we receive into a local variable is propagating to somewhere else, we can just as well receive it there right away. Convert if (!foo(..., &err)) { ... error_propagate(errp, err); ... return ... } to if (!foo(..., errp)) { ... ... return ... } where nothing else needs @err. Coccinelle script: @rule1 forall@ identifier fun, err, errp, lbl; expression list args, args2; binary operator op; constant c1, c2; symbol false; @@ if ( ( - fun(args, &err, args2) + fun(args, errp, args2) | - !fun(args, &err, args2) + !fun(args, errp, args2) | - fun(args, &err, args2) op c1 + fun(args, errp, args2) op c1 ) ) { ... when != err when != lbl: when strict - error_propagate(errp, err); ... when != err ( return; | return c2; | return false; ) } @rule2 forall@ identifier fun, err, errp, lbl; expression list args, args2; expression var; binary operator op; constant c1, c2; symbol false; @@ - var = fun(args, &err, args2); + var = fun(args, errp, args2); ... when != err if ( ( var | !var | var op c1 ) ) { ... when != err when != lbl: when strict - error_propagate(errp, err); ... when != err ( return; | return c2; | return false; | return var; ) } @depends on rule1 || rule2@ identifier err; @@ - Error *err = NULL; ... when != err Not exactly elegant, I'm afraid. The "when != lbl:" is necessary to avoid transforming if (fun(args, &err)) { goto out } ... out: error_propagate(errp, err); even though other paths to label out still need the error_propagate(). For an actual example, see sclp_realize(). Without the "when strict", Coccinelle transforms vfio_msix_setup(), incorrectly. I don't know what exactly "when strict" does, only that it helps here. The match of return is narrower than what I want, but I can't figure out how to express "return where the operand doesn't use @err". For an example where it's too narrow, see vfio_intx_enable(). Silently fails to convert hw/arm/armsse.c, because Coccinelle gets confused by ARMSSE being used both as typedef and function-like macro there. Converted manually. Line breaks tidied up manually. One nested declaration of @local_err deleted manually. Preexisting unwanted blank line dropped in hw/riscv/sifive_e.c. Signed-off-by: Markus Armbruster <armbru@redhat.com> Reviewed-by: Eric Blake <eblake@redhat.com> Message-Id: <20200707160613.848843-35-armbru@redhat.com>
* qom: Use returned bool to check for failure, Coccinelle partMarkus Armbruster2020-07-101-3/+2Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The previous commit enables conversion of foo(..., &err); if (err) { ... } to if (!foo(..., errp)) { ... } for QOM functions that now return true / false on success / error. Coccinelle script: @@ identifier fun = { object_apply_global_props, object_initialize_child_with_props, object_initialize_child_with_propsv, object_property_get, object_property_get_bool, object_property_parse, object_property_set, object_property_set_bool, object_property_set_int, object_property_set_link, object_property_set_qobject, object_property_set_str, object_property_set_uint, object_set_props, object_set_propv, user_creatable_add_dict, user_creatable_complete, user_creatable_del }; expression list args, args2; typedef Error; Error *err; @@ - fun(args, &err, args2); - if (err) + if (!fun(args, &err, args2)) { ... } Fails to convert hw/arm/armsse.c, because Coccinelle gets confused by ARMSSE being used both as typedef and function-like macro there. Convert manually. Line breaks tidied up manually. Signed-off-by: Markus Armbruster <armbru@redhat.com> Reviewed-by: Eric Blake <eblake@redhat.com> Reviewed-by: Vladimir Sementsov-Ogievskiy <vsementsov@virtuozzo.com> Message-Id: <20200707160613.848843-29-armbru@redhat.com>
* qom: Put name parameter before value / visitor parameterMarkus Armbruster2020-07-101-28/+26Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The object_property_set_FOO() setters take property name and value in an unusual order: void object_property_set_FOO(Object *obj, FOO_TYPE value, const char *name, Error **errp) Having to pass value before name feels grating. Swap them. Same for object_property_set(), object_property_get(), and object_property_parse(). Convert callers with this Coccinelle script: @@ identifier fun = { object_property_get, object_property_parse, object_property_set_str, object_property_set_link, object_property_set_bool, object_property_set_int, object_property_set_uint, object_property_set, object_property_set_qobject }; expression obj, v, name, errp; @@ - fun(obj, v, name, errp) + fun(obj, name, v, errp) Chokes on hw/arm/musicpal.c's lcd_refresh() with the unhelpful error message "no position information". Convert that one manually. Fails to convert hw/arm/armsse.c, because Coccinelle gets confused by ARMSSE being used both as typedef and function-like macro there. Convert manually. Fails to convert hw/rx/rx-gdbsim.c, because Coccinelle gets confused by RXCPU being used both as typedef and function-like macro there. Convert manually. The other files using RXCPU that way don't need conversion. Signed-off-by: Markus Armbruster <armbru@redhat.com> Reviewed-by: Eric Blake <eblake@redhat.com> Reviewed-by: Vladimir Sementsov-Ogievskiy <vsementsov@virtuozzo.com> Message-Id: <20200707160613.848843-27-armbru@redhat.com> [Straightforwad conflict with commit 2336172d9b "audio: set default value for pcspk.iobase property" resolved]
* qdev: Use returned bool to check for qdev_realize() etc. failureMarkus Armbruster2020-07-101-34/+17Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Convert foo(..., &err); if (err) { ... } to if (!foo(..., &err)) { ... } for qdev_realize(), qdev_realize_and_unref(), qbus_realize() and their wrappers isa_realize_and_unref(), pci_realize_and_unref(), sysbus_realize(), sysbus_realize_and_unref(), usb_realize_and_unref(). Coccinelle script: @@ identifier fun = { isa_realize_and_unref, pci_realize_and_unref, qbus_realize, qdev_realize, qdev_realize_and_unref, sysbus_realize, sysbus_realize_and_unref, usb_realize_and_unref }; expression list args, args2; typedef Error; Error *err; @@ - fun(args, &err, args2); - if (err) + if (!fun(args, &err, args2)) { ... } Chokes on hw/arm/musicpal.c's lcd_refresh() with the unhelpful error message "no position information". Nothing to convert there; skipped. Fails to convert hw/arm/armsse.c, because Coccinelle gets confused by ARMSSE being used both as typedef and function-like macro there. Converted manually. A few line breaks tidied up manually. Signed-off-by: Markus Armbruster <armbru@redhat.com> Reviewed-by: Eric Blake <eblake@redhat.com> Reviewed-by: Vladimir Sementsov-Ogievskiy <vsementsov@virtuozzo.com> Reviewed-by: Greg Kurz <groug@kaod.org> Message-Id: <20200707160613.848843-5-armbru@redhat.com>
* aspeed: Fix realize error API violationMarkus Armbruster2020-07-021-2/+3
| | | | | | | | | | | | | | | | | | | | | | | | | The Error ** argument must be NULL, &error_abort, &error_fatal, or a pointer to a variable containing NULL. Passing an argument of the latter kind twice without clearing it in between is wrong: if the first call sets an error, it no longer points to NULL for the second call. aspeed_soc_ast2600_realize() and aspeed_soc_realize() are wrong that way: they pass &err to object_property_set_int() and object_property_set_bool() without checking it, and then to sysbus_realize(). Harmless, because the former can't actually fail here. Fix by passing &error_abort instead. Cc: "Cédric Le Goater" <clg@kaod.org> Cc: Peter Maydell <peter.maydell@linaro.org> Cc: Andrew Jeffery <andrew@aj.id.au> Cc: Joel Stanley <joel@jms.id.au> Cc: qemu-arm@nongnu.org Signed-off-by: Markus Armbruster <armbru@redhat.com> Message-Id: <20200630090351.1247703-24-armbru@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
* hw/arm: Drop useless object_property_set_link() error handlingMarkus Armbruster2020-07-021-15/+5Star
| | | | | | | | | | | | | | | object_property_set_link() fails when the property doesn't exist, is not settable, or its .check() method fails. These are all programming errors here, so passing it &error_abort is appropriate. Cc: Peter Maydell <peter.maydell@linaro.org> Cc: "Cédric Le Goater" <clg@kaod.org> Cc: Andrew Jeffery <andrew@aj.id.au> Cc: Joel Stanley <joel@jms.id.au> Cc: qemu-arm@nongnu.org Signed-off-by: Markus Armbruster <armbru@redhat.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20200630090351.1247703-17-armbru@redhat.com>
* aspeed: Clean up roundabout error propagationMarkus Armbruster2020-07-021-6/+4Star
| | | | | | | | | | | | | | | | | | | | | | | | Replace sysbus_realize(SYS_BUS_DEVICE(&s->spi[i]), &local_err); error_propagate(&err, local_err); if (err) { error_propagate(errp, err); return; } by sysbus_realize(SYS_BUS_DEVICE(&s->spi[i]), &err); if (err) { error_propagate(errp, err); return; } Cc: Cédric Le Goater <clg@kaod.org> Signed-off-by: Markus Armbruster <armbru@redhat.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20200630090351.1247703-13-armbru@redhat.com>
* qdev: Convert bus-less devices to qdev_realize() with CoccinelleMarkus Armbruster2020-06-151-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | All remaining conversions to qdev_realize() are for bus-less devices. Coccinelle script: // only correct for bus-less @dev! @@ expression errp; expression dev; @@ - qdev_init_nofail(dev); + qdev_realize(dev, NULL, &error_fatal); @ depends on !(file in "hw/core/qdev.c") && !(file in "hw/core/bus.c")@ expression errp; expression dev; symbol true; @@ - object_property_set_bool(OBJECT(dev), true, "realized", errp); + qdev_realize(DEVICE(dev), NULL, errp); @ depends on !(file in "hw/core/qdev.c") && !(file in "hw/core/bus.c")@ expression errp; expression dev; symbol true; @@ - object_property_set_bool(dev, true, "realized", errp); + qdev_realize(DEVICE(dev), NULL, errp); Note that Coccinelle chokes on ARMSSE typedef vs. macro in hw/arm/armsse.c. Worked around by temporarily renaming the macro for the spatch run. Signed-off-by: Markus Armbruster <armbru@redhat.com> Acked-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Paolo Bonzini <pbonzini@redhat.com> Message-Id: <20200610053247.1583243-57-armbru@redhat.com>
* sysbus: Convert qdev_set_parent_bus() use with Coccinelle, part 4Markus Armbruster2020-06-151-6/+4Star
| | | | | | | | | | | This is still the same transformation as in the previous commits, but here the sysbus_init_child_obj() and its matching realize in are in separate files. Fortunately, there's just one realize left to convert. Signed-off-by: Markus Armbruster <armbru@redhat.com> Reviewed-by: Paolo Bonzini <pbonzini@redhat.com> Message-Id: <20200610053247.1583243-51-armbru@redhat.com>
* sysbus: Convert qdev_set_parent_bus() use with Coccinelle, part 2Markus Armbruster2020-06-151-50/+39Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is the same transformation as in the previous commit, except sysbus_init_child_obj() and realize are too separated for the commit's Coccinelle script to handle, typically because sysbus_init_child_obj() is in a device's instance_init() method, and the matching realize is in its realize() method. Perhaps a Coccinelle wizard could make it transform that pattern, but I'm just a bungler, and the best I can do is transforming the two separate parts separately: @@ expression errp; expression child; symbol true; @@ - object_property_set_bool(OBJECT(child), true, "realized", errp); + sysbus_realize(SYS_BUS_DEVICE(child), errp); // only correct with a matching sysbus_init_child_obj() transformation! @@ expression errp; expression child; symbol true; @@ - object_property_set_bool(child, true, "realized", errp); + sysbus_realize(SYS_BUS_DEVICE(child), errp); // only correct with a matching sysbus_init_child_obj() transformation! @@ expression child; @@ - qdev_init_nofail(DEVICE(child)); + sysbus_realize(SYS_BUS_DEVICE(child), &error_fatal); // only correct with a matching sysbus_init_child_obj() transformation! @@ expression child; expression dev; @@ dev = DEVICE(child); ... - qdev_init_nofail(dev); + sysbus_realize(SYS_BUS_DEVICE(dev), &error_fatal); // only correct with a matching sysbus_init_child_obj() transformation! @@ expression child; identifier dev; @@ DeviceState *dev = DEVICE(child); ... - qdev_init_nofail(dev); + sysbus_realize(SYS_BUS_DEVICE(dev), &error_fatal); // only correct with a matching sysbus_init_child_obj() transformation! @@ expression parent, name, size, type; expression child; symbol true; @@ - sysbus_init_child_obj(parent, name, child, size, type); + sysbus_init_child_XXX(parent, name, child, size, type); @@ expression parent, propname, type; expression child; @@ - sysbus_init_child_XXX(parent, propname, child, sizeof(*child), type) + object_initialize_child(parent, propname, child, type) @@ expression parent, propname, type; expression child; @@ - sysbus_init_child_XXX(parent, propname, &child, sizeof(child), type) + object_initialize_child(parent, propname, &child, type) This script is *unsound*: we need to manually verify init and realize conversions are properly paired. This commit has only the pairs where object_initialize_child()'s @child and sysbus_realize()'s @dev argument text match exactly within the same source file. Note that Coccinelle chokes on ARMSSE typedef vs. macro in hw/arm/armsse.c. Worked around by temporarily renaming the macro for the spatch run. Signed-off-by: Markus Armbruster <armbru@redhat.com> Acked-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Paolo Bonzini <pbonzini@redhat.com> Message-Id: <20200610053247.1583243-49-armbru@redhat.com>
* sysbus: Drop useless OBJECT() in sysbus_init_child_obj() callsMarkus Armbruster2020-06-151-22/+17Star
| | | | | | | | | | OBJECT(child) expands to ((Object *)(child)). sysbus_init_child_obj() parameter @child is void *. Pass child instead of OBJECT(child). Signed-off-by: Markus Armbruster <armbru@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Paolo Bonzini <pbonzini@redhat.com> Message-Id: <20200610053247.1583243-40-armbru@redhat.com>
* qom: Less verbose object_initialize_child()Markus Armbruster2020-06-151-3/+1Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | All users of object_initialize_child() pass the obvious child size argument. Almost all pass &error_abort and no properties. Tiresome. Rename object_initialize_child() to object_initialize_child_with_props() to free the name. New convenience wrapper object_initialize_child() automates the size argument, and passes &error_abort and no properties. Rename object_initialize_childv() to object_initialize_child_with_propsv() for consistency. Convert callers with this Coccinelle script: @@ expression parent, propname, type; expression child, size; symbol error_abort; @@ - object_initialize_child(parent, propname, OBJECT(child), size, type, &error_abort, NULL) + object_initialize_child(parent, propname, child, size, type, &error_abort, NULL) @@ expression parent, propname, type; expression child; symbol error_abort; @@ - object_initialize_child(parent, propname, child, sizeof(*child), type, &error_abort, NULL) + object_initialize_child(parent, propname, child, type) @@ expression parent, propname, type; expression child; symbol error_abort; @@ - object_initialize_child(parent, propname, &child, sizeof(child), type, &error_abort, NULL) + object_initialize_child(parent, propname, &child, type) @@ expression parent, propname, type; expression child, size, err; expression list props; @@ - object_initialize_child(parent, propname, child, size, type, err, props) + object_initialize_child_with_props(parent, propname, child, size, type, err, props) Note that Coccinelle chokes on ARMSSE typedef vs. macro in hw/arm/armsse.c. Worked around by temporarily renaming the macro for the spatch run. Signed-off-by: Markus Armbruster <armbru@redhat.com> Acked-by: Alistair Francis <alistair.francis@wdc.com> [Rebased: machine opentitan is new (commit fe0fe4735e7)] Reviewed-by: Paolo Bonzini <pbonzini@redhat.com> Message-Id: <20200610053247.1583243-37-armbru@redhat.com>
* arm/aspeed: Rework NIC attachmentCédric Le Goater2020-06-151-2/+1Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The number of MACs supported by an Aspeed SoC is defined by "macs_num" under the SoC model, that is two for the AST2400 and AST2500 and four for the AST2600. The model initializes the maximum number of supported MACs but the number of realized devices is capped by the number of network device back-ends defined on the command line. This can leave unrealized devices hanging around in the QOM composition tree. To get virtual hardware that matches the physical hardware, you have to pass exactly as many -nic options as there are MACs, and some of them must be -nic none: * Machines ast2500-evb, palmetto-bmc, romulus-bmc, sonorapass-bmc, swift-bmc, and witherspoon-bmc: two -nic, and the second one must be -nic none. * Machine ast2600-evb: four -nic, the first one must be -nic none. * Machine tacoma-bmc: four nic, the first two and the last one must be -nic none. Modify the machine initialization to define which MACs are attached to a network device back-end using a bit-field property "macs-mask" and let the SoC realize all network devices. The default setting of "macs-mask" is "use MAC0" only, which works for all our AST2400 and AST2500 machines. The AST2600 machines have different configurations. The AST2600 EVB machine activates MAC1, MAC2 and MAC3 and the Tacoma BMC machine activates MAC2. Incompatible CLI change: -nic options now apply to *active* MACs: MAC1, MAC2, MAC3 for ast2600-evb, MAC2 for tacoma-bmc, and MAC0 for all the others. The machines now always get all MACs as they should. Visible in "info qom-tree", here's the change for tacoma-bmc: /machine (tacoma-bmc-machine) /peripheral (container) /peripheral-anon (container) /soc (ast2600-a1) [...] /ftgmac100[0] (ftgmac100) /ftgmac100[0] (qemu:memory-region) /ftgmac100[1] (ftgmac100) + /ftgmac100[0] (qemu:memory-region) /ftgmac100[2] (ftgmac100) + /ftgmac100[0] (qemu:memory-region) /ftgmac100[3] (ftgmac100) + /ftgmac100[0] (qemu:memory-region) [...] /mii[0] (aspeed-mmi) /aspeed-mmi[0] (qemu:memory-region) /mii[1] (aspeed-mmi) + /aspeed-mmi[0] (qemu:memory-region) /mii[2] (aspeed-mmi) + /aspeed-mmi[0] (qemu:memory-region) /mii[3] (aspeed-mmi) + /aspeed-mmi[0] (qemu:memory-region) Also visible in "info qtree"; here's the change for tacoma-bmc: dev: ftgmac100, id "" gpio-out "sysbus-irq" 1 aspeed = true - mac = "52:54:00:12:34:56" - netdev = "hub0port0" + mac = "52:54:00:12:34:57" + netdev = "" mmio 000000001e660000/0000000000002000 dev: ftgmac100, id "" - aspeed = false - mac = "00:00:00:00:00:00" + gpio-out "sysbus-irq" 1 + aspeed = true + mac = "52:54:00:12:34:58" netdev = "" + mmio 000000001e680000/0000000000002000 dev: ftgmac100, id "" - aspeed = false - mac = "00:00:00:00:00:00" - netdev = "" + gpio-out "sysbus-irq" 1 + aspeed = true + mac = "52:54:00:12:34:56" + netdev = "hub0port0" + mmio 000000001e670000/0000000000002000 dev: ftgmac100, id "" - aspeed = false - mac = "00:00:00:00:00:00" + gpio-out "sysbus-irq" 1 + aspeed = true + mac = "52:54:00:12:34:59" netdev = "" + mmio 000000001e690000/0000000000002000 [...] dev: aspeed-mmi, id "" mmio 000000001e650000/0000000000000008 dev: aspeed-mmi, id "" + mmio 000000001e650008/0000000000000008 dev: aspeed-mmi, id "" + mmio 000000001e650010/0000000000000008 dev: aspeed-mmi, id "" + mmio 000000001e650018/0000000000000008 Inactive MACs will have no peer and QEMU may warn the user with : qemu-system-arm: warning: nic ftgmac100.0 has no peer qemu-system-arm: warning: nic ftgmac100.1 has no peer qemu-system-arm: warning: nic ftgmac100.3 has no peer Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Markus Armbruster <armbru@redhat.com> Reviewed-by: Joel Stanley <joel@jms.id.au> [Commit message expanded] Signed-off-by: Markus Armbruster <armbru@redhat.com> Message-Id: <20200609122339.937862-6-armbru@redhat.com>
* arm/aspeed: Compute the number of CPUs from the SoC definitionCédric Le Goater2020-06-151-13/+7Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit ece09beec457 ("aspeed: introduce a configurable number of CPU per machine") was a convient change during bringup but the Aspeed SoCs have a fixed number of CPUs : one for the AST2400 and AST2500, and two for the AST2600. When the number of CPUs configured with -smp is less than the SoC's fixed number, the "unconfigured" CPUs are left unrealized. This can happen for machines ast2600-evb and tacoma-bmc, where the SoC's fixed number is 2. To get virtual hardware that matches the physical hardware, you have to pass -smp cpus=2 (or its sugared form -smp 2). We normally reject -smp cpus=N when N exceeds the machine's limit. Except we ignore cpus=2 (and only cpus=2) with a warning for machines ast2500-evb, palmetto-bmc, romulus-bmc, sonorapass-bmc, swift-bmc, and witherspoon-bmc. Remove the "num-cpu" property from the SoC state and use the fixed number of CPUs defined in the SoC class instead. Compute the default, min, max number of CPUs of the machine directly from the SoC class definition. Machines ast2600-evb and tacoma-bmc now always get their second CPU as they should. Visible in "info qom-tree"; here's the change for ast2600-evb: /machine (ast2600-evb-machine) /peripheral (container) /peripheral-anon (container) /soc (ast2600-a1) /a7mpcore (a15mpcore_priv) /a15mp-priv-container[0] (qemu:memory-region) /gic (arm_gic) /gic_cpu[0] (qemu:memory-region) /gic_cpu[1] (qemu:memory-region) + /gic_cpu[2] (qemu:memory-region) /gic_dist[0] (qemu:memory-region) /gic_vcpu[0] (qemu:memory-region) /gic_viface[0] (qemu:memory-region) /gic_viface[1] (qemu:memory-region) + /gic_viface[2] (qemu:memory-region) /unnamed-gpio-in[0] (irq) [...] + /unnamed-gpio-in[160] (irq) [same for 161 to 190...] + /unnamed-gpio-in[191] (irq) Also visible in "info qtree"; here's the change for ast2600-evb: bus: main-system-bus type System dev: a15mpcore_priv, id "" gpio-in "" 128 - gpio-out "sysbus-irq" 5 - num-cpu = 1 (0x1) + gpio-out "sysbus-irq" 10 + num-cpu = 2 (0x2) num-irq = 160 (0xa0) mmio 0000000040460000/0000000000008000 dev: arm_gic, id "" - gpio-in "" 160 - num-cpu = 1 (0x1) + gpio-in "" 192 + num-cpu = 2 (0x2) num-irq = 160 (0xa0) revision = 2 (0x2) has-security-extensions = true has-virtualization-extensions = true num-priority-bits = 8 (0x8) mmio ffffffffffffffff/0000000000001000 mmio ffffffffffffffff/0000000000002000 mmio ffffffffffffffff/0000000000001000 mmio ffffffffffffffff/0000000000002000 mmio ffffffffffffffff/0000000000000100 + mmio ffffffffffffffff/0000000000000100 + mmio ffffffffffffffff/0000000000000200 mmio ffffffffffffffff/0000000000000200 The other machines now reject -smp cpus=2 just like -smp cpus=3 and up. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Markus Armbruster <armbru@redhat.com> [Commit message expanded] Signed-off-by: Markus Armbruster <armbru@redhat.com> Message-Id: <20200609122339.937862-5-armbru@redhat.com>
* qom: Drop parameter @errp of object_property_add() & friendsMarkus Armbruster2020-05-151-7/+6Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The only way object_property_add() can fail is when a property with the same name already exists. Since our property names are all hardcoded, failure is a programming error, and the appropriate way to handle it is passing &error_abort. Same for its variants, except for object_property_add_child(), which additionally fails when the child already has a parent. Parentage is also under program control, so this is a programming error, too. We have a bit over 500 callers. Almost half of them pass &error_abort, slightly fewer ignore errors, one test case handles errors, and the remaining few callers pass them to their own callers. The previous few commits demonstrated once again that ignoring programming errors is a bad idea. Of the few ones that pass on errors, several violate the Error API. The Error ** argument must be NULL, &error_abort, &error_fatal, or a pointer to a variable containing NULL. Passing an argument of the latter kind twice without clearing it in between is wrong: if the first call sets an error, it no longer points to NULL for the second call. ich9_pm_add_properties(), sparc32_ledma_realize(), sparc32_dma_realize(), xilinx_axidma_realize(), xilinx_enet_realize() are wrong that way. When the one appropriate choice of argument is &error_abort, letting users pick the argument is a bad idea. Drop parameter @errp and assert the preconditions instead. There's one exception to "duplicate property name is a programming error": the way object_property_add() implements the magic (and undocumented) "automatic arrayification". Don't drop @errp there. Instead, rename object_property_add() to object_property_try_add(), and add the obvious wrapper object_property_add(). Signed-off-by: Markus Armbruster <armbru@redhat.com> Reviewed-by: Eric Blake <eblake@redhat.com> Reviewed-by: Paolo Bonzini <pbonzini@redhat.com> Message-Id: <20200505152926.18877-15-armbru@redhat.com> [Two semantic rebase conflicts resolved]
* aspeed: Support AST2600A1 silicon revisionJoel Stanley2020-05-111-3/+3
| | | | | | | | | | | | | | There are minimal differences from Qemu's point of view between the A0 and A1 silicon revisions. As the A1 exercises different code paths in u-boot it is desirable to emulate that instead. Signed-off-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Andrew Jeffery <andrew@aj.id.au> Reviewed-by: Cédric Le Goater <clg@kaod.org> Message-id: 20200504093703.261135-1-joel@jms.id.au Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* aspeed/smc: Fix DMA support for AST2600Cédric Le Goater2020-03-231-0/+6
| | | | | | | | | | | | | | Recent firmwares uses SPI DMA transfers in U-Boot to load the different images (kernel, initrd, dtb) in the SoC DRAM. The AST2600 FMC model is missing the masks to be applied on the DMA registers which resulted in incorrect values. Fix that and wire the SPI controllers which have DMA support on the AST2600. Fixes: bcaa8ddd081c ("aspeed/smc: Add AST2600 support") Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Message-id: 20200320053923.20565-1-clg@kaod.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* hw/arm: ast2600: Wire up EHCI controllersGuenter Roeck2020-02-131-0/+23
| | | | | | | | | | | | | | | | | | | | | | Initialize EHCI controllers on AST2600 using the existing TYPE_PLATFORM_EHCI. After this change, booting ast2600-evb into Linux successfully instantiates a USB interface after the necessary changes are made to its devicetree files. ehci_hcd: USB 2.0 'Enhanced' Host Controller (EHCI) Driver ehci-platform: EHCI generic platform driver ehci-platform 1e6a3000.usb: EHCI Host Controller ehci-platform 1e6a3000.usb: new USB bus registered, assigned bus number 1 ehci-platform 1e6a3000.usb: irq 25, io mem 0x1e6a3000 ehci-platform 1e6a3000.usb: USB 2.0 started, EHCI 1.00 usb usb1: Manufacturer: Linux 5.5.0-09825-ga0802f2d0ef5-dirty ehci_hcd usb 1-1: new high-speed USB device number 2 using ehci-platform Reviewed-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Guenter Roeck <linux@roeck-us.net> Reviewed-by: Niek Linnenbank <nieklinnenbank@gmail.com> Message-id: 20200207174548.9087-1-linux@roeck-us.net Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* hw/arm: ast2600: Wire up the eMMC controllerAndrew Jeffery2020-01-301-3/+26
| | | | | | | | | | | | | | | | Initialise another SDHCI model instance for the AST2600's eMMC controller and use the SDHCI's num_slots value introduced previously to determine whether we should create an SD card instance for the new slot. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Reviewed-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Signed-off-by: Cédric Le Goater <clg@kaod.org> Message-id: 20200114103433.30534-3-clg@kaod.org [ clg : - removed ternary operator from sdhci_attach_drive() - renamed SDHCI objects with a '-controller' prefix ] Signed-off-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* hw/sd: Configure number of slots exposed by the ASPEED SDHCI modelAndrew Jeffery2020-01-301-0/+2
| | | | | | | | | | | | | | | | | | | The AST2600 includes a second cut-down version of the SD/MMC controller found in the AST2500, named the eMMC controller. It's cut down in the sense that it only supports one slot rather than two, but it brings the total number of slots supported by the AST2600 to three. The existing code assumed that the SD controller always provided two slots. Rework the SDHCI object to expose the number of slots as a property to be set by the SoC configuration. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Cédric Le Goater <clg@kaod.org> Message-id: 20200114103433.30534-2-clg@kaod.org [PMM: fixed up to use device_class_set_props()] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* ast2600: Configure CNTFRQ at 1125MHzAndrew Jeffery2019-12-201-0/+3
| | | | | | | | | | | This matches the configuration set by u-boot on the AST2600. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-id: 080ca1267a09381c43cf3c50d434fb6c186f2b6e.1576215453.git-series.andrew@aj.id.au Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* aspeed: Change the "nic" property definitionCédric Le Goater2019-12-161-3/+2Star
| | | | | | | | | | | | | | | | The Aspeed MII model has a link pointing to its associated FTGMAC100 NIC in the machine. Change the "nic" property definition so that it explicitly sets the pointer. The property isn't optional : not being able to set the link is a bug and QEMU should rather abort than exit in this case. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Greg Kurz <groug@kaod.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Cédric Le Goater <clg@kaod.org> Message-id: 20191119141211.25716-18-clg@kaod.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* aspeed: Change the "scu" property definitionCédric Le Goater2019-12-161-4/+4
| | | | | | | | | | | | | | | | The Aspeed Watchdog and Timer models have a link pointing to the SCU controller model of the machine. Change the "scu" property definition so that it explicitly sets the pointer. The property isn't optional : not being able to set the link is a bug and QEMU should rather abort than exit in this case. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Greg Kurz <groug@kaod.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Cédric Le Goater <clg@kaod.org> Message-id: 20191119141211.25716-17-clg@kaod.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* aspeed/i2c: Add support for DMA transfersCédric Le Goater2019-12-161-0/+5
| | | | | | | | | | | | | | | | | | The I2C controller of the Aspeed AST2500 and AST2600 SoCs supports DMA transfers to and from DRAM. A pair of registers defines the buffer address and the length of the DMA transfer. The address should be aligned on 4 bytes and the maximum length should not exceed 4K. The receive or transmit DMA transfer can then be initiated with specific bits in the Command/Status register of the controller. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Tested-by: Jae Hyun Yoo <jae.hyun.yoo@linux.intel.com> Signed-off-by: Cédric Le Goater <clg@kaod.org> Message-id: 20191119141211.25716-5-clg@kaod.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* aspeed: Add a DRAM memory region at the SoC levelCédric Le Goater2019-12-161-2/+5
| | | | | | | | | | | | | | Currently, we link the DRAM memory region to the FMC model (for DMAs) through a property alias at the SoC level. The I2C model will need a similar region for DMA support, add a DRAM region property at the SoC level for both model to use. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Tested-by: Jae Hyun Yoo <jae.hyun.yoo@linux.intel.com> Signed-off-by: Cédric Le Goater <clg@kaod.org> Message-id: 20191119141211.25716-4-clg@kaod.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* aspeed/soc: Add ASPEED Video stubJoel Stanley2019-10-151-0/+5
| | | | | | | Signed-off-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Cédric Le Goater <clg@kaod.org> Message-id: 20190925143248.10000-24-clg@kaod.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* aspeed: add support for the Aspeed MII controller of the AST2600Cédric Le Goater2019-10-151-0/+20
| | | | | | | | | The AST2600 SoC has an extra controller to set the PHY registers. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Message-id: 20190925143248.10000-23-clg@kaod.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* aspeed: Parameterise number of MACsJoel Stanley2019-10-151-2/+8
| | | | | | | | | | | | | To support the ast2600's four MACs allow SoCs to specify the number they have, and create that many. Signed-off-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Cédric Le Goater <clg@kaod.org> Message-id: 20190925143248.10000-22-clg@kaod.org [clg: - included a check on sc->macs_num when realizing the macs - included interrupt definitions for the AST2600 ] Signed-off-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* aspeed/soc: Add AST2600 supportCédric Le Goater2019-10-151-0/+492
Initial definitions for a simple machine using an AST2600 SoC (Cortex CPU). The Cortex CPU and its interrupt controller are too complex to handle in the common Aspeed SoC framework. We introduce a new Aspeed SoC class with instance_init and realize handlers to handle the differences with the AST2400 and the AST2500 SoCs. This will add extra work to keep in sync both models with future extensions but it makes the code clearer. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Message-id: 20190925143248.10000-19-clg@kaod.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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