| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | hw/arm: versal: Add a model of Xilinx Versal SoC | Edgar E. Iglesias | 2018-11-02 | 1 | -0/+323 |
| Add a model of Xilinx Versal SoC. Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Message-id: 20181102131913.1535-2-edgar.iglesias@xilinx.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | |||||
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index : bwlp/qemu.git | |
| Experimental fork of QEMU with video encoding patches | OpenSLX |
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