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| * | hw/arm/sbsa-ref: add "reg" property to DT cpu nodesLeif Lindholm2020-09-011-6/+23
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The sbsa-ref platform uses a minimal device tree to pass amount of memory as well as number of cpus to the firmware. However, when dumping that minimal dtb (with -M sbsa-virt,dumpdtb=<file>), the resulting blob generates a warning when decompiled by dtc due to lack of reg property. Add a simple reg property per cpu, representing a 64-bit MPIDR_EL1. This also ends up being cleaner than having the firmware calculating its own IDs for generating APCI. Signed-off-by: Leif Lindholm <leif@nuviainc.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-id: 20200827124335.30586-1-leif@nuviainc.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* | hw/arm/omap1:Remove redundant statement in omap_clkdsp_read()Chen Qun2020-09-011-1/+0Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Clang static code analyzer show warning: hw/arm/omap1.c:1760:15: warning: Value stored to 'cpu' during its initialization is never read CPUState *cpu = CPU(s->cpu); ^~~ ~~~~~~~~~~~ Reported-by: Euler Robot <euler.robot@huawei.com> Signed-off-by: Chen Qun <kuhn.chenqun@huawei.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Li Qiang <liq3ea@gmail.com> Message-Id: <20200827110311.164316-3-kuhn.chenqun@huawei.com> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
* | hw/arm/virt-acpi-build:Remove dead assignment in build_madt()Chen Qun2020-09-011-2/+1Star
|/ | | | | | | | | | | | | | | Clang static code analyzer show warning: hw/arm/virt-acpi-build.c:641:5: warning: Value stored to 'madt' is never read madt = acpi_data_push(table_data, sizeof *madt); ^ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Reported-by: Euler Robot <euler.robot@huawei.com> Signed-off-by: Chen Qun <kuhn.chenqun@huawei.com> Reviewed-by: Igor Mammedov <imammedo@redhat.com> Reviewed-by: Li Qiang <liq3ea@gmail.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Message-Id: <20200827110311.164316-2-kuhn.chenqun@huawei.com> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
* Merge remote-tracking branch ↵Peter Maydell2020-08-286-22/+56
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 'remotes/pmaydell/tags/pull-target-arm-20200828' into staging target-arm queue: * target/arm: Cleanup and refactoring preparatory to SVE2 * armsse: Define ARMSSEClass correctly * hw/misc/unimp: Improve information provided in log messages * hw/qdev-clock: Avoid calling qdev_connect_clock_in after DeviceRealize * hw/arm/xilinx_zynq: Call qdev_connect_clock_in() before DeviceRealize * hw/net/allwinner-sun8i-emac: Use AddressSpace for DMA transfers * hw/sd/allwinner-sdhost: Use AddressSpace for DMA transfers * target/arm: Fill in the WnR syndrome bit in mte_check_fail * target/arm: Clarify HCR_EL2 ARMCPRegInfo type * hw/arm/musicpal: Use AddressSpace for DMA transfers * hw/clock: Minor cleanups * hw/arm/sbsa-ref: fix typo breaking PCIe IRQs # gpg: Signature made Fri 28 Aug 2020 10:23:02 BST # gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE # gpg: issuer "peter.maydell@linaro.org" # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [ultimate] # gpg: aka "Peter Maydell <pmaydell@gmail.com>" [ultimate] # gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [ultimate] # Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE * remotes/pmaydell/tags/pull-target-arm-20200828: (35 commits) target/arm: Convert sq{, r}dmulh to gvec for aa64 advsimd target/arm: Convert integer multiply-add (indexed) to gvec for aa64 advsimd target/arm: Convert integer multiply (indexed) to gvec for aa64 advsimd target/arm: Generalize inl_qrdmlah_* helper functions target/arm: Tidy SVE tszimm shift formats target/arm: Split out gen_gvec_ool_zz target/arm: Split out gen_gvec_ool_zzz target/arm: Split out gen_gvec_ool_zzp target/arm: Merge helper_sve_clr_* and helper_sve_movz_* target/arm: Split out gen_gvec_ool_zzzp target/arm: Use tcg_gen_gvec_bitsel for trans_SEL_pppp target/arm: Clean up 4-operand predicate expansion target/arm: Merge do_vector2_p into do_mov_p target/arm: Rearrange {sve,fp}_check_access assert target/arm: Split out gen_gvec_fn_zzz, do_zzz_fn target/arm: Split out gen_gvec_fn_zz qemu/int128: Add int128_lshift armsse: Define ARMSSEClass correctly hw/misc/unimp: Display the offset with width of the region size hw/misc/unimp: Display the value with width of the access size ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * armsse: Define ARMSSEClass correctlyEduardo Habkost2020-08-281-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | TYPE_ARM_SSE is a TYPE_SYS_BUS_DEVICE subclass, but ARMSSEClass::parent_class is declared as DeviceClass. It never caused any problems by pure luck: We were not setting class_size for TYPE_ARM_SSE, so class_size of TYPE_SYS_BUS_DEVICE was being used (sizeof(SysBusDeviceClass)). This made the system allocate enough memory for TYPE_ARM_SSE devices even though ARMSSEClass was too small for a sysbus device. Additionally, the ARMSSEClass::info field ended up at the same offset as SysBusDeviceClass::explicit_ofw_unit_address. This would make sysbus_get_fw_dev_path() crash for the device. Luckily, sysbus_get_fw_dev_path() never gets called for TYPE_ARM_SSE devices, because qdev_get_fw_dev_path() is only used by the boot device code, and TYPE_ARM_SSE devices don't appear at the fw_boot_order list. Signed-off-by: Eduardo Habkost <ehabkost@redhat.com> Message-id: 20200826181006.4097163-1-ehabkost@redhat.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * hw/arm/xilinx_zynq: Call qdev_connect_clock_in() before DeviceRealizePhilippe Mathieu-Daudé2020-08-281-9/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Clock canonical name is set in device_set_realized (see the block added to hw/core/qdev.c in commit 0e6934f264). If we connect a clock after the device is realized, this code is not executed. This is currently not a problem as this name is only used for trace events, however this disrupt tracing. Fix by calling qdev_connect_clock_in() before realizing. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20200803105647.22223-3-f4bug@amsat.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * hw/arm/xilinx_zynq: Uninline cadence_uart_create()Philippe Mathieu-Daudé2020-08-281-2/+12
| | | | | | | | | | | | | | | | | | | | As we want to call qdev_connect_clock_in() before the device is realized, we need to uninline cadence_uart_create() first. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20200803105647.22223-2-f4bug@amsat.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * hw/net/allwinner-sun8i-emac: Use AddressSpace for DMA transfersPhilippe Mathieu-Daudé2020-08-281-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Allow the device to execute the DMA transfers in a different AddressSpace. The H3 SoC keeps using the system_memory address space, but via the proper dma_memory_access() API. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Niek Linnenbank <nieklinnenbank@gmail.com> Tested-by: Niek Linnenbank <nieklinnenbank@gmail.com> Message-id: 20200814122907.27732-1-f4bug@amsat.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * hw/sd/allwinner-sdhost: Use AddressSpace for DMA transfersPhilippe Mathieu-Daudé2020-08-282-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Allow the device to execute the DMA transfers in a different AddressSpace. The A10 and H3 SoC keep using the system_memory address space, but via the proper dma_memory_access() API. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Tested-by: Niek Linnenbank <nieklinnenbank@gmail.com> Reviewed-by: Niek Linnenbank <nieklinnenbank@gmail.com> Message-id: 20200814110057.307-1-f4bug@amsat.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * hw/arm/musicpal: Use AddressSpace for DMA transfersPhilippe Mathieu-Daudé2020-08-281-14/+31
| | | | | | | | | | | | | | | | | | | | | | | | | | Allow the device to execute the DMA transfers in a different AddressSpace. We keep using the system_memory address space, but via the proper dma_memory_access() API. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20200814125533.4047-1-f4bug@amsat.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * hw/arm/sbsa-ref: fix typo breaking PCIe IRQsGraeme Gregory2020-08-281-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | Fixing a typo in a previous patch that translated an "i" to a 1 and therefore breaking the allocation of PCIe interrupts. This was discovered when virtio-net-pci devices ceased to function correctly. Cc: qemu-stable@nongnu.org Fixes: 48ba18e6d3f3 ("hw/arm/sbsa-ref: Simplify by moving the gic in the machine state") Signed-off-by: Graeme Gregory <graeme@nuviainc.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-id: 20200821083853.356490-1-graeme@nuviainc.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* | Merge remote-tracking branch ↵Peter Maydell2020-08-289-306/+299Star
|\ \ | |/ |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 'remotes/ehabkost/tags/machine-next-pull-request' into staging Machine queue + QOM fixes and cleanups Bug fix: * numa: hmat: fix cache size check (Igor Mammedov) QOM fixes and cleanups: * Move QOM macros and typedefs to header files * Use TYPE_* constants on TypeInfo structs * Rename QOM type checking macros for consistency * Rename enum values and typedefs that conflict with QOM type checking amcros * Fix typos on QOM type checking macros * Delete unused QOM type checking macros that use non-existing typedefs * hvf: Add missing include * xen-legacy-backend: Add missing typedef XenLegacyDevice # gpg: Signature made Thu 27 Aug 2020 20:20:05 BST # gpg: using RSA key 5A322FD5ABC4D3DBACCFD1AA2807936F984DC5A6 # gpg: issuer "ehabkost@redhat.com" # gpg: Good signature from "Eduardo Habkost <ehabkost@redhat.com>" [full] # Primary key fingerprint: 5A32 2FD5 ABC4 D3DB ACCF D1AA 2807 936F 984D C5A6 * remotes/ehabkost/tags/machine-next-pull-request: (53 commits) dc390: Use TYPE_DC390_DEVICE constant ppce500: Use TYPE_PPC_E500_PCI_BRIDGE constant tosa: Use TYPE_TOSA_MISC_GPIO constant xlnx-zcu102: Use TYPE_ZCU102_MACHINE constant sclpconsole: Use TYPE_* constants amd_iommu: Use TYPE_AMD_IOMMU_PCI constant nios2_iic: Use TYPE_ALTERA_IIC constant etsec: Use TYPE_ETSEC_COMMON constant migration: Rename class type checking macros swim: Rename struct SWIM to Swim s390-virtio-ccw: Rename S390_MACHINE_CLASS macro nubus: Rename class type checking macros vfio/pci: Move QOM macros to header kvm: Move QOM macros to kvm.h mptsas: Move QOM macros to header pxa2xx: Move QOM macros to header rocker: Move QOM macros to header auxbus: Move QOM macros to header piix: Move QOM macros to header virtio-serial-bus: Move QOM macros to header ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * tosa: Use TYPE_TOSA_MISC_GPIO constantEduardo Habkost2020-08-271-1/+1
| | | | | | | | | | | | | | | | | | This will make future conversion to use OBJECT_DECLARE* easier. Signed-off-by: Eduardo Habkost <ehabkost@redhat.com> Reviewed-by: Li Qiang <liq3ea@gmail.com> Message-Id: <20200826184334.4120620-7-ehabkost@redhat.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
| * xlnx-zcu102: Use TYPE_ZCU102_MACHINE constantEduardo Habkost2020-08-271-1/+1
| | | | | | | | | | | | | | | | | | | | | | This will make future conversion to use OBJECT_DECLARE* easier. Signed-off-by: Eduardo Habkost <ehabkost@redhat.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: Li Qiang <liq3ea@gmail.com> Message-Id: <20200826184334.4120620-6-ehabkost@redhat.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
| * pxa2xx: Move QOM macros to headerEduardo Habkost2020-08-271-7/+0Star
| | | | | | | | | | | | | | | | | | | | This will make future conversion to OBJECT_DECLARE* easier. Reviewed-by: Daniel P. Berrangé <berrange@redhat.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com> Tested-By: Roman Bolshakov <r.bolshakov@yadro.com> Message-Id: <20200825192110.3528606-40-ehabkost@redhat.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
| * armsse: Rename QOM macros to avoid conflictsEduardo Habkost2020-08-271-12/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Rename TYPE_ARMSSE to TYPE_ARM_SSE, and ARMSSE*() type checking macros to ARM_SSE*(). This will avoid a future conflict between an ARM_SSE() type checking macro and the ARMSSE typedef name. Reviewed-by: Daniel P. Berrangé <berrange@redhat.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com> Tested-By: Roman Bolshakov <r.bolshakov@yadro.com> Message-Id: <20200825192110.3528606-26-ehabkost@redhat.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
| * aspeed_soc: Rename memmap/irqmap enum constantsEduardo Habkost2020-08-273-220/+220
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Some of the enum constant names conflict with the QOM type check macros: ASPEED_GPIO ASPEED_I2C ASPEED_RTC ASPEED_SCU ASPEED_SDHCI ASPEED_SDMC ASPEED_VIC ASPEED_WDT ASPEED_XDMA This needs to be addressed to allow us to transform the QOM type check macros into functions generated by OBJECT_DECLARE_TYPE(). Rename all the constants to ASPEED_DEV_*, to avoid conflicts. Reviewed-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Daniel P. Berrangé <berrange@redhat.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com> Tested-By: Roman Bolshakov <r.bolshakov@yadro.com> Message-Id: <20200825192110.3528606-7-ehabkost@redhat.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
| * allwinner-h3: Rename memmap enum constantsEduardo Habkost2020-08-272-65/+65
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Some of the enum constant names conflict with the QOM type check macros (AW_H3_CCU, AW_H3_SYSCTRL). This needs to be addressed to allow us to transform the QOM type check macros into functions generated by OBJECT_DECLARE_TYPE(). Rename all the constants to AW_H3_DEV_*, to avoid conflicts. Reviewed-by: Daniel P. Berrangé <berrange@redhat.com> Reviewed-by: Niek Linnenbank <nieklinnenbank@gmail.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com> Tested-By: Roman Bolshakov <r.bolshakov@yadro.com> Message-Id: <20200825192110.3528606-6-ehabkost@redhat.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
* | arm/acpi: fix an out of spec _UID for PCI rootMichael S. Tsirkin2020-08-271-1/+1
|/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On ARM/virt machine type QEMU currently reports an incorrect _UID in ACPI. The particular node in question is the primary PciRoot (PCI0 in ACPI), which gets assigned PCI0 in ACPI UID and 0 in the DevicePath. This is due to the _UID assigned to it by build_dsdt in hw/arm/virt-acpi-build.c Which does not correspond to the primary PCI identifier given by pcibus_num in hw/pci/pci.c In UEFI v2.8, section "10.4.2 Rules with ACPI _HID and _UID" ends with the paragraph, Root PCI bridges will use the plug and play ID of PNP0A03, This will be stored in the ACPI Device Path _HID field, or in the Expanded ACPI Device Path _CID field to match the ACPI name space. The _UID in the ACPI Device Path structure must match the _UID in the ACPI name space. (See especially the last sentence.) A similar bug has been reported on i386, on that architecture it has been reported to confuse at least macOS which uses ACPI UIDs to build the DevicePath for NVRAM boot options, while OVMF firmware gets them via an internal channel through QEMU. When UEFI firmware and ACPI have different values, this makes the underlying operating system unable to report its boot option. Cc: qemu-stable@nongnu.org Reported-by: Vitaly Cheptsov <vit9696@protonmail.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com>
* hw/arm/smmuv3: Advertise SMMUv3.2 range invalidationEric Auger2020-08-242-0/+2
| | | | | | | | | | | | Expose the RIL bit so that the guest driver uses range invalidation. Although RIL is a 3.2 features, We let the AIDR advertise SMMUv3.1 support as v3.x implementation is allowed to implement features from v3.(x+1). Signed-off-by: Eric Auger <eric.auger@redhat.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20200728150815.11446-12-eric.auger@redhat.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* hw/arm/smmuv3: Support HAD and advertise SMMUv3.1 supportEric Auger2020-08-244-3/+9
| | | | | | | | | | | | | | | | | HAD is a mandatory features with SMMUv3.1 if S1P is set, which is our case. Other 3.1 mandatory features come with S2P which we don't have. So let's support HAD and advertise SMMUv3.1 support in AIDR. HAD support allows the CD to disable hierarchical attributes, ie. if the HAD0/1 bit is set, the APTable field of table descriptors walked through TTB0/1 is ignored. Signed-off-by: Eric Auger <eric.auger@redhat.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20200728150815.11446-11-eric.auger@redhat.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* hw/arm/smmuv3: Let AIDR advertise SMMUv3.0 supportEric Auger2020-08-242-0/+4
| | | | | | | | | | Add the support for AIDR register. It currently advertises SMMU V3.0 spec. Signed-off-by: Eric Auger <eric.auger@redhat.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20200728150815.11446-10-eric.auger@redhat.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* hw/arm/smmuv3: Fix IIDR offsetEric Auger2020-08-241-1/+1
| | | | | | | | | | The SMMU IIDR register is at 0x018 offset. Fixes: 10a83cb9887 ("hw/arm/smmuv3: Skeleton") Signed-off-by: Eric Auger <eric.auger@redhat.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20200728150815.11446-9-eric.auger@redhat.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* hw/arm/smmuv3: Get prepared for range invalidationEric Auger2020-08-244-30/+67
| | | | | | | | | | | | | | Enhance the smmu_iotlb_inv_iova() helper with range invalidation. This uses the new fields passed in the NH_VA and NH_VAA commands: the size of the range, the level and the granule. As NH_VA and NH_VAA both use those fields, their decoding and handling is factorized in a new smmuv3_s1_range_inval() helper. Signed-off-by: Eric Auger <eric.auger@redhat.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20200728150815.11446-8-eric.auger@redhat.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* hw/arm/smmuv3: Introduce smmuv3_s1_range_inval() helperEric Auger2020-08-242-21/+18Star
| | | | | | | | | | | | | | | | | | Let's introduce an helper for S1 IOVA range invalidation. This will be used for NH_VA and NH_VAA commands. It decodes the same fields, trace, calls the UNMAP notifiers and invalidate the corresponding IOTLB entries. At the moment, we do not support 3.2 range invalidation yet. So it reduces to a single IOVA invalidation. Note the leaf bit now is also decoded for the CMD_TLBI_NH_VAA command. At the moment it is only used for tracing. Signed-off-by: Eric Auger <eric.auger@redhat.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20200728150815.11446-7-eric.auger@redhat.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* hw/arm/smmu-common: Manage IOTLB block entriesEric Auger2020-08-244-22/+60
| | | | | | | | | | | | | | | | | | | | | | At the moment each entry in the IOTLB corresponds to a page sized mapping (4K, 16K or 64K), even if the page belongs to a mapped block. In case of block mapping this unefficiently consumes IOTLB entries. Change the value of the entry so that it reflects the actual mapping it belongs to (block or page start address and size). Also the level/tg of the entry is encoded in the key. In subsequent patches we will enable range invalidation. This latter is able to provide the level/tg of the entry. Encoding the level/tg directly in the key will allow to invalidate using g_hash_table_remove() when num_pages equals to 1. Signed-off-by: Eric Auger <eric.auger@redhat.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20200728150815.11446-6-eric.auger@redhat.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* hw/arm/smmu: Introduce SMMUTLBEntry for PTW and IOTLB valueEric Auger2020-08-242-20/+22
| | | | | | | | | | | | | | Introduce a specialized SMMUTLBEntry to store the result of the PTW and cache in the IOTLB. This structure extends the generic IOMMUTLBEntry struct with the level of the entry and the granule size. Those latter will be useful when implementing range invalidation. Signed-off-by: Eric Auger <eric.auger@redhat.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20200728150815.11446-5-eric.auger@redhat.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* hw/arm/smmu: Introduce smmu_get_iotlb_key()Eric Auger2020-08-242-30/+37
| | | | | | | | | | | Introduce the smmu_get_iotlb_key() helper and the SMMU_IOTLB_ASID() macro. Also move smmu_get_iotlb_key and smmu_iotlb_key_hash in the IOTLB related code section. Signed-off-by: Eric Auger <eric.auger@redhat.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20200728150815.11446-4-eric.auger@redhat.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* hw/arm/smmu-common: Add IOTLB helpersEric Auger2020-08-243-26/+41
| | | | | | | | | | Add two helpers: one to lookup for a given IOTLB entry and one to insert a new entry. We also move the tracing there. Signed-off-by: Eric Auger <eric.auger@redhat.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20200728150815.11446-3-eric.auger@redhat.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* hw/arm/smmu-common: Factorize some code in smmu_ptw_64()Eric Auger2020-08-241-31/+17Star
| | | | | | | | | | | Page and block PTE decoding can share some code. Let's first handle table PTE and factorize some code shared by page and block PTEs. Signed-off-by: Eric Auger <eric.auger@redhat.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20200728150815.11446-2-eric.auger@redhat.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* Merge remote-tracking branch 'remotes/philmd-gitlab/tags/sd-next-20200821' ↵Peter Maydell2020-08-235-18/+95
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | into staging SD/MMC patches - Convert legacy SD host controller to the SDBus API - Move legacy API to a separate "sdcard_legacy.h" header - Introduce methods to access multiple bytes on SDBus data lines - Fix 'switch function' group location - Fix SDSC maximum card size (2GB) CI jobs result: https://gitlab.com/philmd/qemu/-/pipelines/180605963 # gpg: Signature made Fri 21 Aug 2020 18:27:50 BST # gpg: using RSA key FAABE75E12917221DCFD6BB2E3E32C2CDEADC0DE # gpg: Good signature from "Philippe Mathieu-Daudé (F4BUG) <f4bug@amsat.org>" [full] # Primary key fingerprint: FAAB E75E 1291 7221 DCFD 6BB2 E3E3 2C2C DEAD C0DE * remotes/philmd-gitlab/tags/sd-next-20200821: (23 commits) hw/sd: Correct the maximum size of a Standard Capacity SD Memory Card hw/sd: Fix incorrect populated function switch status data structure hw/sd: Use sdbus_read_data() instead of sdbus_read_byte() when possible hw/sd: Add sdbus_read_data() to read multiples bytes on the data line hw/sd: Use sdbus_write_data() instead of sdbus_write_byte when possible hw/sd: Add sdbus_write_data() to write multiples bytes on the data line hw/sd: Rename sdbus_read_data() as sdbus_read_byte() hw/sd: Rename sdbus_write_data() as sdbus_write_byte() hw/sd: Rename read/write_data() as read/write_byte() hw/sd: Move sdcard legacy API to 'hw/sd/sdcard_legacy.h' hw/sd/sdcard: Make sd_data_ready() static hw/sd/pl181: Replace disabled fprintf()s by trace events hw/sd/pl181: Do not create SD card within the SD host controller hw/sd/pl181: Expose a SDBus and connect the SDCard to it hw/sd/pl181: Use named GPIOs hw/sd/pl181: Add TODO to use Fifo32 API hw/sd/pl181: Rename pl181_send_command() as pl181_do_command() hw/sd/pl181: Replace fprintf(stderr, "*\n") with error_report() hw/sd/milkymist: Do not create SD card within the SD host controller hw/sd/milkymist: Create the SDBus at init() ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * hw/sd/pl181: Do not create SD card within the SD host controllerPhilippe Mathieu-Daudé2020-08-214-2/+60
| | | | | | | | | | | | | | | | | | | | | | | | SD/MMC host controllers provide a SD Bus to plug SD cards, but don't come with SD card plugged in :) Let the machine/board model create and plug the SD cards when required. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Acked-by: Peter Maydell <peter.maydell@linaro.org> Message-Id: <20200705204630.4133-8-f4bug@amsat.org>
| * hw/sd/pl181: Use named GPIOsPhilippe Mathieu-Daudé2020-08-213-6/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | To make the code easier to manage/review/use, rename the cardstatus[0] variable as 'card_readonly' and name the GPIO "card-read-only". Similarly with cardstatus[1], renamed as 'card_inserted' and name its GPIO "card-inserted". Adapt the users accordingly by using the qdev_init_gpio_out_named() function. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Acked-by: Peter Maydell <peter.maydell@linaro.org> Message-Id: <20200705204630.4133-6-f4bug@amsat.org>
| * hw/sd/pxa2xx_mmci: Do not create SD card within the SD host controllerPhilippe Mathieu-Daudé2020-08-211-10/+29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | SD/MMC host controllers provide a SD Bus to plug SD cards, but don't come with SD card plugged in :) The machine/board object is where the SD cards are created. Since the PXA2xx is not qdevified, for now create the cards in pxa270_init() which is the SoC model. In the future we will move this to the board model. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Acked-by: Peter Maydell <peter.maydell@linaro.org> Message-Id: <20200705213350.24725-2-f4bug@amsat.org>
* | Merge remote-tracking branch ↵Peter Maydell2020-08-221-1/+8
|\ \ | |/ |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 'remotes/ehabkost/tags/machine-next-pull-request' into staging Machine queue 2020-08-19 Regular post-release changes: * hw: add compat machines for 5.2 (Cornelia Huck) Features: * qmp: Expose MachineClass::default_ram_id (Michal Privoznik) Cleanups: * qdev: Document qdev_prop_set_drive_err() return value (Philippe Mathieu-Daudé) # gpg: Signature made Wed 19 Aug 2020 16:21:55 BST # gpg: using RSA key 5A322FD5ABC4D3DBACCFD1AA2807936F984DC5A6 # gpg: issuer "ehabkost@redhat.com" # gpg: Good signature from "Eduardo Habkost <ehabkost@redhat.com>" [full] # Primary key fingerprint: 5A32 2FD5 ABC4 D3DB ACCF D1AA 2807 936F 984D C5A6 * remotes/ehabkost/tags/machine-next-pull-request: hw: add compat machines for 5.2 qmp: Expose MachineClass::default_ram_id qdev: Document qdev_prop_set_drive_err() return value Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * hw: add compat machines for 5.2Cornelia Huck2020-08-191-1/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Add 5.2 machine types for arm/i440fx/q35/s390x/spapr. Reviewed-by: Andrew Jones <drjones@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Reviewed-by: Greg Kurz <groug@kaod.org> Acked-by: Christian Borntraeger <borntraeger@de.ibm.com> Acked-by: David Gibson <david@gibson.dropbear.id.au> Acked-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com> Message-Id: <20200819144016.281156-1-cohuck@redhat.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
* | meson: convert hw/arch*Marc-André Lureau2020-08-212-56/+59
| | | | | | | | | | | | | | | | Each architecture's sourceset is placed in an hw_arch dictionary, and picked up from there when building the per-emulator static_library. Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
* | trace: switch position of headers to what Meson requiresPaolo Bonzini2020-08-211-0/+1
|/ | | | | | | | | | | | | | | | | Meson doesn't enjoy the same flexibility we have with Make in choosing the include path. In particular the tracing headers are using $(build_root)/$(<D). In order to keep the include directives unchanged, the simplest solution is to generate headers with patterns like "trace/trace-audio.h" and place forwarding headers in the source tree such that for example "audio/trace.h" includes "trace/trace-audio.h". This patch is too ugly to be applied to the Makefiles now. It's only a way to separate the changes to the tracing header files from the Meson rewrite of the tracing logic. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
* hw/arm/nrf51_soc: Set system_clock_scalePeter Maydell2020-08-031-0/+5
| | | | | | | | | | | | | | | | | | The nrf51 SoC model wasn't setting the system_clock_scale global.which meant that if guest code used the systick timer in "use the processor clock" mode it would hang because time never advances. Set the global to match the documented CPU clock speed for this SoC. This SoC in fact doesn't have a SysTick timer (which is the only thing currently that cares about the system_clock_scale), because it's a configurable option in the Cortex-M0. However our Cortex-M0 and thus our nrf51 and our micro:bit board do provide a SysTick, so we ought to provide a functional one rather than a broken one. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-id: 20200727193458.31250-1-peter.maydell@linaro.org
* msf2-soc, stellaris: Don't wire up SYSRESETREQPeter Maydell2020-08-032-23/+0Star
| | | | | | | | | | | | | The MSF2 SoC model and the Stellaris board code both wire SYSRESETREQ up to a function that just invokes qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET); This is now the default action that the NVIC does if the line is not connected, so we can delete the handling code. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20200728103744.6909-4-peter.maydell@linaro.org
* hw/arm/netduino2, netduinoplus2: Set system_clock_scalePeter Maydell2020-08-032-0/+20
| | | | | | | | | | | | | | | | The netduino2 and netduinoplus2 boards forgot to set the system_clock_scale global, which meant that if guest code used the systick timer in "use the processor clock" mode it would hang because time never advances. Set the global to match the documented CPU clock speed of these boards. Judging by the data sheet this is slightly simplistic because the SoC allows configuration of the SYSCLK source and frequency via the RCC (reset and clock control) module, but we don't model that. Fixes: https://bugs.launchpad.net/qemu/+bug/1876187 Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20200727162617.26227-1-peter.maydell@linaro.org
* hw/arm/boot: Fix MTE for EL3 direct kernel bootRichard Henderson2020-07-271-0/+3
| | | | | | | | | | | | When booting an EL3 cpu with -kernel, we set up EL3 and then drop down to EL2. We need to enable access to v8.5-MemTag tag allocation at EL3 before doing so. Reported-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20200724163853.504655-3-richard.henderson@linaro.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* hw/arm/boot: Fix PAUTH for EL3 direct kernel bootRichard Henderson2020-07-271-0/+3
| | | | | | | | | | | When booting an EL3 cpu with -kernel, we set up EL3 and then drop down to EL2. We need to enable access to v8.3-PAuth keys and instructions at EL3 before doing so. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20200724163853.504655-2-richard.henderson@linaro.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* hw: Only compile the usb-dwc2 controller if it is really neededThomas Huth2020-07-241-0/+1
| | | | | | | | | | | | | | The USB_DWC2 switch is currently "default y", so it is included in all qemu-system-* builds, even if it is not needed. Even worse, it does a "select USB", so USB devices are now showing up as available on targets that do not support USB at all. This sysbus device should only be included by the boards that need it, i.e. by the Raspi machines. Fixes: 153ef1662c ("dwc-hsotg (dwc2) USB host controller emulation") Signed-off-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Paul Zimmerman <pauldzim@gmail.com> Message-id: 20200722154719.10130-1-thuth@redhat.com Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
* Merge remote-tracking branch 'remotes/armbru/tags/pull-qom-2020-07-21' into ↵Peter Maydell2020-07-211-4/+2Star
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | staging QOM patches for 2020-07-21 # gpg: Signature made Tue 21 Jul 2020 16:40:27 BST # gpg: using RSA key 354BC8B3D7EB2A6B68674E5F3870B400EB918653 # gpg: issuer "armbru@redhat.com" # gpg: Good signature from "Markus Armbruster <armbru@redhat.com>" [full] # gpg: aka "Markus Armbruster <armbru@pond.sub.org>" [full] # Primary key fingerprint: 354B C8B3 D7EB 2A6B 6867 4E5F 3870 B400 EB91 8653 * remotes/armbru/tags/pull-qom-2020-07-21: qom: Make info qom-tree sort children more efficiently qom: Document object_get_canonical_path() returns malloced string qom: Change object_get_canonical_path_component() not to malloc Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * qom: Change object_get_canonical_path_component() not to mallocMarkus Armbruster2020-07-211-4/+2Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | object_get_canonical_path_component() returns a malloced copy of a property name on success, null on failure. 19 of its 25 callers immediately free the returned copy. Change object_get_canonical_path_component() to return the property name directly. Since modifying the name would be wrong, adjust the return type to const char *. Drop the free from the 19 callers become simpler, add the g_strdup() to the other six. Signed-off-by: Markus Armbruster <armbru@redhat.com> Message-Id: <20200714160202.3121879-4-armbru@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Li Qiang <liq3ea@gmail.com>
* | hw: Mark nd_table[] misuse in realize methods FIXMEMarkus Armbruster2020-07-213-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | nd_table[] contains NIC configuration for boards to pick up. Device code has no business looking there. Several devices do it anyway. Two of them already have a suitable FIXME comment: "allwinner-a10" and "msf2-soc". Copy it to the others: "allwinner-h3", "xlnx-versal", "xlnx,zynqmp", "sparc32-ledma", "riscv.sifive.u.soc". Signed-off-by: Markus Armbruster <armbru@redhat.com> Message-Id: <20200715140440.3540942-3-armbru@redhat.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Niek Linnenbank <nieklinnenbank@gmail.com> Reviewed-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
* | msf2: Unbreak device-list-properties for "msf-soc"Markus Armbruster2020-07-211-4/+5
|/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Watch this: $ qemu-system-aarch64 -M ast2600-evb -S -display none -qmp stdio {"QMP": {"version": {"qemu": {"micro": 50, "minor": 0, "major": 5}, "package": "v5.0.0-2464-g3a9163af4e"}, "capabilities": ["oob"]}} {"execute": "qmp_capabilities"} {"return": {}} {"execute": "device-list-properties", "arguments": {"typename": "msf2-soc"}} Unsupported NIC model: ftgmac100 armbru@dusky:~/work/images$ echo $? 1 This is what breaks "make check SPEED=slow". Root cause is m2sxxx_soc_initfn()'s messing with nd_table[] via qemu_check_nic_model(). That's wrong. We fixed the exact same bug for device "allwinner-a10" in commit 8aabc5437b "hw/arm/allwinner-a10: Do not use nd_table in instance_init function". Fix this instance the same way: move the offending code to m2sxxx_soc_realize(), where it's less wrong, and add a FIXME comment. Fixes: 05b7374a58 ("msf2: Add EMAC block to SmartFusion2 SoC") Signed-off-by: Markus Armbruster <armbru@redhat.com> Message-Id: <20200715140440.3540942-2-armbru@redhat.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
* hw/arm/armsse: Assert info->num_cpus is in-bounds in armsse_realize()Peter Maydell2020-07-201-0/+2
| | | | | | | | | | | | | | | | | In armsse_realize() we have a loop over [0, info->num_cpus), which indexes into various fixed-size arrays in the ARMSSE struct. This confuses Coverity, which warns that we might overrun those arrays (CID 1430326, 1430337, 1430371, 1430414, 1430430). This can't actually happen, because the info struct is always one of the entries in the armsse_variants[] array and num_cpus is either 1 or 2; we also already assert in armsse_init() that num_cpus is not too large. However, adding an assert to armsse_realize() like the one in armsse_init() should help Coverity figure out that these code paths aren't possible. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-id: 20200713143716.9881-1-peter.maydell@linaro.org
* hw/arm/virt: Disable memory hotplug when MTE is enabledRichard Henderson2020-07-201-0/+5
| | | | | | | | | | | | | When MTE is enabled, tag memory must exist for all RAM. It might be possible to simultaneously hot plug tag memory alongside the corresponding normal memory, but for now just disable hotplug. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20200713213341.590275-4-richard.henderson@linaro.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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