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* Merge remote-tracking branch 'remotes/mst/tags/for_upstream' into stagingPeter Maydell2019-11-071-7/+120
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | virtio, pci: fixes A couple of bugfixes. Signed-off-by: Michael S. Tsirkin <mst@redhat.com> # gpg: Signature made Wed 06 Nov 2019 12:00:19 GMT # gpg: using RSA key 281F0DB8D28D5469 # gpg: Good signature from "Michael S. Tsirkin <mst@kernel.org>" [full] # gpg: aka "Michael S. Tsirkin <mst@redhat.com>" [full] # Primary key fingerprint: 0270 606B 6F3C DF3D 0B17 0970 C350 3912 AFBE 8E67 # Subkey fingerprint: 5D09 FD08 71C8 F85B 94CA 8A0D 281F 0DB8 D28D 5469 * remotes/mst/tags/for_upstream: virtio: notify virtqueue via host notifier when available hw/i386: AMD-Vi IVRS DMA alias support pci: Use PCI aliases when determining device IOMMU address space Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * hw/i386: AMD-Vi IVRS DMA alias supportAlex Williamson2019-11-051-7/+120
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When we account for DMA aliases in the PCI address space, we can no longer use a single IVHD entry in the IVRS covering all devices. We instead need to walk the PCI bus and create alias ranges when we find a conventional bus. These alias ranges cannot overlap with a "Select All" range (as currently implemented), so we also need to enumerate each device with IVHD entries. Importantly, the IVHD entries used here include a Device ID, which is simply the PCI BDF (Bus/Device/Function). The guest firmware is responsible for programming bus numbers, so the final revision of this table depends on the update mechanism (acpi_build_update) to be called after guest PCI enumeration. For an example guest configuration of: -+-[0000:40]---00.0-[41]----00.0 Intel Corporation 82574L Gigabit Network Connection \-[0000:00]-+-00.0 Intel Corporation 82G33/G31/P35/P31 Express DRAM Controller +-01.0 Device 1234:1111 +-02.0-[01]----00.0 Intel Corporation 82574L Gigabit Network Connection +-02.1-[02]----00.0 Red Hat, Inc. QEMU XHCI Host Controller +-02.2-[03]-- +-02.3-[04]-- +-02.4-[05]-- +-02.5-[06-09]----00.0-[07-09]--+-00.0-[08]-- | \-01.0-[09]----00.0 Intel Corporation 82574L Gigabit Network Connection +-02.6-[0a-0c]----00.0-[0b-0c]--+-01.0-[0c]-- | \-03.0 Intel Corporation 82540EM Gigabit Ethernet Controller +-02.7-[0d]----0e.0 Intel Corporation 82540EM Gigabit Ethernet Controller +-03.0 Red Hat, Inc. QEMU PCIe Expander bridge +-04.0 Advanced Micro Devices, Inc. [AMD] Device 0020 +-1f.0 Intel Corporation 82801IB (ICH9) LPC Interface Controller +-1f.2 Intel Corporation 82801IR/IO/IH (ICH9R/DO/DH) 6 port SATA Controller [AHCI mode] \-1f.3 Intel Corporation 82801I (ICH9 Family) SMBus Controller Where we have: 00:02.7 PCI bridge: Intel Corporation 82801 PCI Bridge (dmi-to-pci-bridge) 00:03.0 Host bridge: Red Hat, Inc. QEMU PCIe Expander bridge (pcie-expander-bus) 06:00.0 PCI bridge: Texas Instruments XIO3130 PCI Express Switch (Upstream) (pcie-switch-upstream-port) 07:00.0 PCI bridge: Texas Instruments XIO3130 PCI Express Switch (Downstream) (pcie-switch-downstream-port) 07:01.0 PCI bridge: Texas Instruments XIO3130 PCI Express Switch (Downstream) (pcie-switch-downstream-port) 0a:00.0 PCI bridge: Red Hat, Inc. Device 000e (pcie-to-pci-bridge) The following IVRS table is produced: AMD-Vi: Using IVHD type 0x10 AMD-Vi: device: 00:04.0 cap: 0040 seg: 0 flags: d1 info 0000 AMD-Vi: mmio-addr: 00000000fed80000 AMD-Vi: DEV_SELECT devid: 40:00.0 flags: 00 AMD-Vi: DEV_SELECT_RANGE_START devid: 41:00.0 flags: 00 AMD-Vi: DEV_RANGE_END devid: 41:1f.7 AMD-Vi: DEV_SELECT devid: 00:00.0 flags: 00 AMD-Vi: DEV_SELECT devid: 00:01.0 flags: 00 AMD-Vi: DEV_SELECT devid: 00:02.0 flags: 00 AMD-Vi: DEV_SELECT_RANGE_START devid: 01:00.0 flags: 00 AMD-Vi: DEV_RANGE_END devid: 01:1f.7 AMD-Vi: DEV_SELECT devid: 00:02.1 flags: 00 AMD-Vi: DEV_SELECT_RANGE_START devid: 02:00.0 flags: 00 AMD-Vi: DEV_RANGE_END devid: 02:1f.7 AMD-Vi: DEV_SELECT devid: 00:02.2 flags: 00 AMD-Vi: DEV_SELECT_RANGE_START devid: 03:00.0 flags: 00 AMD-Vi: DEV_RANGE_END devid: 03:1f.7 AMD-Vi: DEV_SELECT devid: 00:02.3 flags: 00 AMD-Vi: DEV_SELECT_RANGE_START devid: 04:00.0 flags: 00 AMD-Vi: DEV_RANGE_END devid: 04:1f.7 AMD-Vi: DEV_SELECT devid: 00:02.4 flags: 00 AMD-Vi: DEV_SELECT_RANGE_START devid: 05:00.0 flags: 00 AMD-Vi: DEV_RANGE_END devid: 05:1f.7 AMD-Vi: DEV_SELECT devid: 00:02.5 flags: 00 AMD-Vi: DEV_SELECT devid: 06:00.0 flags: 00 AMD-Vi: DEV_SELECT devid: 07:00.0 flags: 00 AMD-Vi: DEV_SELECT_RANGE_START devid: 08:00.0 flags: 00 AMD-Vi: DEV_RANGE_END devid: 08:1f.7 AMD-Vi: DEV_SELECT devid: 07:01.0 flags: 00 AMD-Vi: DEV_SELECT_RANGE_START devid: 09:00.0 flags: 00 AMD-Vi: DEV_RANGE_END devid: 09:1f.7 AMD-Vi: DEV_SELECT devid: 00:02.6 flags: 00 AMD-Vi: DEV_SELECT devid: 0a:00.0 flags: 00 AMD-Vi: DEV_ALIAS_RANGE devid: 0b:00.0 flags: 00 devid_to: 0b:00.0 AMD-Vi: DEV_RANGE_END devid: 0c:1f.7 AMD-Vi: DEV_SELECT devid: 00:02.7 flags: 00 AMD-Vi: DEV_ALIAS_RANGE devid: 0d:00.0 flags: 00 devid_to: 00:02.7 AMD-Vi: DEV_RANGE_END devid: 0d:1f.7 AMD-Vi: DEV_SELECT devid: 00:03.0 flags: 00 AMD-Vi: DEV_SELECT devid: 00:04.0 flags: 00 AMD-Vi: DEV_SELECT devid: 00:1f.0 flags: 00 AMD-Vi: DEV_SELECT devid: 00:1f.2 flags: 00 AMD-Vi: DEV_SELECT devid: 00:1f.3 flags: 00 Reviewed-by: Peter Xu <peterx@redhat.com> Signed-off-by: Alex Williamson <alex.williamson@redhat.com> Message-Id: <157187084880.5439.16700585779699233836.stgit@gimli.home> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
* | hw/pci-host/i440fx: Remove the last PIIX3 tracesPhilippe Mathieu-Daudé2019-11-051-1/+7
| | | | | | | | | | | | | | | | | | | | The PIIX3 is not tied to the i440FX and can even be used without it. Move its creation to the machine code (pc_piix.c). We have now removed the last trace of southbridge code in the i440FX northbridge. Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
* | hw/pci-host: Rename incorrectly named 'piix' as 'i440fx'Philippe Mathieu-Daudé2019-11-051-1/+1
| | | | | | | | | | | | | | | | | | We moved all the PIIX3 southbridge code out of hw/pci-host/piix.c, it now only contains i440FX northbridge code. Rename it to match the chipset modelled. Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
* | hw/pci-host/piix: Extract PIIX3 functions to hw/isa/piix3.cPhilippe Mathieu-Daudé2019-11-051-0/+1
| | | | | | | | | | | | | | Move all the PIIX3 functions to a new file: hw/isa/piix3.c. Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
* | hw/pci-host/piix: Move i440FX declarations to hw/pci-host/i440fx.hPhilippe Mathieu-Daudé2019-11-051-0/+1
| | | | | | | | | | | | | | | | | | The hw/pci-host/piix.c contains a mix of PIIX3 and i440FX chipsets functions. To be able to split it, we need to export some declarations first. Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
* | hw/pci-host/piix: Define and use the PIIX IRQ Route Control RegistersPhilippe Mathieu-Daudé2019-11-051-2/+3
| | | | | | | | | | | | | | | | | | | | The IRQ Route Control registers definitions belong to the PIIX chipset. We were only defining the 'A' register. Define the other B, C and D registers, and use them. Acked-by: Paul Durrant <paul@xen.org> Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
* | hw/pci-host/piix: Move RCR_IOPORT register definitionPhilippe Mathieu-Daudé2019-11-051-1/+1
| | | | | | | | | | | | | | | | The RCR_IOPORT register belongs to the PIIX chipset. Move the definition to "piix.h", and prepend the PIIX prefix. Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
* | piix4: Add a MC146818 RTC Controller as specified in datasheetPhilippe Mathieu-Daudé2019-11-052-2/+2
|/ | | | | | | | | | | | Remove mc146818rtc instanciated in malta board, to not have it twice. Acked-by: Michael S. Tsirkin <mst@redhat.com> Acked-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Hervé Poussineau <hpoussin@reactos.org> Message-Id: <20171216090228.28505-13-hpoussin@reactos.org> [PMD: rebased, set RTC base_year to 2000] Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
* i386: implement IGNNEPaolo Bonzini2019-10-261-1/+1
| | | | | | | | | | | Change the handling of port F0h writes and FPU exceptions to implement IGNNE. The implementation mixes a bit what the chipset and processor do in real hardware, but the effect is the same as what happens with actual FERR# and IGNNE# pins: writing to port F0h asserts IGNNE# in addition to lowering FP_IRQ; while clearing the SE bit in the FPU status word deasserts IGNNE#. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
* target/i386: move FERR handling to target/i386Paolo Bonzini2019-10-263-16/+9Star
| | | | | | | | Move it out of pc.c since it is strictly tied to TCG. This is almost exclusively code movement, the next patch will implement IGNNE. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
* Merge commit 'df84f17' into HEADPaolo Bonzini2019-10-2612-873/+1571
|\ | | | | | | | | | | This merge fixes a semantic conflict with the trivial tree. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
| * hw/i386/pc: Remove kvm_i386.h includePhilippe Mathieu-Daudé2019-10-242-2/+0Star
| | | | | | | | | | | | | | | | | | | | By extracting pc_gsi_create() and pc_i8259_create() we removed the access to "kvm_i386.h" from the machine code. We can now remove it. Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-Id: <20191015162705.28087-25-philmd@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
| * hw/i386/pc: Extract pc_i8259_create()Philippe Mathieu-Daudé2019-10-243-25/+21Star
| | | | | | | | | | | | | | | | | | The i8259 creation code is common to all PC machines, extract the common code. Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-Id: <20191018135910.24286-5-philmd@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
| * hw/i386/pc: Move gsi_state creation codePhilippe Mathieu-Daudé2019-10-241-3/+3
| | | | | | | | | | | | | | | | | | | | The code block related to IRQ starts few lines later. Move the comment and the pc_gsi_create() invocation where we start to use the IRQs. Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-Id: <20191018135910.24286-4-philmd@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
| * hw/i386/pc: Extract pc_gsi_create()Philippe Mathieu-Daudé2019-10-243-16/+17
| | | | | | | | | | | | | | | | | | | | | | The GSI creation code is common to all PC machines, extract the common code. Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com> Reviewed-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-Id: <20191018135910.24286-2-philmd@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
| * hw/i386: Introduce the microvm machine typeSergio Lopez2019-10-223-0/+583
| | | | | | | | | | | | | | | | | | | | | | | | | | microvm is a machine type inspired by Firecracker and constructed after its machine model. It's a minimalist machine type without PCI nor ACPI support, designed for short-lived guests. microvm also establishes a baseline for benchmarking and optimizing both QEMU and guest operating systems, since it is optimized for both boot time and footprint. Signed-off-by: Sergio Lopez <slp@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
| * hw/i386: make x86.c independent from PCMachineStateSergio Lopez2019-10-224-36/+35Star
| | | | | | | | | | | | | | | | | | | | | | | | As a last step into splitting PCMachineState and deriving X86MachineState from it, make the functions previously extracted from pc.c to x86.c independent from PCMachineState, using X86MachineState instead. Signed-off-by: Sergio Lopez <slp@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
| * hw/i386: split PCMachineState deriving X86MachineState from itPaolo Bonzini2019-10-228-199/+260
| | | | | | | | | | | | | | | | | | | | | | Split up PCMachineState and PCMachineClass and derive X86MachineState and X86MachineClass from them. This allows sharing code with non-PC x86 machine types. Signed-off-by: Sergio Lopez <slp@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
| * hw/i386/pc: move shared x86 functions to x86.c and export themSergio Lopez2019-10-226-641/+695
| | | | | | | | | | | | | | | | | | | | | | Move x86 functions that will be shared between PC and non-PC machine types to x86.c, along with their helpers. Signed-off-by: Sergio Lopez <slp@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Stefano Garzarella <sgarzare@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
| * hw/i386/pc: remove commented out code from x86_load_linux()Sergio Lopez2019-10-221-13/+0Star
| | | | | | | | | | | | | | | | Follow checkpatch.pl recommendation and remove commented out code from x86_load_linux(). Signed-off-by: Sergio Lopez <slp@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
| * hw/i386/pc: avoid an assignment in if condition in x86_load_linux()Sergio Lopez2019-10-221-1/+8
| | | | | | | | | | | | | | | | Follow checkpatch.pl recommendation and avoid an assignment in if condition in x86_load_linux(). Signed-off-by: Sergio Lopez <slp@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
| * hw/i386/pc: replace use of strtol with qemu_strtoui in x86_load_linux()Sergio Lopez2019-10-221-1/+8
| | | | | | | | | | | | | | | | | | Follow checkpatch.pl recommendation and replace the use of strtol with qemu_strtoui in x86_load_linux(). Signed-off-by: Sergio Lopez <slp@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com>
| * hw/i386/pc: fix code style issues on functions that will be moved outSergio Lopez2019-10-221-24/+29
| | | | | | | | | | | | | | | | | | Fix code style issues detected by checkpatch.pl on functions that will be moved out to x86.c. Signed-off-by: Sergio Lopez <slp@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com>
| * hw/i386/pc: rename functions shared with non-PC machinesSergio Lopez2019-10-224-19/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The following functions are named *pc* but are not PC-machine specific but generic to the X86 architecture, rename them: load_linux -> x86_load_linux pc_new_cpu -> x86_new_cpu pc_cpus_init -> x86_cpus_init pc_cpu_index_to_props -> x86_cpu_index_to_props pc_get_default_cpu_node_id -> x86_get_default_cpu_node_id pc_possible_cpu_arch_ids -> x86_possible_cpu_arch_ids old_pc_system_rom_init -> x86_system_rom_init Signed-off-by: Sergio Lopez <slp@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Stefano Garzarella <sgarzare@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
* | hw: Move MC146818 device from hw/timer/ to hw/rtc/ subdirectoryPhilippe Mathieu-Daudé2019-10-243-3/+3
|/ | | | | | | | | | | | | The MC146818 is a Real Time Clock, not a timer. Move it under the hw/rtc/ subdirectory. Use copyright statement from 80cabfad163 for "hw/rtc/mc146818rtc.h". Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Acked-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-Id: <20191003230404.19384-4-philmd@redhat.com> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
* Merge remote-tracking branch 'remotes/mst/tags/for_upstream' into stagingPeter Maydell2019-10-172-1/+9
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | virtio, vhost, acpi: features, fixes, tests ARM ACPI memory hotplug support + tests for new arm/virt ACPI tables. Virtio fs support (no migration). A vhost-user reconnect bugfix. Signed-off-by: Michael S. Tsirkin <mst@redhat.com> # gpg: Signature made Tue 15 Oct 2019 22:02:19 BST # gpg: using RSA key 281F0DB8D28D5469 # gpg: Good signature from "Michael S. Tsirkin <mst@kernel.org>" [full] # gpg: aka "Michael S. Tsirkin <mst@redhat.com>" [full] # Primary key fingerprint: 0270 606B 6F3C DF3D 0B17 0970 C350 3912 AFBE 8E67 # Subkey fingerprint: 5D09 FD08 71C8 F85B 94CA 8A0D 281F 0DB8 D28D 5469 * remotes/mst/tags/for_upstream: virtio: add vhost-user-fs-pci device virtio: add vhost-user-fs base device virtio: Add virtio_fs linux headers tests/acpi: add expected tables for arm/virt tests: document how to update acpi tables tests: Add bios tests to arm/virt tests: allow empty expected files tests/acpi: add empty files tests: Update ACPI tables list for upcoming arm/virt tests docs/specs: Add ACPI GED documentation hw/arm: Use GED for system_powerdown event hw/arm: Factor out powerdown notifier from GPIO hw/arm/virt-acpi-build: Add PC-DIMM in SRAT hw/arm/virt: Enable device memory cold/hot plug with ACPI boot hw/arm/virt: Add memory hotplug framework hw/acpi: Add ACPI Generic Event Device Support hw/acpi: Do not create memory hotplug method when handler is not defined hw/acpi: Make ACPI IO address space configurable vhost-user: save features if the char dev is closed Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * hw/acpi: Make ACPI IO address space configurableShameer Kolothum2019-10-052-1/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is in preparation for adding support for ARM64 platforms where it doesn't use port mapped IO for ACPI IO space. We are making changes so that MMIO region can be accommodated and board can pass the base address into the aml build function. Also move few MEMORY_* definitions to header so that other memory hotplug event signalling mechanisms (eg. Generic Event Device on HW-reduced acpi platforms) can use the same from their respective event handler code. Signed-off-by: Shameer Kolothum <shameerali.kolothum.thodi@huawei.com> Reviewed-by: Eric Auger <eric.auger@redhat.com> Reviewed-by: Igor Mammedov <imammedo@redhat.com> Message-Id: <20190918130633.4872-2-shameerali.kolothum.thodi@huawei.com> Acked-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
* | memory: allow memory_region_register_iommu_notifier() to failEric Auger2019-10-042-10/+15
|/ | | | | | | | | | | | | | | | | | | | Currently, when a notifier is attempted to be registered and its flags are not supported (especially the MAP one) by the IOMMU MR, we generally abruptly exit in the IOMMU code. The failure could be handled more nicely in the caller and especially in the VFIO code. So let's allow memory_region_register_iommu_notifier() to fail as well as notify_flag_changed() callback. All sites implementing the callback are updated. This patch does not yet remove the exit(1) in the amd_iommu code. in SMMUv3 we turn the warning message into an error message saying that the assigned device would not work properly. Signed-off-by: Eric Auger <eric.auger@redhat.com> Reviewed-by: Peter Xu <peterx@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
* pc: Add an SMB0 ACPI device to q35Corey Minyard2019-09-203-10/+26
| | | | | | | | | | | | | | | | This is so I2C devices can be found in the ACPI namespace. Currently that's only IPMI, but devices can be easily added now. Adding the devices required some PCI information, and the bus itself to be added to the PCMachineState structure. Note that this only works on Q35, the ACPI for PIIX4 is not capable of handling an SMBus device. Cc: Michael S. Tsirkin <mst@redhat.com> Cc: Igor Mammedov <imammedo@redhat.com> Signed-off-by: Corey Minyard <cminyard@mvista.com> Reviewed-by: Paolo Bonzini <pbonzini@redhat.com>
* ipmi: Fix SSIF ACPI handling to use the right CRSCorey Minyard2019-09-201-1/+1
| | | | | | | | Pass in the CRS so that it can be set to the SMBus for IPMI later. Cc: Michael S. Tsirkin <mst@redhat.com> Cc: Igor Mammedov <imammedo@redhat.com> Signed-off-by: Corey Minyard <cminyard@mvista.com>
* ipmi: Add an SMBus IPMI interfaceCorey Minyard2019-09-201-0/+1
| | | | Signed-off-by: Corey Minyard <cminyard@mvista.com>
* ipmi: Add PCI IPMI interfacesCorey Minyard2019-09-201-0/+2
| | | | | | | | | Pretty straightforward, just hook the current KCS and BT code into the PCI system with the proper configuration. Cc: Michael S. Tsirkin <mst@redhat.com> Cc: M: Marcel Apfelbaum <marcel.apfelbaum@gmail.com> Signed-off-by: Corey Minyard <cminyard@mvista.com>
* Merge remote-tracking branch 'remotes/mst/tags/for_upstream' into stagingPeter Maydell2019-09-172-6/+56
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | virtio,vhost,pc: features, fixes, cleanups. Virtio 1.0 support for virtio-mmio. Misc fixes, cleanups. Signed-off-by: Michael S. Tsirkin <mst@redhat.com> # gpg: Signature made Mon 16 Sep 2019 16:17:30 BST # gpg: using RSA key 281F0DB8D28D5469 # gpg: Good signature from "Michael S. Tsirkin <mst@kernel.org>" [full] # gpg: aka "Michael S. Tsirkin <mst@redhat.com>" [full] # Primary key fingerprint: 0270 606B 6F3C DF3D 0B17 0970 C350 3912 AFBE 8E67 # Subkey fingerprint: 5D09 FD08 71C8 F85B 94CA 8A0D 281F 0DB8 D28D 5469 * remotes/mst/tags/for_upstream: virtio-mmio: implement modern (v2) personality (virtio-1) virtio pmem: user document intel_iommu: Remove the caching-mode check during flag change pc/q35: Disallow vfio-pci hotplug without VT-d caching mode qdev/machine: Introduce hotplug_allowed hook intel_iommu: Sanity check vfio-pci config on machine init done backends/vhost-user.c: prevent using uninitialized vqs vhost-user-blk: prevent using uninitialized vqs docs/nvdimm: add example on persistent backend setup MAINTAINERS: update virtio-rng and virtio-serial maintainer Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * intel_iommu: Remove the caching-mode check during flag changePeter Xu2019-09-161-4/+0Star
| | | | | | | | | | | | | | | | | | | | | | | | That's never a good place to stop QEMU process... Since now we have both the machine done sanity check and also the hotplug handler, we can safely remove this to avoid that. Reviewed-by: Eric Auger <eric.auger@redhat.com> Signed-off-by: Peter Xu <peterx@redhat.com> Message-Id: <20190916080718.3299-5-peterx@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
| * pc/q35: Disallow vfio-pci hotplug without VT-d caching modePeter Xu2019-09-161-0/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Instead of bailing out when trying to hotplug a vfio-pci device with below configuration: -device intel-iommu,caching-mode=off With this we can return a warning message to the user via QMP/HMP and the VM will continue to work after failing the hotplug: (qemu) device_add vfio-pci,bus=root.3,host=05:00.0,id=vfio1 Error: Device assignment is not allowed without enabling caching-mode=on for Intel IOMMU. Reviewed-by: Eric Auger <eric.auger@redhat.com> Signed-off-by: Peter Xu <peterx@redhat.com> Message-Id: <20190916080718.3299-4-peterx@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
| * intel_iommu: Sanity check vfio-pci config on machine init donePeter Xu2019-09-161-3/+36
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This check was previously only happened when the IOMMU is enabled in the guest. It was always too late because the enabling of IOMMU normally only happens during the boot of guest OS. It means that we can bail out and exit directly during the guest OS boots if the configuration of devices are not supported. Or, if the guest didn't enable vIOMMU at all, then the user can use the guest normally but as long as it reconfigure the guest OS to enable the vIOMMU then reboot, the user will see the panic right after the reset when the next boot starts. Let's make this failure even earlier so that we force the user to use caching-mode for vfio-pci devices when with the vIOMMU. So the user won't get surprise at least during execution of the guest, which seems a bit nicer. This will affect some user who didn't enable vIOMMU in the guest OS but was using vfio-pci and the vtd device in the past. However I hope it's not a majority because not enabling vIOMMU with the device attached is actually meaningless. We still keep the old assertion for safety so far because the hotplug path could still reach it, so far. Reviewed-by: Eric Auger <eric.auger@redhat.com> Signed-off-by: Peter Xu <peterx@redhat.com> Message-Id: <20190916080718.3299-2-peterx@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
* | hw/i386/pc: Extract the x86 generic fw_cfg codePhilippe Mathieu-Daudé2019-09-163-131/+145
| | | | | | | | | | | | | | | | | | | | | | Extract all the functions that are not PC-machine specific into the (arch-specific) fw_cfg.c file. This will allow other X86-machine to reuse these functions. Suggested-by: Samuel Ortiz <sameo@linux.intel.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-Id: <20190818225414.22590-16-philmd@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
* | hw/i386/pc: Rename pc_build_feature_control() as generic fw_cfg_build_*Philippe Mathieu-Daudé2019-09-161-3/+3
| | | | | | | | | | | | | | | | | | | | | | Now that the pc_build_feature_control_file() function has been refactored to not depend of PC specific types, rename it to a more generic name. Suggested-by: Samuel Ortiz <sameo@linux.intel.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-Id: <20190818225414.22590-15-philmd@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
* | hw/i386/pc: Let pc_build_feature_control() take a MachineState argumentPhilippe Mathieu-Daudé2019-09-161-3/+2Star
| | | | | | | | | | | | | | | | | | | | Let the pc_build_feature_control_file() function take a generic MachineState argument. Suggested-by: Samuel Ortiz <sameo@linux.intel.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-Id: <20190818225414.22590-14-philmd@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
* | hw/i386/pc: Let pc_build_feature_control() take a FWCfgState argumentPhilippe Mathieu-Daudé2019-09-161-3/+4
| | | | | | | | | | | | | | | | | | | | Pass the FWCfgState object by argument, this will allow us to remove the PCMachineState argument later. Suggested-by: Samuel Ortiz <sameo@linux.intel.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-Id: <20190818225414.22590-13-philmd@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
* | hw/i386/pc: Rename pc_build_smbios() as generic fw_cfg_build_smbios()Philippe Mathieu-Daudé2019-09-161-2/+2
| | | | | | | | | | | | | | | | | | | | Now that the pc_build_smbios() function has been refactored to not depend of PC specific types, rename it to a more generic name. Suggested-by: Samuel Ortiz <sameo@linux.intel.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-Id: <20190818225414.22590-12-philmd@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
* | hw/i386/pc: Let pc_build_smbios() take a generic MachineState argumentPhilippe Mathieu-Daudé2019-09-161-3/+2Star
| | | | | | | | | | | | | | | | | | | | Let the pc_build_smbios() function take a generic MachineState argument. Suggested-by: Samuel Ortiz <sameo@linux.intel.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-Id: <20190818225414.22590-11-philmd@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
* | hw/i386/pc: Let pc_build_smbios() take a FWCfgState argumentPhilippe Mathieu-Daudé2019-09-161-5/+5
| | | | | | | | | | | | | | | | | | | | Pass the FWCfgState object by argument, this will allow us to remove the PCMachineState argument later. Suggested-by: Samuel Ortiz <sameo@linux.intel.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-Id: <20190818225414.22590-10-philmd@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
* | hw/i386/pc: Replace PCMachineState argument with MachineState in ↵Paolo Bonzini2019-09-161-4/+4
| | | | | | | | | | | | | | | | | | | | fw_cfg_arch_create In the previous commit we removed the last access to PCMachineState. Replace it with a generic MachineState argument and use it to retrieve the CPUArchIdList. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
* | hw/i386/pc: Pass the CPUArchIdList array by argumentPhilippe Mathieu-Daudé2019-09-161-10/+9Star
| | | | | | | | | | | | | | | | | | | | Pass the CPUArchIdList array by argument, this will allow us to remove the PCMachineState argument later. Suggested-by: Samuel Ortiz <sameo@linux.intel.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-Id: <20190818225414.22590-8-philmd@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
* | hw/i386/pc: Pass the apic_id_limit value by argumentPhilippe Mathieu-Daudé2019-09-161-2/+3
| | | | | | | | | | | | | | | | | | | | Pass the apic_id_limit value by argument, this will allow us to remove the PCMachineState argument later. Suggested-by: Samuel Ortiz <sameo@linux.intel.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-Id: <20190818225414.22590-7-philmd@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
* | hw/i386/pc: Pass the boot_cpus value by argumentPhilippe Mathieu-Daudé2019-09-161-3/+4
| | | | | | | | | | | | | | | | | | | | The boot_cpus is used once. Pass it by argument, this will allow us to remove the PCMachineState argument later. Suggested-by: Samuel Ortiz <sameo@linux.intel.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-Id: <20190818225414.22590-6-philmd@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
* | hw/i386/pc: Rename bochs_bios_init as more generic fw_cfg_arch_createPhilippe Mathieu-Daudé2019-09-161-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The bochs_bios_init() function is not restricted to the Bochs BIOS and is useful to other BIOS. Since it is not specific to the PC machine, and can be reused by other machines of the X86 architecture, rename it as fw_cfg_arch_create(). Suggested-by: Samuel Ortiz <sameo@linux.intel.com> Reviewed-by: Li Qiang <liq3ea@gmail.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-Id: <20190818225414.22590-5-philmd@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
* | hw/i386/pc: Use address_space_memory in placePhilippe Mathieu-Daudé2019-09-161-3/+4
| | | | | | | | | | | | | | | | | | | | | | The address_space_memory variable is used once. Use it in place and remove the argument. Suggested-by: Samuel Ortiz <sameo@linux.intel.com> Reviewed-by: Li Qiang <liq3ea@gmail.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-Id: <20190818225414.22590-4-philmd@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
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