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* heathrow: remove obsolete heathow_init() functionMark Cave-Ayland2018-04-271-18/+5Star
| | | | | | | Instead wire up heathrow to the CPU and grackle PCI host using qdev GPIOs. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
* target/arm: Fetch GICv3 state directly from CPUARMStateAaron Lindsay2018-04-261-8/+2Star
| | | | | | | | | | | This eliminates the need for fetching it from el_change_hook_opaque, and allows for supporting multiple el_change_hooks without having to hack something together to find the registered opaque belonging to GICv3. Signed-off-by: Aaron Lindsay <alindsay@codeaurora.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1523997485-1905-6-git-send-email-alindsay@codeaurora.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* hw/intc/arm_gicv3: Fix secure-GIC NS ICC_PMR and ICC_RPR accessesPeter Maydell2018-03-231-3/+3
| | | | | | | | | | | | | | | | | | | | | | If the GIC has the security extension support enabled, then a non-secure access to ICC_PMR must take account of the non-secure view of interrupt priorities, where real priorities 0x00..0x7f are secure-only and not visible to the non-secure guest, and priorities 0x80..0xff are shown to the guest as if they were 0x00..0xff. We had the logic here wrong: * on reads, the priority is in the secure range if bit 7 is clear, not if it is set * on writes, we want to set bit 7, not mask everything else Our ICC_RPR read code had the same error as ICC_PMR. (Compare the GICv3 spec pseudocode functions ICC_RPR_EL1 and ICC_PMR_EL1.) Fixes: https://bugs.launchpad.net/qemu/+bug/1748434 Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Andrew Jones <drjones@redhat.com> Message-id: 20180315133441.24149-1-peter.maydell@linaro.org
* openpic_kvm: drop address_space_to_flatview callPaolo Bonzini2018-03-061-4/+0Star
| | | | | | | | | | | | | | The MemoryListener is registered on address_space_memory, there is not much to assert. This currently works because the callback is invoked only once when the listener is registered, but section->fv is the _new_ FlatView, not the old one on later calls and that would break. This confines address_space_to_flatview to exec.c and memory.c. Acked-by: David Gibson <david@gibson.dropbear.id.au> Reviewed-by: Alexey Kardashevskiy <aik@ozlabs.ru> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
* openpic: move OpenPIC state and related definitions to openpic.hMark Cave-Ayland2018-03-061-157/+0Star
| | | | | | | | | This is to faciliate access to OpenPICState when wiring up the PIC to the macio controller. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
* openpic: move KVM-specific declarations into separate openpic_kvm.h fileMark Cave-Ayland2018-03-061-0/+1
| | | | | | | | | | This is needed before the next patch because the target-dependent kvm stub uses the existing kvm_openpic_connect_vcpu() declaration, making it impossible to move the device-specific declarations into the same file without breaking ppc-linux-user compilation. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
* heathrow: change heathrow_pic_init() to return the heathrow deviceMark Cave-Ayland2018-03-061-4/+6
| | | | | | | | | | | | | This enables the device to be made available during the setup of the Old World machine. In order to pass back the previous set of IRQs we temporarily introduce a new pic_irqs parameter until it can be removed. An additional benefit of this change is that it is also possible to remove the pic_mem pointer used for macio by accessing the memory region via sysbus. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
* heathrow: convert to trace-eventsMark Cave-Ayland2018-03-062-21/+16Star
| | | | | Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
* heathrow: QOMify heathrow PICMark Cave-Ayland2018-03-061-56/+70
| | | | | Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
* qmp: expose s390-specific CPU infoViktor Mihajlovski2018-02-261-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Presently s390x is the only architecture not exposing specific CPU information via QMP query-cpus. Upstream discussion has shown that it could make sense to report the architecture specific CPU state, e.g. to detect that a CPU has been stopped. With this change the output of query-cpus will look like this on s390: [ {"arch": "s390", "current": true, "props": {"core-id": 0}, "cpu-state": "operating", "CPU": 0, "qom_path": "/machine/unattached/device[0]", "halted": false, "thread_id": 63115}, {"arch": "s390", "current": false, "props": {"core-id": 1}, "cpu-state": "stopped", "CPU": 1, "qom_path": "/machine/unattached/device[1]", "halted": true, "thread_id": 63116} ] This change doesn't add the s390-specific data to HMP 'info cpus'. A follow-on patch will remove all architecture specific information from there. Signed-off-by: Viktor Mihajlovski <mihajlov@linux.vnet.ibm.com> Reviewed-by: David Hildenbrand <david@redhat.com> Reviewed-by: Christian Borntraeger <borntraeger@de.ibm.com> Reviewed-by: Eric Blake <eblake@redhat.com> Message-Id: <1518797321-28356-2-git-send-email-mihajlov@linux.vnet.ibm.com> Reviewed-by: Cornelia Huck <cohuck@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
* hw/intc/armv7m_nvic: Fix byte-to-interrupt number conversionsPeter Maydell2018-02-151-4/+4
| | | | | | | | | | | | | | | | | In many of the NVIC registers relating to interrupts, we have to convert from a byte offset within a register set into the number of the first interrupt which is affected. We were getting this wrong for: * reads of NVIC_ISPR<n>, NVIC_ISER<n>, NVIC_ICPR<n>, NVIC_ICER<n>, NVIC_IABR<n> -- in all these cases we were missing the "* 8" needed to convert from the byte offset to the interrupt number (since all these registers use one bit per interrupt) * writes of NVIC_IPR<n> had the opposite problem of a spurious "* 8" (since these registers use one byte per interrupt) Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-id: 20180209165810.6668-9-peter.maydell@linaro.org
* hw/intc/armv7m_nvic: Implement SCRPeter Maydell2018-02-151-4/+8
| | | | | | | | | | | We were previously making the system control register (SCR) just RAZ/WI. Although we don't implement the functionality this register controls, we should at least provide the state, including the banked state for v8M. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20180209165810.6668-7-peter.maydell@linaro.org
* hw/intc/armv7m_nvic: Implement cache ID registersPeter Maydell2018-02-151-0/+16
| | | | | | | | | | | | | | | | | | | | | | | | M profile cores have a similar setup for cache ID registers to A profile: * Cache Level ID Register (CLIDR) is a fixed value * Cache Type Register (CTR) is a fixed value * Cache Size ID Registers (CCSIDR) are a bank of registers; which one you see is selected by the Cache Size Selection Register (CSSELR) The only difference is that they're in the NVIC memory mapped register space rather than being coprocessor registers. Implement the M profile view of them. Since neither Cortex-M3 nor Cortex-M4 implement caches, we don't need to update their init functions and can leave the ctr/clidr/ccsidr[] fields in their ARMCPU structs at zero. Newer cores (like the Cortex-M33) will want to be able to set these ID registers to non-zero values, though. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20180209165810.6668-6-peter.maydell@linaro.org
* hw/intc/armv7m_nvic: Implement v8M CPPWR registerPeter Maydell2018-02-151-0/+14
| | | | | | | | | | | | | The Coprocessor Power Control Register (CPPWR) is new in v8M. It allows software to control whether coprocessors are allowed to power down and lose their state. QEMU doesn't have any notion of power control, so we choose the IMPDEF option of making the whole register RAZ/WI (indicating that no coprocessors can ever power down and lose state). Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20180209165810.6668-5-peter.maydell@linaro.org
* hw/intc/armv7m_nvic: Implement M profile cache maintenance opsPeter Maydell2018-02-151-0/+12
| | | | | | | | | | | | For M profile cores, cache maintenance operations are done by writing to special registers in the system register space. For QEMU, cache operations are always NOPs, since we don't implement the cache. Implementing these explicitly avoids a spurious LOG_GUEST_ERROR when the guest uses them. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20180209165810.6668-4-peter.maydell@linaro.org
* hw/intc/armv7m_nvic: Fix ICSR PENDNMISET/CLR handlingPeter Maydell2018-02-151-3/+3
| | | | | | | | | | | | The PENDNMISET/CLR bits in the ICSR should be RAZ/WI from NonSecure state if the AIRCR.BFHFNMINS bit is zero. We had misimplemented this as making the bits RAZ/WI from both Secure and NonSecure states. Fix this bug by checking attrs.secure so that Secure code can pend and unpend NMIs. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20180209165810.6668-3-peter.maydell@linaro.org
* hw/intc/armv7m_nvic: Don't hardcode M profile ID registers in NVICPeter Maydell2018-02-151-14/+16
| | | | | | | | | | | | | | | | | Instead of hardcoding the values of M profile ID registers in the NVIC, use the fields in the CPU struct. This will allow us to give different M profile CPU types different ID register values. This commit includes the addition of the missing ID_ISAR5, which exists as RES0 in both v7M and v8M. (The values of the ID registers might be wrong for the M4 -- this commit leaves the behaviour there unchanged.) Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20180209165810.6668-2-peter.maydell@linaro.org
* Merge remote-tracking branch 'remotes/armbru/tags/pull-misc-2018-02-07-v4' ↵Peter Maydell2018-02-092-2/+0Star
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | into staging Miscellaneous patches for 2018-02-07 # gpg: Signature made Fri 09 Feb 2018 12:52:51 GMT # gpg: using RSA key 3870B400EB918653 # gpg: Good signature from "Markus Armbruster <armbru@redhat.com>" # gpg: aka "Markus Armbruster <armbru@pond.sub.org>" # Primary key fingerprint: 354B C8B3 D7EB 2A6B 6867 4E5F 3870 B400 EB91 8653 * remotes/armbru/tags/pull-misc-2018-02-07-v4: Move include qemu/option.h from qemu-common.h to actual users Drop superfluous includes of qapi/qmp/qjson.h Drop superfluous includes of qapi/qmp/dispatch.h Include qapi/qmp/qnull.h exactly where needed Include qapi/qmp/qnum.h exactly where needed Include qapi/qmp/qbool.h exactly where needed Include qapi/qmp/qstring.h exactly where needed Include qapi/qmp/qdict.h exactly where needed Include qapi/qmp/qlist.h exactly where needed Include qapi/qmp/qobject.h exactly where needed qdict qlist: Make most helper macros functions Eliminate qapi/qmp/types.h Typedef the subtypes of QObject in qemu/typedefs.h, too Include qmp-commands.h exactly where needed Drop superfluous includes of qapi/qmp/qerror.h Include qapi/error.h exactly where needed Drop superfluous includes of qapi-types.h and test-qapi-types.h Clean up includes Use #include "..." for our own headers, <...> for others vnc: use stubs for CONFIG_VNC=n dummy functions Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * Include qapi/error.h exactly where neededMarkus Armbruster2018-02-092-2/+0Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This cleanup makes the number of objects depending on qapi/error.h drop from 1910 (out of 4743) to 1612 in my "build everything" tree. While there, separate #include from file comment with a blank line, and drop a useless comment on why qemu/osdep.h is included first. Reviewed-by: Eric Blake <eblake@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Markus Armbruster <armbru@redhat.com> Message-Id: <20180201111846.21846-5-armbru@redhat.com> [Semantic conflict with commit 34e304e975 resolved, OSX breakage fixed]
* | Merge remote-tracking branch ↵Peter Maydell2018-02-094-12/+218
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 'remotes/pmaydell/tags/pull-target-arm-20180209' into staging target-arm queue: * Support M profile derived exceptions on exception entry and exit * Implement AArch64 v8.2 crypto insns (SHA-512, SHA-3, SM3, SM4) * Implement working i.MX6 SD controller * Various devices preparatory to i.MX7 support * Preparatory patches for SVE emulation * v8M: Fix bug in implementation of 'TT' insn * Give useful error if user tries to use userspace GICv3 with KVM # gpg: Signature made Fri 09 Feb 2018 11:01:23 GMT # gpg: using RSA key 3C2525ED14360CDE # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" # gpg: aka "Peter Maydell <pmaydell@gmail.com>" # gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" # Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE * remotes/pmaydell/tags/pull-target-arm-20180209: (30 commits) hw/core/generic-loader: Allow PC to be set on command line target/arm/translate.c: Fix missing 'break' for TT insns target/arm/kvm: gic: Prevent creating userspace GICv3 with KVM target/arm: Add SVE state to TB->FLAGS target/arm: Add ZCR_ELx target/arm: Add SVE to migration state target/arm: Add predicate registers for SVE target/arm: Expand vector registers for SVE hw/arm: Move virt's PSCI DT fixup code to arm/boot.c usb: Add basic code to emulate Chipidea USB IP i.MX: Add implementation of i.MX7 GPR IP block i.MX: Add i.MX7 GPT variant i.MX: Add code to emulate GPCv2 IP block i.MX: Add code to emulate i.MX7 SNVS IP-block i.MX: Add code to emulate i.MX2 watchdog IP block i.MX: Add code to emulate i.MX7 CCM, PMU and ANALOG IP blocks hw: i.MX: Convert i.MX6 to use TYPE_IMX_USDHC sdhci: Add i.MX specific subtype of SDHCI target/arm: enable user-mode SHA-3, SM3, SM4 and SHA-512 instruction support target/arm: implement SM4 instructions ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * | i.MX: Add code to emulate GPCv2 IP blockAndrey Smirnov2018-02-092-1/+126
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add minimal code needed to allow upstream Linux guest to boot. Cc: Peter Maydell <peter.maydell@linaro.org> Cc: Jason Wang <jasowang@redhat.com> Cc: Philippe Mathieu-Daudé <f4bug@amsat.org> Cc: Marcel Apfelbaum <marcel.apfelbaum@zoho.com> Cc: Michael S. Tsirkin <mst@redhat.com> Cc: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Cc: yurovsky@gmail.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * | target/arm: Split "get pending exception info" from "acknowledge it"Peter Maydell2018-02-092-8/+25
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently armv7m_nvic_acknowledge_irq() does three things: * make the current highest priority pending interrupt active * return a bool indicating whether that interrupt is targeting Secure or NonSecure state * implicitly tell the caller which is the highest priority pending interrupt by setting env->v7m.exception We need to split these jobs, because v7m_exception_taken() needs to know whether the pending interrupt targets Secure so it can choose to stack callee-saves registers or not, but it must not make the interrupt active until after it has done that stacking, in case the stacking causes a derived exception. Similarly, it needs to know the number of the pending interrupt so it can read the correct vector table entry before the interrupt is made active, because vector table reads might also cause a derived exception. Create a new armv7m_nvic_get_pending_irq_info() function which simply returns information about the highest priority pending interrupt, and use it to rearrange the v7m_exception_taken() code so we don't acknowledge the exception until we've done all the things which could possibly cause a derived exception. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-id: 1517324542-6607-3-git-send-email-peter.maydell@linaro.org
| * | target/arm: Add armv7m_nvic_set_pending_derived()Peter Maydell2018-02-092-3/+67
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In order to support derived exceptions (exceptions generated in the course of trying to take an exception), we need to be able to handle prioritizing whether to take the original exception or the derived exception. We do this by introducing a new function armv7m_nvic_set_pending_derived() which the exception-taking code in helper.c will call when a derived exception occurs. Derived exceptions are dealt with mostly like normal pending exceptions, so we share the implementation with the armv7m_nvic_set_pending() function. Note that the way we structure this is significantly different from the v8M Arm ARM pseudocode: that does all the prioritization logic in the DerivedLateArrival() function, whereas we choose to let the existing "identify highest priority exception" logic do the prioritization for us. The effect is the same, though. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 1517324542-6607-2-git-send-email-peter.maydell@linaro.org
* | s390x/flic: cache the common flic class in a central functionDavid Hildenbrand2018-02-091-1/+12
| | | | | | | | | | | | | | | | This avoids tons of conversions when handling interrupts. Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20180129125623.21729-19-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
* | s390x/kvm: cache the kvm flic in a central functionDavid Hildenbrand2018-02-091-5/+16
| | | | | | | | | | | | | | | | | | This avoids tons of conversions when handling interrupts. Acked-by: Christian Borntraeger <borntraeger@de.ibm.com> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20180129125623.21729-18-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
* | s390x/tcg: cache the qemu flic in a central functionDavid Hildenbrand2018-02-091-6/+17
| | | | | | | | | | | | | | | | This avoids tons of conversions when handling interrupts. Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20180129125623.21729-17-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
* | s390x/flic: optimize CPU wakeup for TCGDavid Hildenbrand2018-02-091-2/+29
| | | | | | | | | | | | | | | | | | Kicking all CPUs on every floating interrupt is far from efficient. Let's optimize it at least a little bit. Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20180129125623.21729-12-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
* | s390x/flic: implement qemu_s390_clear_io_flic()David Hildenbrand2018-02-091-2/+29
| | | | | | | | | | | | | | | | | | Now that we have access to the io interrupts, we can implement clear_io_irq() for TCG. Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20180129125623.21729-11-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
* | s390x/flic: make floating interrupts on TCG actually floatingDavid Hildenbrand2018-02-091-10/+134
| | | | | | | | | | | | | | | | | | | | | | Move floating interrupt handling into the flic. Floating interrupts will now be considered by all CPUs, not just CPU #0. While at it, convert I/O interrupts to use a list and make sure we properly consider I/O sub-classes in s390_cpu_has_io_int(). Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20180129125623.21729-9-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
* | s390x/flic: no need to call s390_io_interrupt() from flicDavid Hildenbrand2018-02-091-1/+2
| | | | | | | | | | | | | | | | | | We can directly call the right function. Suggested-by: Cornelia Huck <cohuck@redhat.com> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20180129125623.21729-7-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
* | s390x/flic: factor out injection of floating interruptsDavid Hildenbrand2018-02-092-5/+89
| | | | | | | | | | | | | | | | | | | | | | | | | | Let the flic device handle it internally. This will allow us to later on store floating interrupts in the flic for the TCG case. This now also simplifies kvm.c. All that's left is the fallback interface for floating interrupts, which is now triggered directly via the flic in case anything goes wrong. Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20180129125623.21729-6-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
* | s390x/tcg: simplify lookup of flicDavid Hildenbrand2018-02-091-5/+3Star
| | | | | | | | | | | | | | | | We can simply search for an object of our common type. Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20180129125623.21729-4-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
* | s390x/flic: simplify flic initializationDavid Hildenbrand2018-02-092-14/+5Star
|/ | | | | | | | | This makes it clearer, which device is used for which accelerator. Reviewed-by: Christian Borntraeger <borntraeger@de.ibm.com> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20180129125623.21729-3-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
* qdev: use device_class_set_parent_realize/unrealize/reset()Philippe Mathieu-Daudé2018-02-056-16/+10Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | changes generated using the following Coccinelle patch: @@ type DeviceParentClass; DeviceParentClass *pc; DeviceClass *dc; identifier parent_fn; identifier child_fn; @@ ( +device_class_set_parent_realize(dc, child_fn, &pc->parent_fn); -pc->parent_fn = dc->realize; ... -dc->realize = child_fn; | +device_class_set_parent_unrealize(dc, child_fn, &pc->parent_fn); -pc->parent_fn = dc->unrealize; ... -dc->unrealize = child_fn; | +device_class_set_parent_reset(dc, child_fn, &pc->parent_fn); -pc->parent_fn = dc->reset; ... -dc->reset = child_fn; ) Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20180114020412.26160-4-f4bug@amsat.org> Reviewed-by: Marcel Apfelbaum <marcel@redhat.com> Acked-by: David Gibson <david@gibson.dropbear.id.au> Acked-by: Cornelia Huck <cohuck@redhat.com> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
* xlnx-zynqmp-ipi: Initial version of the Xilinx IPI deviceAlistair Francis2018-01-262-0/+378
| | | | | | | | This is the initial version of the Inter Processor Interrupt device. Signed-off-by: Alistair Francis <alistair.francis@xilinx.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
* xlnx-pmu-iomod-intc: Add the PMU Interrupt controllerAlistair Francis2018-01-262-0/+555
| | | | | | | | | Add the PMU IO Module Interrupt controller device. Signed-off-by: Alistair Francis <alistair.francis@xilinx.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
* Merge remote-tracking branch ↵Peter Maydell2018-01-251-4/+21
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 'remotes/pmaydell/tags/pull-target-arm-20180125' into staging target-arm queue: * target/arm: Fix address truncation in 64-bit pagetable walks * i.MX: Fix FEC/ENET receive functions * target/arm: preparatory refactoring for SVE emulation * hw/intc/arm_gic: Prevent the GIC from signaling an IRQ when it's "active and pending" * hw/intc/arm_gic: Fix C_RPR value on idle priority * hw/intc/arm_gic: Fix group priority computation for group 1 IRQs * hw/intc/arm_gic: Fix the NS view of C_BPR when C_CTRL.CBPR is 1 * hw/arm/virt: Check that the CPU realize method succeeded * sdhci: fix a NULL pointer dereference due to uninitialized AddressSpace object * xilinx_spips: Correct usage of an uninitialized local variable * pl110: Implement vertical compare/next base interrupts # gpg: Signature made Thu 25 Jan 2018 12:59:25 GMT # gpg: using RSA key 0x3C2525ED14360CDE # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" # gpg: aka "Peter Maydell <pmaydell@gmail.com>" # gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" # Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE * remotes/pmaydell/tags/pull-target-arm-20180125: (21 commits) pl110: Implement vertical compare/next base interrupts xilinx_spips: Correct usage of an uninitialized local variable sdhci: fix a NULL pointer dereference due to uninitialized AddresSpace object hw/arm/virt: Check that the CPU realize method succeeded hw/intc/arm_gic: Fix the NS view of C_BPR when C_CTRL.CBPR is 1 hw/intc/arm_gic: Fix group priority computation for group 1 IRQs hw/intc/arm_gic: Fix C_RPR value on idle priority hw/intc/arm_gic: Prevent the GIC from signaling an IRQ when it's "active and pending" target/arm: Simplify fp_exception_el for user-only target/arm: Hoist store to flags output in cpu_get_tb_cpu_state target/arm: Move cpu_get_tb_cpu_state out of line target/arm: Add ARM_FEATURE_SVE vmstate: Add VMSTATE_UINT64_SUB_ARRAY target/arm: Add aa{32, 64}_vfp_{dreg, qreg} helpers target/arm: Change the type of vfp.regs target/arm: Use pointers in neon tbl helper target/arm: Use pointers in neon zip/uzp helpers target/arm: Use pointers in crypto helpers target/arm: Mark disas_set_insn_syndrome inline i.MX: Fix FEC/ENET receive funtions ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * hw/intc/arm_gic: Fix the NS view of C_BPR when C_CTRL.CBPR is 1Luc MICHEL2018-01-251-3/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | When C_CTRL.CBPR is 1, the Non-Secure view of C_BPR is altered: - A Non-Secure read of C_BPR should return the BPR value plus 1, saturated to 7, - A Non-Secure write should be ignored. Signed-off-by: Luc MICHEL <luc.michel@git.antfield.fr> Message-id: 20180119145756.7629-6-luc.michel@greensocs.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> [PMM: fixed comment typo] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * hw/intc/arm_gic: Fix group priority computation for group 1 IRQsLuc MICHEL2018-01-251-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | When determining the group priority of a group 1 IRQ, if C_CTRL.CBPR is 0, the non-secure BPR value is used. However, this value must be incremented by one so that it matches the secure world number of implemented priority bits (NS world has one less priority bit compared to the Secure world). Signed-off-by: Luc MICHEL <luc.michel@git.antfield.fr> Message-id: 20180119145756.7629-5-luc.michel@greensocs.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> [PMM: add assert, as the gicv3 code has] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * hw/intc/arm_gic: Fix C_RPR value on idle priorityLuc MICHEL2018-01-251-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When there is no active interrupts in the GIC, a read to the C_RPR register should return the value of the "Idle priority", which is either the maximum value an IRQ priority field can be set to, or 0xff. Since the QEMU GIC model implements all the 8 priority bits, the Idle priority is 0xff. Internally, when there is no active interrupt, the running priority value is 0x100. The gic_get_running_priority function returns an uint8_t and thus, truncate this value to 0x00 when returning it. This is wrong since a value of 0x00 correspond to the maximum possible priority. This commit fixes the returned value when the internal value is 0x100. Note that it is correct for the Non-Secure view to return 0xff even though from the NS world point of view, only 7 priority bits are implemented. The specification states that the Idle priority can be 0xff even when not all the 8 priority bits are implemented. This has been verified against a real GICv2 hardware on a Xilinx ZynqMP based board. Regarding the ARM11MPCore version of the GIC, the specification is not clear on that point, so this commit does not alter its behavior. Signed-off-by: Luc MICHEL <luc.michel@git.antfield.fr> Message-id: 20180119145756.7629-4-luc.michel@greensocs.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * hw/intc/arm_gic: Prevent the GIC from signaling an IRQ when it's "active and ↵Luc MICHEL2018-01-251-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | pending" In the GIC, when an IRQ is acknowledged, its state goes from "pending" to: - "active" if the corresponding IRQ pin has been de-asserted - "active and pending" otherwise. The GICv2 manual states that when a IRQ becomes active (or active and pending), the GIC should either signal another (higher priority) IRQ to the CPU if there is one, or de-assert the CPU IRQ pin. The current implementation of the GIC in QEMU does not check if the IRQ is already active when looking for pending interrupts with sufficient priority in gic_update(). This can lead to signaling an interrupt that is already active. This usually happens when splitting priority drop and interrupt deactivation. On priority drop, the IRQ stays active until deactivation. If it becomes pending again, chances are that it will be incorrectly selected as best_irq in gic_update(). This commit fixes this by checking if the IRQ is not already active when looking for best_irq in gic_update(). Note that regarding the ARM11MPCore GIC version, the corresponding manual is not clear on that point, but it has has no priority drop/interrupt deactivation separation, so this case should not happen. Signed-off-by: Luc MICHEL <luc.michel@git.antfield.fr> Message-id: 20180119145756.7629-3-luc.michel@greensocs.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* | sparc/leon3 irqmp: fix IRQ software ackJean-Christophe Dubois2018-01-241-6/+11
|/ | | | | | | | | | | | | | | | | | | | | | | | | | | | With the LEON3 IRQ controller IRQs can be acknowledged 2 ways: * Explicitly by software writing to the CLEAR_OFFSET register * Implicitly when the procesor is done running the trap handler attached to the IRQ. The actual IRQMP code only allows the implicit processor triggered IRQ ack. If software write explicitly to the CLEAR_OFFSET register, this will clear the pending bit in the register value but this will not lower the ongoing raised IRQ with the processor. The IRQ will be kept raised to the LEON processor until the related trap handler is run and the processor implicitly ack the interrupt. So with the actual IRQMP code trap handler have to be run even if the software has already done its job by clearing the pending bit. This feature has been tested on another LEON3 simulator (tsim_leon3 from Gaisler) and it turns out that the Qemu implementation is not equivalent to the tsim one. In tsim, if software does clear a pending interrupt before the related interrupt handler is triggered the said interrupt handler will not be called. This patch brings the Qemu IRQMP implementation in line with the tsim implementation by allowing IRQ to be acknowledged by software only. Signed-off-by: Jean-Christophe Dubois <jcd@tribudubois.net> Reviewed-by: Fabien Chouteau <chouteau@adacore.com> Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
* Replace all occurances of __FUNCTION__ with __func__Alistair Francis2018-01-221-1/+1
| | | | | | | | | | | | | | | | Replace all occurs of __FUNCTION__ except for the check in checkpatch with the non GCC specific __func__. One line in hcd-musb.c was manually tweaked to pass checkpatch. Signed-off-by: Alistair Francis <alistair.francis@xilinx.com> Reviewed-by: Eric Blake <eblake@redhat.com> Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com> Reviewed-by: Anthony PERARD <anthony.perard@citrix.com> Reviewed-by: Juan Quintela <quintela@redhat.com> Reviewed-by: Gerd Hoffmann <kraxel@redhat.com> [THH: Removed hunks related to pxa2xx_mmci.c (fixed already)] Signed-off-by: Thomas Huth <thuth@redhat.com>
* hw/intc/armv7m: Support byte and halfword accesses to CFSRPeter Maydell2018-01-161-16/+22
| | | | | | | | | | | | The Configurable Fault Status Register for ARMv7M and v8M is supposed to be byte and halfword accessible, but we were only implementing word accesses. Add support for the other access sizes, which are used by the Zephyr RTOS. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reported-by: Andy Gross <andy.gross@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-id: 1512742372-31517-1-git-send-email-peter.maydell@linaro.org
* hw/intc/arm_gic: reserved register addresses are RAZ/WIPeter Maydell2018-01-111-2/+3
| | | | | | | | | | | | The GICv2 specification says that reserved register addresses must RAZ/WI; now that we implement external abort handling for Arm CPUs this means we must return MEMTX_OK rather than MEMTX_ERROR, to avoid generating a spurious guest data abort. Cc: qemu-stable@nongnu.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1513183941-24300-3-git-send-email-peter.maydell@linaro.org Reviewed-by: Alistair Francis <alistair.francis@xilinx.com>
* hw/intc/arm_gicv3: Make reserved register addresses RAZ/WIPeter Maydell2018-01-113-5/+29
| | | | | | | | | | | | The GICv3 specification says that reserved register addresses should RAZ/WI. This means we need to return MEMTX_OK, not MEMTX_ERROR, because now that we support generating external aborts the latter will cause an abort on new board models. Cc: qemu-stable@nongnu.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1513183941-24300-2-git-send-email-peter.maydell@linaro.org Reviewed-by: Alistair Francis <alistair.francis@xilinx.com>
* sun4m: remove include/hw/sparc/sun4m.h and all references to itMark Cave-Ayland2018-01-091-1/+0Star
| | | | | | | | With the previous commit there is now nothing left in sun4m.h so it can be removed, along with all remaining references to it. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Acked-by: Artyom Tarasenko <atar4qemu@gmail.com>
* apic: add function to apic that will be used by hvfSergio Andres Gomez Del Real2017-12-221-0/+12
| | | | | | | | | This patch adds the function apic_get_highest_priority_irr to apic.c and exports it through the interface in apic.h for use by hvf. Signed-off-by: Sergio Andres Gomez Del Real <Sergio.G.DelReal@gmail.com> Message-Id: <20170913090522.4022-8-Sergio.G.DelReal@gmail.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
* i8259: move TYPE_INTERRUPT_STATS_PROVIDER upperPeter Xu2017-12-212-7/+7
| | | | | | | | | | Now both classes (i8259, i8259-kvm) support this. Move this upper to the common class code. Signed-off-by: Peter Xu <peterx@redhat.com> Message-Id: <20171210063819.14892-6-peterx@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
* kvm-i8259: support "info pic" and "info irq"Peter Xu2017-12-211-0/+1
| | | | | | | | | | | | | | | | | | | | | | Let's leverage the i8259 common code for kvm-i8259 too. I think it's still possible that stats can lost when i8259 is in kernel and meanwhile when irqfd is used, e.g., by vfio or vhost devices. However that should be rare IMHO since they should be using MSIs mostly if they really want performance (that's why people use vhost and device assignment), and no old INTx should be used. As long as the INTx users are emulated in QEMU the stats will be correct. For "info pic", it should be always accurate since we fetch kvm regs before dump. More importantly, it's just too simple to do this now - it's only 10+ LOC to gain this feature. Signed-off-by: Peter Xu <peterx@redhat.com> Message-Id: <20171210063819.14892-5-peterx@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
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