summaryrefslogtreecommitdiffstats
path: root/hw/intc
Commit message (Collapse)AuthorAgeFilesLines
* hw/intc: Vectored Interrupt Controller (VIC)Amir Gonnen2022-04-263-0/+317
| | | | | | | | | | | | | | | Implement nios2 Vectored Interrupt Controller (VIC). VIC is connected to EIC. It needs to update rha, ril, rrs and rnmi fields on Nios2CPU before raising an IRQ. For that purpose, VIC has a "cpu" property which should refer to the nios2 cpu and set by the board that connects VIC. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Amir Gonnen <amir.gonnen@neuroblade.ai> Message-Id: <20220303153906.2024748-5-amir.gonnen@neuroblade.ai> [rth: Split out nios2_vic.h] Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220421151735.31996-60-richard.henderson@linaro.org>
* Merge tag 'pull-target-arm-20220422-1' of ↵Richard Henderson2022-04-229-242/+1508
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | https://git.linaro.org/people/pmaydell/qemu-arm into staging target-arm queue: * Implement GICv4 emulation * Some cleanup patches in target/arm * hw/arm/smmuv3: Pass the actual perm to returned IOMMUTLBEntry in smmuv3_translate() # -----BEGIN PGP SIGNATURE----- # # iQJNBAABCAA3FiEE4aXFk81BneKOgxXPPCUl7RQ2DN4FAmJisasZHHBldGVyLm1h # eWRlbGxAbGluYXJvLm9yZwAKCRA8JSXtFDYM3vcdEACIcvC8E93tFfeKwDQHSdPx # 7dPCdq+EZc/xEA2U/q282PFtvNBP6zo65RzWKXTkyfE5exLkCmqJqXSIUVfiuTyT # IAx9mL++StpBJMiqAebzEp2n8gwG7JymFeGuHYGet/nRrcwQYacBNxSl+BIVqZAm # mUy2UOlqJDlzMAVOcs/Ikfhj0z3qa52aZ8eF6sQI3mbSggiSIWOhyzNYo7jMB1x7 # UuHlYpvYDltKT7PveA5JSuBP9OmV5RrqqO4s5c22Y+o4k+La/NURDPdegblMfRA9 # MfWAEHqjA1WQaxh/Tb4Bex1u875mFMOXMZk3P910wSeqxMLhTCmjTA2g4p1KhfcA # LQJ5G2IvSA7HN660NLhZAqL601/1tS7Qcl387TfcU7WCDbgmzv2RCvH6UACF2hVl # CH4bC3lKvemT324aOBs/TCnvdu54qR6hkJZ57XSn59QHvrRvrREVdYNfQnl/g751 # GTp8aMcmvTkZ8I7k2t4Tx+CoFO38+rv7PupLN+Eq4k97ovXmAWxekizv8KYu5itY # emg63kItorwCgRwkKP28RKWLS/7dEpoF8sg5jBiBtGBGNG0AWPq4GZdrhaL58cr4 # lr4nSseN2IRsrp3SgM2203RjdghFM8ey1Dq+x2mRp+Q21vVTltI/VSiUSz0c2Vpo # JgbC4Jo+jufMkav31zOCAg== # =jqHX # -----END PGP SIGNATURE----- # gpg: Signature made Fri 22 Apr 2022 06:46:19 AM PDT # gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE # gpg: issuer "peter.maydell@linaro.org" # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [full] # gpg: aka "Peter Maydell <pmaydell@gmail.com>" [full] # gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [full] * tag 'pull-target-arm-20220422-1' of https://git.linaro.org/people/pmaydell/qemu-arm: (61 commits) hw/arm/smmuv3: Pass the actual perm to returned IOMMUTLBEntry in smmuv3_translate() target/arm: Use tcg_constant_i32 in translate.h target/arm: Use tcg_constant in translate-vfp.c target/arm: Use smin/smax for do_sat_addsub_32 target/arm: Use tcg_constant in translate-neon.c target/arm: Use tcg_constant in translate-m-nocp.c target/arm: Simplify aa32 DISAS_WFI target/arm: Simplify gen_sar target/arm: Simplify GEN_SHIFT in translate.c target/arm: Split out gen_rebuild_hflags target/arm: Split out set_btype_raw target/arm: Remove fpexc32_access target/arm: Change CPUArchState.thumb to bool target/arm: Change DisasContext.thumb to bool target/arm: Extend store_cpu_offset to take field size target/arm: Change CPUArchState.aarch64 to bool target/arm: Change DisasContext.aarch64 to bool target/arm: Update SCTLR bits to ARMv9.2 target/arm: Update SCR_EL3 bits to ARMv8.8 target/arm: Update ISAR fields for ARMv8.8 ... Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * hw/intc/arm_gicv3: Allow 'revision' property to be set to 4Peter Maydell2022-04-222-5/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Now that we have implemented all the GICv4 requirements, relax the error-checking on the GIC object's 'revision' property to allow a TCG GIC to be a GICv4, whilst still constraining the KVM GIC to GICv3. Our 'revision' property doesn't consider the possibility of wanting to specify the minor version of the GIC -- for instance there is a GICv3.1 which adds support for extended SPI and PPI ranges, among other things, and also GICv4.1. But since the QOM property is internal to QEMU, not user-facing, we can cross that bridge when we come to it. Within the GIC implementation itself code generally checks against the appropriate ID register feature bits, and the only use of s->revision is for setting those ID register bits. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220408141550.1271295-39-peter.maydell@linaro.org
| * hw/intc/arm_gicv3: Update ID and feature registers for GICv4Peter Maydell2022-04-226-12/+32
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Update the various GIC ID and feature registers for GICv4: * PIDR2 [7:4] is the GIC architecture revision * GICD_TYPER.DVIS is 1 to indicate direct vLPI injection support * GICR_TYPER.VLPIS is 1 to indicate redistributor support for vLPIs * GITS_TYPER.VIRTUAL is 1 to indicate vLPI support * GITS_TYPER.VMOVP is 1 to indicate that our VMOVP implementation handles cross-ITS synchronization for the guest * ICH_VTR_EL2.nV4 is 0 to indicate direct vLPI injection support Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220408141550.1271295-38-peter.maydell@linaro.org
| * hw/intc/arm_gicv3_redist: Implement gicv3_redist_inv_vlpi()Peter Maydell2022-04-221-2/+5
| | | | | | | | | | | | | | | | | | | | Implement the function gicv3_redist_inv_vlpi(), which was previously left as a stub. This is the function that does the work of the INV command for a virtual interrupt. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220408141550.1271295-37-peter.maydell@linaro.org
| * hw/intc/arm_gicv3_redist: Implement gicv3_redist_vinvall()Peter Maydell2022-04-221-1/+7
| | | | | | | | | | | | | | | | | | | | Implement the gicv3_redist_vinvall() function (previously left as a stub). This function handles the work of a VINVALL command: it must invalidate any cached information associated with a specific vCPU. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220408141550.1271295-36-peter.maydell@linaro.org
| * hw/intc/arm_gicv3_redist: Implement gicv3_redist_mov_vlpi()Peter Maydell2022-04-221-2/+18
| | | | | | | | | | | | | | | | | | | | Implement the gicv3_redist_mov_vlpi() function (previously left as a stub). This function handles the work of a VMOVI command: it marks the vLPI not-pending on the source and pending on the destination. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220408141550.1271295-35-peter.maydell@linaro.org
| * hw/intc/arm_gicv3_redist: Use set_pending_table_bit() in mov handlingPeter Maydell2022-04-221-8/+1Star
| | | | | | | | | | | | | | | | | | | | | | We can use our new set_pending_table_bit() utility function in gicv3_redist_mov_lpi() to clear the bit in the source pending table, rather than doing the "load, clear bit, store" ourselves. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220408141550.1271295-34-peter.maydell@linaro.org
| * hw/intc/arm_gicv3_redist: Implement gicv3_redist_vlpi_pending()Peter Maydell2022-04-221-2/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | Implement the function gicv3_redist_vlpi_pending(), which was previously left as a stub. This is the function that is called by the CPU interface when it changes the state of a vLPI. It's similar to gicv3_redist_process_vlpi(), but we know that the vCPU is definitely resident on the redistributor and the irq is in range, so it is a bit simpler. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220408141550.1271295-33-peter.maydell@linaro.org
| * hw/intc/arm_gicv3_redist: Implement gicv3_redist_process_vlpi()Peter Maydell2022-04-221-4/+44
| | | | | | | | | | | | | | | | | | | | | | | | | | Implement the function gicv3_redist_process_vlpi(), which was left as just a stub earlier. This function deals with being handed a VLPI by the ITS. It must set the bit in the pending table. If the vCPU is currently resident we must recalculate the highest priority pending vLPI; otherwise we may need to ring a "doorbell" interrupt to let the hypervisor know it might want to reschedule the vCPU. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220408141550.1271295-32-peter.maydell@linaro.org
| * hw/intc/arm_gicv3_redist: Factor out "update bit in pending table" codePeter Maydell2022-04-221-19/+30
| | | | | | | | | | | | | | | | | | | | Factor out the code which sets a single bit in an LPI pending table. We're going to need this for handling vLPI tables, not just the physical LPI table. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220408141550.1271295-31-peter.maydell@linaro.org
| * hw/intc/arm_gicv3_redist: Recalculate hppvlpi on VPENDBASER writesPeter Maydell2022-04-221-3/+84
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The guest uses GICR_VPENDBASER to tell the redistributor when it is scheduling or descheduling a vCPU. When it writes and changes the VALID bit from 0 to 1, it is scheduling a vCPU, and we must update our view of the current highest priority pending vLPI from the new Pending and Configuration tables. When it writes and changes the VALID bit from 1 to 0, it is descheduling, which means that there is no longer a highest priority pending vLPI. The specification allows the implementation to use part of the vLPI Pending table as an IMPDEF area where it can cache information when a vCPU is descheduled, so that it can avoid having to do a full rescan of the tables when the vCPU is scheduled again. For now, we don't take advantage of this, and simply do a complete rescan. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220408141550.1271295-30-peter.maydell@linaro.org
| * hw/intc/arm_gicv3_redist: Factor out "update hpplpi for all LPIs" logicPeter Maydell2022-04-221-20/+46
| | | | | | | | | | | | | | | | | | | | | | Factor out the common part of gicv3_redist_update_lpi_only() into a new function update_for_all_lpis(), which does a full rescan of an LPI Pending table and sets the specified PendingIrq struct with the highest priority pending enabled LPI it finds. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220408141550.1271295-29-peter.maydell@linaro.org
| * hw/intc/arm_gicv3_redist: Factor out "update hpplpi for one LPI" logicPeter Maydell2022-04-221-27/+47
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently the functions which update the highest priority pending LPI information by looking at the LPI Pending and Configuration tables are hard-coded to use the physical LPI tables addressed by GICR_PENDBASER and GICR_PROPBASER. To support virtual LPIs we will need to do essentially the same job, but looking at the current virtual LPI Pending and Configuration tables and updating cs->hppvlpi instead of cs->hpplpi. Factor out the common part of the gicv3_redist_check_lpi_priority() function into a new update_for_one_lpi() function, which updates a PendingIrq struct if the specified LPI is higher priority than what is currently recorded there. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220408141550.1271295-28-peter.maydell@linaro.org
| * hw/intc/arm_gicv3_cpuif: Don't recalculate maintenance irq unnecessarilyPeter Maydell2022-04-221-5/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The maintenance interrupt state depends only on: * ICH_HCR_EL2 * ICH_LR<n>_EL2 * ICH_VMCR_EL2 fields VENG0 and VENG1 Now we have a separate function that updates only the vIRQ and vFIQ lines, use that in places that only change state that affects vIRQ and vFIQ but not the maintenance interrupt. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220408141550.1271295-27-peter.maydell@linaro.org
| * hw/intc/arm_gicv3_cpuif: Support vLPIsPeter Maydell2022-04-225-6/+137
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The CPU interface changes to support vLPIs are fairly minor: in the parts of the code that currently look at the list registers to determine the highest priority pending virtual interrupt, we must also look at the highest priority pending vLPI. To do this we change hppvi_index() to check the vLPI and return a special-case value if that is the right virtual interrupt to take. The callsites (which handle HPPIR and IAR registers and the "raise vIRQ and vFIQ lines" code) then have to handle this special-case value. This commit includes two interfaces with the as-yet-unwritten redistributor code: * the new GICv3CPUState::hppvlpi will be set by the redistributor (in the same way as the existing hpplpi does for physical LPIs) * when the CPU interface acknowledges a vLPI it needs to set it to non-pending; the new gicv3_redist_vlpi_pending() function (which matches the existing gicv3_redist_lpi_pending() used for physical LPIs) is a stub that will be filled in later Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220408141550.1271295-26-peter.maydell@linaro.org
| * hw/intc/arm_gicv3_cpuif: Split "update vIRQ/vFIQ" from gicv3_cpuif_virt_update()Peter Maydell2022-04-223-25/+53
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The function gicv3_cpuif_virt_update() currently sets all of vIRQ, vFIQ and the maintenance interrupt. This implies that it has to be used quite carefully -- as the comment notes, setting the maintenance interrupt will typically cause the GIC code to be re-entered recursively. For handling vLPIs, we need the redistributor to be able to tell the cpuif to update the vIRQ and vFIQ lines when the highest priority pending vLPI changes. Since that change can't cause the maintenance interrupt state to change, we can pull the "update vIRQ/vFIQ" parts of gicv3_cpuif_virt_update() out into a separate function, which the redistributor can then call without having to worry about the reentrancy issue. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220408141550.1271295-25-peter.maydell@linaro.org
| * hw/intc/arm_gicv3: Implement new GICv4 redistributor registersPeter Maydell2022-04-223-0/+99
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Implement the new GICv4 redistributor registers: GICR_VPROPBASER and GICR_VPENDBASER; for the moment we implement these as simple reads-as-written stubs, together with the necessary migration and reset handling. We don't put ID-register checks on the handling of these registers, because they are all in the only-in-v4 extra register frames, so they're not accessible in a GICv3. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220408141550.1271295-24-peter.maydell@linaro.org
| * hw/intc/arm_gicv3: Implement GICv4's new redistributor framePeter Maydell2022-04-223-5/+26
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The GICv4 extends the redistributor register map -- where GICv3 had two 64KB frames per CPU, GICv4 has four frames. Add support for the extra frame by using a new gicv3_redist_size() function in the places in the GIC implementation which currently use a fixed constant size for the redistributor register block. (Until we implement the extra registers they will RAZ/WI.) Any board that wants to use a GICv4 will need to also adjust to handle the different sized redistributor register block; that will be done separately. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220408141550.1271295-23-peter.maydell@linaro.org
| * hw/intc/arm_gicv3_its: Implement VINVALLPeter Maydell2022-04-224-0/+45
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The VINVALL command should cause any cached information in the ITS or redistributor for the specified vCPU to be dropped or otherwise made consistent with the in-memory LPI configuration tables. Here we implement the command and table parsing, leaving the redistributor part as a stub for the moment, as usual. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220408141550.1271295-22-peter.maydell@linaro.org
| * hw/intc/arm_gicv3_its: Implement VMOVIPeter Maydell2022-04-224-0/+116
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Implement the GICv4 VMOVI command, which moves the pending state of a virtual interrupt from one redistributor to another. As with MOVI, we handle the "parse and validate command arguments and table lookups" part in the ITS source file, and pass the final results to a function in the redistributor which will do the actual operation. As with the "make a VLPI pending" change, for the moment we leave that redistributor function as a stub, to be implemented in a later commit. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220408141550.1271295-21-peter.maydell@linaro.org
| * hw/intc/arm_gicv3_its: Implement INV for virtual interruptsPeter Maydell2022-04-223-2/+31
| | | | | | | | | | | | | | | | | | | | Implement the ITS side of the handling of the INV command for virtual interrupts; as usual this calls into a redistributor function which we leave as a stub to fill in later. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220408141550.1271295-20-peter.maydell@linaro.org
| * hw/intc/arm_gicv3_its: Implement INV command properlyPeter Maydell2022-04-224-2/+74
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We were previously implementing INV (like INVALL) to just blow away cached highest-priority-pending-LPI information on all connected redistributors. For GICv4.0, this isn't going to be sufficient, because the LPI we are invalidating cached information for might be either physical or virtual, and the required action is different for those two cases. So we need to do the full process of looking up the ITE from the devid and eventid. This also means we can do the error checks that the spec lists for this command. Split out INV handling into a process_inv() function like our other command-processing functions. For the moment, stick to handling only physical LPIs; we will add the vLPI parts later. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220408141550.1271295-19-peter.maydell@linaro.org
| * hw/intc/arm_gicv3_its: Implement VSYNCPeter Maydell2022-04-223-0/+13
| | | | | | | | | | | | | | | | | | | | | | The VSYNC command forces the ITS to synchronize all outstanding ITS operations for the specified vPEID, so that subsequent writes to GITS_TRANSLATER honour them. The QEMU implementation is always in sync, so for us this is a nop, like the existing SYNC command. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220408141550.1271295-18-peter.maydell@linaro.org
| * hw/intc/arm_gicv3_its: Implement VMOVPPeter Maydell2022-04-223-0/+85
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Implement the GICv4 VMOVP command, which updates an entry in the vPE table to change its rdbase field. This command is unique in the ITS command set because its effects must be propagated to all the other ITSes connected to the same GIC as the ITS which executes the VMOVP command. The GICv4 spec allows two implementation choices for handling the propagation to other ITSes: * If GITS_TYPER.VMOVP is 1, the guest only needs to issue the command on one ITS, and the implementation handles the propagation to all ITSes * If GITS_TYPER.VMOVP is 0, the guest must issue the command on every ITS, and arrange for the ITSes to synchronize the updates with each other by setting ITSList and Sequence Number fields in the command packets We choose the GITS_TYPER.VMOVP = 1 approach, and synchronously execute the update on every ITS. For GICv4.1 this command has extra fields in the command packet and additional behaviour. We define the 4.1-only fields with the FIELD macro, but only implement the GICv4.0 version of the command. Note that we don't update the reported GITS_TYPER value here; we'll do that later in a commit which updates all the reported feature bit and ID register values for GICv4. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220408141550.1271295-17-peter.maydell@linaro.org [PMM: Moved gicv3_foreach_its() to arm_gicv3_its_common.h, for consistency with gicv3_add_its()]
| * hw/intc/arm_gicv3: Keep pointers to every connected ITSPeter Maydell2022-04-223-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The GICv4 ITS VMOVP command's semantics require it to perform the operation on every ITS connected to the same GIC that the ITS that received the command is attached to. This means that the GIC object needs to keep a pointer to every ITS that is connected to it (previously it was sufficient for the ITS to have a pointer to its GIC). Add a glib ptrarray to the GICv3 object which holds pointers to every connected ITS, and make the ITS add itself to the array for the GIC it is connected to when it is realized. Note that currently all QEMU machine types with an ITS have exactly one ITS in the system, so typically the length of this ptrarray will be 1. Multiple ITSes are typically used to improve performance on real hardware, so we wouldn't need to have more than one unless we were modelling a real machine type that had multile ITSes. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> [PMM: Moved gicv3_add_its() to arm_gicv3_its_common.h to avoid compilation error building the KVM ITS] Message-id: 20220408141550.1271295-16-peter.maydell@linaro.org
| * hw/intc/arm_gicv3_its: Handle virtual interrupts in process_its_cmd()Peter Maydell2022-04-224-2/+125
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For GICv4, interrupt table entries read by process_its_cmd() may indicate virtual LPIs which are to be directly injected into a VM. Implement the ITS side of the code for handling this. This is similar to the existing handling of physical LPIs, but instead of looking up a collection ID in a collection table, we look up a vPEID in a vPE table. As with the physical LPIs, we leave the rest of the work to code in the redistributor device. The redistributor half will be implemented in a later commit; for now we just provide a stub function which does nothing. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220408141550.1271295-15-peter.maydell@linaro.org
| * hw/intc/arm_gicv3_its: Split out process_its_cmd() physical interrupt codePeter Maydell2022-04-221-17/+32
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Split the part of process_its_cmd() which is specific to physical interrupts into its own function. This is the part which starts by taking the ICID and looking it up in the collection table. The handling of virtual interrupts is significantly different (involving a lookup in the vPE table) so structuring the code with one sub-function for the physical interrupt case and one for the virtual interrupt case will be clearer than putting both cases in one large function. The code for handling the "remove mapping from ITE" for the DISCARD command remains in process_its_cmd() because it is common to both virtual and physical interrupts. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220408141550.1271295-14-peter.maydell@linaro.org
| * hw/intc/arm_gicv3_its: Factor out CTE lookup sequencePeter Maydell2022-04-221-70/+39Star
| | | | | | | | | | | | | | | | | | Factor out the sequence of looking up a CTE from an ICID including the validity and error checks. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220408141550.1271295-13-peter.maydell@linaro.org
| * hw/intc/arm_gicv3_its: Factor out "find ITE given devid, eventid"Peter Maydell2022-04-221-50/+54
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The operation of finding an interrupt table entry given a (DeviceID, EventID) pair is necessary in multiple different ITS commands. The process requires first using the DeviceID as an index into the device table to find the DTE, and then useng the EventID as an index into the interrupt table specified by that DTE to find the ITE. We also need to handle all the possible error cases: indexes out of range, table memory not readable, table entries not valid. Factor this out into a separate lookup_ite() function which we can then call from the places where we were previously open-coding this sequence. We'll also need this for some of the new GICv4.0 commands. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220408141550.1271295-12-peter.maydell@linaro.org
| * hw/intc/arm_gicv3_its: Distinguish success and error cases of CMD_CONTINUEPeter Maydell2022-04-221-13/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | In the ItsCmdResult enum, we currently distinguish only CMD_STALL (failure, stall processing of the command queue) and CMD_CONTINUE (keep processing the queue), and we use the latter both for "there was a parameter error, go on to the next command" and "the command succeeded, go on to the next command". Sometimes we would like to distinguish those two cases, so add CMD_CONTINUE_OK to the enum to represent the success situation, and use it in the relevant places. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220408141550.1271295-11-peter.maydell@linaro.org
| * hw/intc/arm_gicv3_its: Implement VMAPPPeter Maydell2022-04-223-0/+102
| | | | | | | | | | | | | | | | | | | | | | | | | | Implement the GICv4 VMAPP command, which writes an entry to the vPE table. For GICv4.1 this command has extra fields in the command packet and additional behaviour. We define the 4.1-only fields with the FIELD macro, but only implement the GICv4.0 version of the command. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220408141550.1271295-10-peter.maydell@linaro.org
| * hw/intc/arm_gicv3_its: Implement VMAPI and VMAPTIPeter Maydell2022-04-223-0/+102
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Implement the GICv4 VMAPI and VMAPTI commands. These write an interrupt translation table entry that maps (DeviceID,EventID) to (vPEID,vINTID,doorbell). The only difference between VMAPI and VMAPTI is that VMAPI assumes vINTID == EventID rather than both being specified in the command packet. (This code won't be reachable until we allow the GIC version to be set to 4. Support for reading this new virtual-interrupt DTE and handling it correctly will be implemented in a later commit.) Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220408141550.1271295-9-peter.maydell@linaro.org
| * hw/intc/arm_gicv3_its: Implement GITS_BASER2 for GICv4Peter Maydell2022-04-222-0/+41
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The GICv4 defines a new in-guest-memory table for the ITS: this is the vPE table. Implement the new GITS_BASER2 register which the guest uses to tell the ITS where the vPE table is located, including the decode of the register fields into the TableDesc structure which we do for the GITS_BASER<n> when the guest enables the ITS. We guard provision of the new register with the its_feature_virtual() function, which does a check of the GITS_TYPER.Virtual bit which indicates presence of ITS support for virtual LPIs. Since this bit is currently always zero, GICv4-specific features will not be accessible to the guest yet. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220408141550.1271295-8-peter.maydell@linaro.org
| * hw/intc/arm_gicv3_its: Factor out "is intid a valid LPI ID?"Peter Maydell2022-04-221-3/+7
| | | | | | | | | | | | | | | | | | | | In process_mapti() we check interrupt IDs to see whether they are in the valid LPI range. Factor this out into its own utility function, as we're going to want it elsewhere too for GICv4. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220408141550.1271295-7-peter.maydell@linaro.org
| * hw/intc/arm_gicv3: Report correct PIDR0 values for ID registersPeter Maydell2022-04-224-5/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We use the common function gicv3_idreg() to supply the CoreSight ID register values for the GICv3 for the copies of these ID registers in the distributor, redistributor and ITS register frames. This isn't quite correct, because while most of the register values are the same, the PIDR0 value should vary to indicate which of these three frames it is. (You can see this and also the correct values of these PIDR0 registers by looking at the GIC-600 or GIC-700 TRMs, for example.) Make gicv3_idreg() take an extra argument for the PIDR0 value. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220408141550.1271295-5-peter.maydell@linaro.org
| * hw/intc/arm_gicv3: Insist that redist region capacity matches CPU countPeter Maydell2022-04-221-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Boards using the GICv3 need to configure it with both the total number of CPUs and also the sizes of all the memory regions which contain redistributors (one redistributor per CPU). At the moment the GICv3 checks that the number of CPUs specified is not too many to fit in the defined redistributor regions, but in fact the code assumes that the two match exactly. For instance when we set the GICR_TYPER.Last bit on the final redistributor in each region, we assume that we don't need to consider the possibility of a region being only half full of redistributors or even completely empty. We also assume in gicv3_redist_read() and gicv3_redist_write() that we can calculate the CPU index from the offset within the MemoryRegion and that this will always be in range. Fortunately all the board code sets the redistributor region sizes to exactly match the CPU count, so this isn't a visible bug. We could in theory make the GIC code handle non-full redistributor regions, or have it automatically reduce the provided region sizes to match the CPU count, but the simplest thing is just to strengthen the error check and insist that the CPU count and redistributor region size settings match exactly, since all the board code does that anyway. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220408141550.1271295-4-peter.maydell@linaro.org
| * hw/intc/arm_gicv3: Sanity-check num-cpu propertyPeter Maydell2022-04-221-0/+4
| | | | | | | | | | | | | | | | | | | | In the GICv3 code we implicitly rely on there being at least one CPU and thus at least one redistributor and CPU interface. Sanity-check that the property the board code sets is not zero. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220408141550.1271295-3-peter.maydell@linaro.org
| * hw/intc/arm_gicv3_its: Add missing blank linePeter Maydell2022-04-221-0/+1
| | | | | | | | | | | | | | | | | | | | In commit b6f96009acc we split do_process_its_cmd() from process_its_cmd(), but forgot the usual blank line between function definitions. Add it. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220408141550.1271295-2-peter.maydell@linaro.org
* | hw/intc: riscv_aclint: Add reset function of ACLINT devicesJim Shu2022-04-221-0/+39
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This commit implements reset function of all ACLINT devices. ACLINT device reset will clear MTIME and MSIP register to 0. Depend on RISC-V ACLINT spec v1.0-rc4: https://github.com/riscv/riscv-aclint/blob/v1.0-rc4/riscv-aclint.adoc Signed-off-by: Jim Shu <jim.shu@sifive.com> Reviewed-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20220420080901.14655-5-frank.chang@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
* | hw/intc: Make RISC-V ACLINT mtime MMIO register writableFrank Chang2022-04-221-21/+50
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | RISC-V privilege spec defines that mtime is exposed as a memory-mapped machine-mode read-write register. However, as QEMU uses host monotonic timer as timer source, this makes mtime to be read-only in RISC-V ACLINT. This patch makes mtime to be writable by recording the time delta value between the mtime value to be written and the timer value at the time mtime is written. Time delta value is then added back whenever the timer value is retrieved. Signed-off-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Jim Shu <jim.shu@sifive.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20220420080901.14655-4-frank.chang@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
* | hw/intc: Support 32/64-bit mtimecmp and mtime accesses in RISC-V ACLINTFrank Chang2022-04-221-15/+27
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | RISC-V privilege spec defines that: * In RV32, memory-mapped writes to mtimecmp modify only one 32-bit part of the register. * For RV64, naturally aligned 64-bit memory accesses to the mtime and mtimecmp registers are additionally supported and are atomic. It's possible to perform both 32/64-bit read/write accesses to both mtimecmp and mtime registers. Signed-off-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Jim Shu <jim.shu@sifive.com> Message-Id: <20220420080901.14655-3-frank.chang@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
* | hw/intc: Add .impl.[min|max]_access_size declaration in RISC-V ACLINTFrank Chang2022-04-221-0/+4
|/ | | | | | | | | | | | | | If device's MemoryRegion doesn't have .impl.[min|max]_access_size declaration, the default access_size_min would be 1 byte and access_size_max would be 4 bytes (see: softmmu/memory.c). This will cause a 64-bit memory access to ACLINT to be splitted into two 32-bit memory accesses. Signed-off-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Jim Shu <jim.shu@sifive.com> Message-Id: <20220420080901.14655-2-frank.chang@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
* Merge tag 'misc-pull-request' of gitlab.com:marcandre.lureau/qemu into stagingRichard Henderson2022-04-211-6/+3Star
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Misc cleanups # -----BEGIN PGP SIGNATURE----- # # iQJQBAABCAA6FiEEh6m9kz+HxgbSdvYt2ujhCXWWnOUFAmJhYIscHG1hcmNhbmRy # ZS5sdXJlYXVAcmVkaGF0LmNvbQAKCRDa6OEJdZac5W0jD/43n8PL2cv42lq6OaIS # OYN9vfW9xgA9THZiUH4xEHYreZh+KofmY1PbJn1n7q+v6DecBiqM4fZr1LY8X3PM # xRUH0l4gjXwYwX2cSSo5UTZ/PF248Uoo3tUE3vgMFkYghHMjKcTtaSkYEPGHf2nR # t3m1qLG9w9YPhVg7PNCntjUKi+w2TtcrRVzP7V7XyFc1HrAoT0ys6KaBBrXMbcjz # SxTRbcwSq+6aPjQIn0RWp8Hp1HkdNjegB98dkyqRLlVaugHZWPYDXDQTgVziQlX8 # dU8YrlvTOtDWwsNP6awWnW6/IjKuJjGR0wT3QKwi8JAZ0YV3egwEKoQRUAyHtnn2 # FkSMYgmJcF0ai1aIJFAx+3PIzCfS49lKXA0t303DtY3hRR9JKGMwaV2do9Wm2irt # o7T1lKKN7R7R8Q3U4OsatYMYm7KYL07NEDiQCPloGvCo27ezkAWCKXAw1mRUkxKF # jKwJPcnOUq21Jp6tpjsR8ifSw70jBSEWQSGqhXnDhZhx2C2/Qqkg2I8DagLiPger # kYxbQ13LTG0R25YHa1r3UmzuD+HpZOM8XoLJc5yun/1UrwyR9ghHrOoxkSnRT2Ks # QFn//xQ2SzUnGBNzNSMfTk8vzludxSWfFnOjkviF6E2Elnw3p8f/kOQRAft5dMBY # ftgoy2yLone3HpKfjuOriicIzg== # =0GLo # -----END PGP SIGNATURE----- # gpg: Signature made Thu 21 Apr 2022 06:47:55 AM PDT # gpg: using RSA key 87A9BD933F87C606D276F62DDAE8E10975969CE5 # gpg: issuer "marcandre.lureau@redhat.com" # gpg: Good signature from "Marc-André Lureau <marcandre.lureau@redhat.com>" [full] # gpg: aka "Marc-André Lureau <marcandre.lureau@gmail.com>" [full] * tag 'misc-pull-request' of gitlab.com:marcandre.lureau/qemu: (30 commits) qga: use fixed-length and GDateTime for log timestamp tests/fuzz: fix warning qga: remove need for QEMU atomic.h util: replace qemu_get_local_state_pathname() util: use qemu_create() in qemu_write_pidfile() util: use qemu_write_full() in qemu_write_pidfile() util: simplify write in signal handler qtest: simplify socket_send() qga: move qga_get_host_name() Move error_printf_unless_qmp() with monitor unit tests: run-time skip test-qga if TSAN is enabled compiler.h: add QEMU_SANITIZE_{ADDRESS,THREAD} tests: remove block/qdict checks from check-qobject.c include: move qdict_{crumple,flatten} declarations include: add qemu/keyval.h include: move qemu_fdatasync() to osdep include: move qemu_msync() to osdep compiler.h: replace QEMU_NORETURN with G_NORETURN osdep.h: move qemu_build_not_reached() doc/style: CLang -> Clang ... Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * intc/exynos4210_gic: replace snprintf() with g_strdup_printf()Marc-André Lureau2022-04-211-6/+3Star
| | | | | | | | | | | | | | | | | | | | | | While at it, replace '%x' with '%u' as suggested by Philippe Mathieu-Daudé. Also fixes a GCC 12.0.1 -Wformat-overflow false-positive. Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Daniel P. Berrangé <berrange@redhat.com> Message-Id: <20220420132624.2439741-16-marcandre.lureau@redhat.com>
* | hw/arm/exynos4210: Put combiners into state structPeter Maydell2022-04-211-30/+1Star
| | | | | | | | | | | | | | | | | | | | Switch the creation of the combiner devices to the new-style "embedded in state struct" approach, so we can easily refer to the object elsewhere during realize. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220404154658.565020-18-peter.maydell@linaro.org
* | hw/arm/exynos4210: Move exynos4210_combiner_get_gpioin() into exynos4210.cPeter Maydell2022-04-211-77/+0Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The function exynos4210_combiner_get_gpioin() currently lives in exynos4210_combiner.c, but it isn't really part of the combiner device itself -- it is a function that implements the wiring up of some interrupt sources to multiple combiner inputs. Move it to live with the other SoC-level code in exynos4210.c, along with a few macros previously defined in exynos4210.h which are now used only in exynos4210.c. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220404154658.565020-11-peter.maydell@linaro.org
* | hw/arm/exynos4210: Put external GIC into state structPeter Maydell2022-04-211-15/+2Star
| | | | | | | | | | | | | | | | | | | | Switch the creation of the external GIC to the new-style "embedded in state struct" approach, so we can easily refer to the object elsewhere during realize. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220404154658.565020-9-peter.maydell@linaro.org
* | hw/arm/exynos4210: Move exynos4210_init_board_irqs() into exynos4210.cPeter Maydell2022-04-211-204/+0Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The function exynos4210_init_board_irqs() currently lives in exynos4210_gic.c, but it isn't really part of the exynos4210.gic device -- it is a function that implements (some of) the wiring up of interrupts between the SoC's GIC and combiner components. This means it fits better in exynos4210.c, which is the SoC-level code. Move it there. Similarly, exynos4210_git_irq() is used almost only in the SoC-level code, so move it too. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220404154658.565020-8-peter.maydell@linaro.org
* | hw/arm/exynos4210: Fix code style nit in combiner_grp_to_gic_id[]Peter Maydell2022-04-211-1/+1
| | | | | | | | | | | | | | | | | | | | | | Fix a missing set of spaces around '-' in the definition of combiner_grp_to_gic_id[]. We're about to move this code, so fix the style issue first to keep checkpatch happy with the code-motion patch. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220404154658.565020-7-peter.maydell@linaro.org
generated by cgit v1.2.3-55-g7522 (git 2.39.0) at 2025-01-27 05:40:13 +0100