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* | esp: rename existing ESP QOM type to SYSBUS_ESPMark Cave-Ayland2021-03-071-2/+2
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* vt82c686: Move creation of ISA devices to the ISA bridgeBALATON Zoltan2021-02-211-24/+5Star
* vt82c686: Fix SMBus IO base and configuration registersBALATON Zoltan2021-02-211-3/+1Star
* hw/mips/boston: Use bootloader helper to set GCRsJiaxun Yang2021-02-211-34/+11Star
* hw/mips/boston: Use bl_gen_kernel_jump to generate bootloadersJiaxun Yang2021-02-211-15/+2Star
* hw/mips/fuloong2e: Use bl_gen_kernel_jump to generate bootloadersJiaxun Yang2021-02-211-24/+3Star
* hw/mips: Add a bootloader helperJiaxun Yang2021-02-212-1/+201
* hw/mips: loongson3: Drop 'struct MemmapEntry'Bin Meng2021-02-212-9/+4Star
* cpu: tcg_ops: move to tcg-cpu-ops.h, keep a pointer in CPUClassClaudio Fontana2021-02-051-2/+5
* cpu: move cc->transaction_failed to tcg_opsClaudio Fontana2021-02-051-2/+7
* docs/system: Remove deprecated 'fulong2e' machine aliasPhilippe Mathieu-Daudé2021-01-141-1/+0Star
* hw/mips/boston: Check 64-bit support with cpu_type_is_64bit()Philippe Mathieu-Daudé2021-01-141-4/+2Star
* hw/mips/fuloong2e: Correct cpuclock in PROM environmentJiaxun Yang2021-01-041-3/+3
* hw/mips/fuloong2e: Remove unused env entryJiaxun Yang2021-01-041-1/+0Star
* hw/mips/fuloong2e: Replace faulty documentation linksJiaxun Yang2021-01-041-10/+3Star
* hw/mips/fuloong2e: Remove define DEBUG_FULOONG2E_INITJiaxun Yang2021-01-041-2/+0Star
* hw/mips: Use address translation helper to handle ENVP_ADDRJiaxun Yang2021-01-042-43/+43
* hw/mips/malta: Use address translation helper to calculate bootloader_run_addrJiaxun Yang2021-01-041-2/+2
* hw/mips: Make bootloader addresses unsignedJiaxun Yang2021-01-043-21/+21
* hw/mips: Add Loongson-3 machine supportHuacai Chen2021-01-043-1/+651
* hw/mips: Add Loongson-3 boot parameter helpersHuacai Chen2021-01-043-0/+393
* hw/mips: Implement fw_cfg_arch_key_name()Huacai Chen2021-01-044-0/+58
* vt82c686: Remove legacy vt82c686b_pm_init() functionBALATON Zoltan2021-01-041-1/+4
* vt82c686: Remove legacy vt82c686b_isa_init() functionBALATON Zoltan2021-01-041-1/+3
* vt82c686: Remove vt82c686b_[am]c97_init() functionsBALATON Zoltan2021-01-041-2/+2
* hw: Use the PCI_SLOT() macro from 'hw/pci/pci.h'Philippe Mathieu-Daudé2021-01-041-1/+1
* hw/mips/malta: Rewrite CP0_MVPConf0 access using deposit()Philippe Mathieu-Daudé2020-12-131-2/+6
* hw/mips/malta: Do not initialize MT registers if MT ASE absentPhilippe Mathieu-Daudé2020-12-131-1/+3
* target/mips: Introduce ase_mt_available() helperPhilippe Mathieu-Daudé2020-12-131-2/+1Star
* hw/mips: Move address translation helpers to target/mips/Philippe Mathieu-Daudé2020-12-133-53/+1Star
* target/mips: Rename cpu_supports_FEAT() as cpu_type_supports_FEAT()Philippe Mathieu-Daudé2020-12-132-4/+4
* vl: extract softmmu/datadir.cPaolo Bonzini2020-12-104-0/+4
* mips: do not use ram_size globalPaolo Bonzini2020-12-102-3/+3
* mips: remove bios_namePaolo Bonzini2020-12-104-12/+12
* hw/mips/boston: Fix memory leak in boston_fdt_filter() error-handling pathsPeter Maydell2020-11-091-6/+4Star
* hw/mips/boston: Fix Lesser GPL version numberChetan Pant2020-11-031-1/+1
* hw/mips: Fix Lesser GPL version numberChetan Pant2020-11-031-1/+1
* hw/mips: Remove the 'r4k' machinePhilippe Mathieu-Daudé2020-11-033-332/+0Star
* hw/mips: Remove exit(1) in case of missing ROMPavel Dovgalyuk2020-10-174-24/+13Star
* hw/mips: Rename TYPE_MIPS_BOSTON to TYPE_BOSTONEduardo Habkost2020-10-171-4/+4
* hw/mips: Simplify code using ROUND_UP(INITRD_PAGE_SIZE)Philippe Mathieu-Daudé2020-10-174-9/+6Star
* hw/mips: Simplify loading 64-bit ELF kernelsPhilippe Mathieu-Daudé2020-10-172-10/+2Star
* hw/mips/malta: Use clearer qdev stylePhilippe Mathieu-Daudé2020-10-171-4/+4
* hw/mips/malta: Move gt64120 related code togetherPhilippe Mathieu-Daudé2020-10-171-7/+6Star
* hw/mips/malta: Fix FPGA I/O region sizePhilippe Mathieu-Daudé2020-10-171-1/+1
* hw/mips/cps: Do not allow use without input clockPhilippe Mathieu-Daudé2020-10-171-0/+5
* hw/mips/malta: Set CPU frequency to 320 MHzPhilippe Mathieu-Daudé2020-10-171-3/+16
* hw/mips/boston: Set CPU frequency to 1 GHzPhilippe Mathieu-Daudé2020-10-171-0/+13
* hw/mips/cps: Expose input clock and connect it to CPU coresPhilippe Mathieu-Daudé2020-10-171-0/+4
* hw/mips/jazz: Correct CPU frequenciesPhilippe Mathieu-Daudé2020-10-171-1/+14
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