summaryrefslogtreecommitdiffstats
path: root/hw/pci-host/Makefile.objs
Commit message (Collapse)AuthorAgeFilesLines
* hw/pci-host: Add Kconfig entry to select the IGD Passthrough Host BridgePhilippe Mathieu-Daudé2019-12-181-1/+1
| | | | | | | | | | | | Add the XEN_IGD_PASSTHROUGH Kconfig option. Xen build has that option selected by default. Non-Xen builds now have to select this feature manually. Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-Id: <20191209095002.32194-7-philmd@redhat.com> Acked-by: Paul Durrant <paul@xen.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
* hw/pci-host/i440fx: Extract the IGD passthrough host bridge devicePhilippe Mathieu-Daudé2019-12-181-0/+1
| | | | | | | | | | We can use a i440FX without the IGD passthrough host bridge. Extract it into a new file, 'hw/pci-host/xen_igd_pt.c'. Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-Id: <20191209095002.32194-6-philmd@redhat.com> Acked-by: Paul Durrant <paul@xen.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
* hw/pci-host: Rename incorrectly named 'piix' as 'i440fx'Philippe Mathieu-Daudé2019-11-051-1/+1
| | | | | | | | | We moved all the PIIX3 southbridge code out of hw/pci-host/piix.c, it now only contains i440FX northbridge code. Rename it to match the chipset modelled. Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
* build: actually use CONFIG_PAMPaolo Bonzini2019-02-051-1/+1
| | | | | | | | | | | Do not link it unconditionally into all binaries. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Yang Zhong <yang.zhong@intel.com> Reviewed-by: Thomas Huth <thuth@redhat.com> Message-Id: <20190202072456.6468-6-yang.zhong@intel.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
* hw/pci-host/Makefile.objs: make CONFIGS clear for PCI EXPRESSYang Zhong2019-02-051-4/+4
| | | | | | | | | | | | Change the CONFIGs for PCI EXPRESS and make module name more clear for code files. Signed-off-by: Yang Zhong <yang.zhong@intel.com> Cc: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Reviewed-by: Thomas Huth <thuth@redhat.com> Message-Id: <20190202072456.6468-5-yang.zhong@intel.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
* pci: Add support for Designware IP blockAndrey Smirnov2018-03-091-0/+2
| | | | | | | | | | | | | | | Add code needed to get a functional PCI subsytem when using in conjunction with upstream Linux guest (4.13+). Tested to work against "e1000e" (network adapter, using MSI interrupts) as well as "usb-ehci" (USB controller, using legacy PCI interrupts). Based on "i.MX6 Applications Processor Reference Manual" (Document Number: IMX6DQRM Rev. 4) as well as corresponding dirver in Linux kernel (circa 4.13 - 4.16 found in drivers/pci/dwc/*) Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* apb: rename apb.c to sabre.cMark Cave-Ayland2018-01-241-1/+1
| | | | | | | | | | | | | | This is the final stage in correcting the naming convention with respect to sabre, APB and PBM. It is effectively a file rename from apb.c to sabre.c along with touching up a few constants to remove the remaining references to APB. Note that as part of the rename process the configuration variable CONFIG_PCI_APB is changed to CONFIG_PCI_SABRE. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Acked-by: Artyom Tarasenko <atar4qemu@gmail.com>
* hw: xilinx-pcie: Add support for Xilinx AXI PCIe ControllerPaul Burton2017-02-221-0/+1
| | | | | | | | | | | | | | | | Add support for emulating the Xilinx AXI Root Port Bridge for PCI Express as described by Xilinx' PG055 document. This is a PCIe controller that can be used with certain series of Xilinx FPGAs, and is used on the MIPS Boston board which will make use of this code. Signed-off-by: Paul Burton <paul.burton@imgtec.com> [yongbok.kim@imgtec.com: removed returning on !level, updated IRQ connection with GPIO logic, moved xilinx_pcie_init() to boston.c replaced stw_le_p() with pci_set_word() and other cosmetic changes] Signed-off-by: Yongbok Kim <yongbok.kim@imgtec.com>
* pci: Add generic PCIe host bridgeAlexander Graf2015-02-131-0/+1
| | | | | | | | | | | | | | | | | With simple exposure of MMFG, ioport window, mmio window and an IRQ line we can successfully create a workable PCIe host bridge that can be mapped anywhere and only needs to get described to the OS using whatever means it likes. This patch implements such a "generic" host bridge. It handles 4 legacy IRQ lines. MSIs need to be handled external to the host bridge. This device is particularly useful for the "pci-host-ecam-generic" driver in Linux. Signed-off-by: Alexander Graf <agraf@suse.de> Reviewed-by: Claudio Fontana <claudio.fontana@huawei.com> Tested-by: Claudio Fontana <claudio.fontana@huawei.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* dec.c - move to pci-bridgeMichael S. Tsirkin2013-06-021-1/+0Star
| | | | | | | | Looks like dec.c is in pci-host by mistake. Moving it over to pci-bridge. Acked-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
* hw: move PCI bridges to hw/pci-* or hw/ARCHPaolo Bonzini2013-04-081-0/+18
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>