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* hw/riscv: Split out the boot functionsAlistair Francis2019-06-271-46/+5Star
| | | | | | | | | | Split the common RISC-V boot functions into a seperate file. This allows us to share the common code. Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
* riscv: virt: Add cpu-topology DT node.Atish Patra2019-06-261-2/+20
| | | | | | | | | | | | | | | | | | | | | | | | | Currently, there is no cpu topology defined in RISC-V. Define a device tree node that clearly describes the entire topology. This saves the trouble of scanning individual cache to figure out the topology. Here is the linux kernel patch series that enables topology for RISC-V. http://lists.infradead.org/pipermail/linux-riscv/2019-June/005072.html CPU topology after applying this patch in QEMU & above series in kernel / # cat /sys/devices/system/cpu/cpu2/topology/thread_siblings_list 2 / # cat /sys/devices/system/cpu/cpu2/topology/physical_package_id 0 / # cat /sys/devices/system/cpu/cpu2/topology/core_siblings_list 0-7 Signed-off-by: Atish Patra <atish.patra@wdc.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
* riscv: virt: Correct pci "bus-range" encodingBin Meng2019-06-241-1/+1
| | | | | | | | | The largest pci bus number should be calculated from ECAM size, instead of its base address. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
* riscv: virt: Allow specifying a CPU via commandlineAlistair Francis2019-05-241-1/+2
| | | | | | Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Igor Mammedov <imammedo@redhat.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
* target/riscv: Remove unused include of riscv_htif.h for virt board riscvJonathan Behrens2019-05-241-1/+0Star
| | | | | | | Signed-off-by: Jonathan Behrens <fintelia@gmail.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
* riscv: Ensure the kernel start address is correctly castAlistair Francis2019-02-121-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Cast the kernel start address to the target bit length. This ensures that we calculate the initrd offset to a valid address for the architecture. Steps to reproduce the original problem (reported by Alex): Build U-Boot for the virt machine for riscv32. Then run it with $ qemu-system-riscv32 -M virt -kernel u-boot -nographic -initrd <a file> You can find the initrd address with U-Boot# fdt addr $fdtcontroladdr U-Boot# fdt ls /chosen Then take a peek at that address: U-Boot# md.b <addr> and you will see that there is nothing there without this patch. The reason is that the binary was loaded to a negative address. Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Suggested-by: Alexander Graf <agraf@suse.de> Reported-by: Alexander Graf <agraf@suse.de> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
* elf: Add optional function ptr to load_elf() to parse ELF notesLiam Merwick2019-02-051-1/+1
| | | | | | | | | | | | | | | | | | | This patch adds an optional function pointer, 'elf_note_fn', to load_elf() which causes load_elf() to additionally parse any ELF program headers of type PT_NOTE and check to see if the ELF Note is of the type specified by the 'translate_opaque' arg. If a matching ELF Note is found then the specfied function pointer is called to process the ELF note. Passing a NULL function pointer results in ELF Notes being skipped. The first consumer of this functionality is the PVHboot support which needs to read the XEN_ELFNOTE_PHYS32_ENTRY ELF Note while loading the uncompressed kernel binary in order to discover the boot entry address for the x86/HVM direct boot ABI. Signed-off-by: Liam Merwick <liam.merwick@oracle.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
* hw/riscv/virt: Connect the gpex PCIeAlistair Francis2018-12-201-1/+130
| | | | | | | | | | | | Connect the gpex PCIe device based on the device tree included in the HiFive Unleashed ROM. Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Logan Gunthorpe <logang@deltatee.com> Reviewed-by: Logan Gunthorpe <logang@deltatee.com> Tested-by: Guenter Roeck <linux@roeck-us.net> Tested-by: Andrea Bolognani <abologna@redhat.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
* hw/riscv/virt: Adjust memory layout spacingAlistair Francis2018-12-201-8/+8
| | | | | | | | Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Logan Gunthorpe <logang@deltatee.com> Tested-by: Guenter Roeck <linux@roeck-us.net> Tested-by: Andrea Bolognani <abologna@redhat.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
* hw/riscv/virt: Free the test device tree node nameAlistair Francis2018-11-141-0/+1
| | | | | Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
* RISC-V: Don't add NULL bootargs to device-treeMichael Clark2018-10-171-1/+3
| | | | | | | | | Signed-off-by: Michael Clark <mjc@sifive.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
* RISC-V: Add missing free for plic_hart_configMichael Clark2018-10-171-0/+2
| | | | | | | | | Signed-off-by: Michael Clark <mjc@sifive.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
* Merge remote-tracking branch 'remotes/armbru/tags/pull-error-2018-09-24' ↵Peter Maydell2018-09-251-2/+2
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | into staging Error reporting & miscellaneous patches for 2018-09-24 # gpg: Signature made Mon 24 Sep 2018 16:16:50 BST # gpg: using RSA key 3870B400EB918653 # gpg: Good signature from "Markus Armbruster <armbru@redhat.com>" # gpg: aka "Markus Armbruster <armbru@pond.sub.org>" # Primary key fingerprint: 354B C8B3 D7EB 2A6B 6867 4E5F 3870 B400 EB91 8653 * remotes/armbru/tags/pull-error-2018-09-24: MAINTAINERS: Fix F: patterns that don't match anything Drop "qemu:" prefix from error_report() arguments qemu-error: make use of {error, warn}_report_once_cond qemu-error: add {error, warn}_report_once_cond Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * Drop "qemu:" prefix from error_report() argumentsMao Zhongyi2018-09-241-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | error_report and friends already add a "qemu-system-xxx" prefix to the string, so a "qemu:" prefix is redundant in the string. Just drop it. Reported-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Mao Zhongyi <maozhongyi@cmss.chinamobile.com> Reviewed-by: Eduardo Habkost <ehabkost@redhat.com> Message-Id: <1537495530-580-1-git-send-email-maozhongyi@cmss.chinamobile.com> Acked-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Markus Armbruster <armbru@redhat.com>
* | hw/riscv/virtio: Set the soc device tree node as a simple-busAlistair Francis2018-09-051-1/+1
|/ | | | | | | | To allow Linux to enumerate devices on the /soc/ node set it as a "simple-bus". Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
* virt: Fix crash when introspecting the deviceAlistair Francis2018-07-191-3/+2Star
| | | | | | | | | | | | Use the new object_initialize_child() and sysbus_init_child_obj() to fix the issue. Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Suggested-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Michael Clark <mjc@sifive.com> Reviewed-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
* hw/riscv/sifive_plic: Use gpios instead of irqsAlistair Francis2018-07-061-2/+2
| | | | | | | | | | | Instead of creating the interrupt in lines with qemu_allocate_irq() use qdev_init_gpio_in() as this gives us the ability to use the qdev*gpio*() helpers later on. Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Suggested-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Michael Clark <mjc@sifive.com>
* hw/riscv: Use the IEC binary prefix definitionsPhilippe Mathieu-Daudé2018-07-021-1/+2
| | | | | | | | | | | | | | | It eases code review, unit is explicit. Patch generated using: $ git grep -E '(1024|2048|4096|8192|(<<|>>).?(10|20|30))' hw/ include/hw/ and modified manually. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Michael Clark <mjc@sifive.com> Message-Id: <20180625124238.25339-17-f4bug@amsat.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
* RISC-V: Mark ROM read-only after copying in codeMichael Clark2018-05-061-19/+24
| | | | | | | | | | | | | | | | | | | | The sifive_u machine already marks its ROM readonly however it has the wrong base address for its mask ROM. This patch fixes the sifive_u mask ROM base address. This commit makes all other boards consistently use mask_rom as the variable name for their ROMs. Boards that use device tree now check that that the device tree fits in the assigned ROM space using the new qemu_fdt_totalsize(void *fdt) interface, adding a bounds check and error message. This can detect truncation. Cc: Sagar Karandikar <sagark@eecs.berkeley.edu> Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Cc: Palmer Dabbelt <palmer@sifive.com> Cc: Alistair Francis <Alistair.Francis@wdc.com> Signed-off-by: Michael Clark <mjc@sifive.com> Reviewed-by: Alistair Francis <Alistair.Francis@wdc.com>
* RISC-V: Remove EM_RISCV ELF_MACHINE indirectionMichael Clark2018-05-061-1/+1
| | | | | | | | | | | Pointless indirection. Other ports use EM_ constants directly. Cc: Sagar Karandikar <sagark@eecs.berkeley.edu> Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Signed-off-by: Michael Clark <mjc@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
* RISC-V: Remove unused class definitionsMichael Clark2018-05-061-25/+0Star
| | | | | | | | | | | | | | | Removes a whole lot of unnecessary boilerplate code. Machines don't need to be objects. The expansion of the SOC object model for the RISC-V machines will happen in the future as SiFive plans to add their FE310 and FU540 SOCs to QEMU. However, it seems that this present boilerplate is complete unnecessary. Cc: Sagar Karandikar <sagark@eecs.berkeley.edu> Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Signed-off-by: Michael Clark <mjc@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
* RISC-V: Remove identity_translate from load_elfMichael Clark2018-05-061-6/+1Star
| | | | | | | | | | | | | When load_elf is called with NULL as an argument to the address translate callback, it does an identity translation. This commit removes the redundant identity_translate callback. Cc: Sagar Karandikar <sagark@eecs.berkeley.edu> Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Signed-off-by: Michael Clark <mjc@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
* RISC-V: Use ROM base address and size from memmapMichael Clark2018-05-061-2/+2
| | | | | | | | | | | | Another case of replacing hard coded constants, this time referring to the definition in the virt machine's memmap. Cc: Sagar Karandikar <sagark@eecs.berkeley.edu> Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Signed-off-by: Michael Clark <mjc@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
* RISC-V: Make virt board description match spikeMichael Clark2018-05-061-1/+1
| | | | | | | | | | | | This makes 'qemu-system-riscv64 -machine help' output more tidy and consistent. Cc: Sagar Karandikar <sagark@eecs.berkeley.edu> Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Signed-off-by: Michael Clark <mjc@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
* RISC-V: Replace hardcoded constants with enum valuesMichael Clark2018-05-061-2/+4
| | | | | | | | | | | | The RISC-V device-tree code has a number of hard-coded constants and this change moves them into header enums. Cc: Sagar Karandikar <sagark@eecs.berkeley.edu> Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Signed-off-by: Michael Clark <mjc@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
* Change references to serial_hds[] to serial_hd()Peter Maydell2018-04-261-1/+1
| | | | | | | | | | Change all the uses of serial_hds[] to go via the new serial_hd() function. Code change produced with: find hw -name '*.[ch]' | xargs sed -i -e 's/serial_hds\[\([^]]*\)\]/serial_hd(\1)/g' Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Message-id: 20180420145249.32435-8-peter.maydell@linaro.org
* RISC-V VirtIO MachineMichael Clark2018-03-061-0/+420
RISC-V machine with device-tree, 16550a UART and VirtIO MMIO. The following machine is implemented: - 'virt'; CLINT, PLIC, 16550A UART, VirtIO MMIO, device-tree Acked-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Michael Clark <mjc@sifive.com>
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