summaryrefslogtreecommitdiffstats
path: root/hw
Commit message (Collapse)AuthorAgeFilesLines
...
| * | hw/arm/aspeed: Add Fuji machine typePeter Delevoryas2021-09-201-0/+120
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This adds a new machine type "fuji-bmc" based on the following device tree: https://github.com/torvalds/linux/blob/40cb6373b46/arch/arm/boot/dts/aspeed-bmc-facebook-fuji.dts Most of the i2c devices are not there, they're added here: https://github.com/facebook/openbmc/blob/fb2ed12002fb/meta-facebook/meta-fuji/recipes-utils/openbmc-utils/files/setup_i2c.sh I tested this by building a Fuji image from Facebook's OpenBMC repo, booting, and ssh'ing from host-to-guest. Signed-off-by: Peter Delevoryas <pdel@fb.com> Reviewed-by: Joel Stanley <joel@jms.id.au> [ clg: On 32-bit hosts, lower RAM to 1G because of 2047 MB limit ] Message-Id: <20210906133124.3674661-1-pdel@fb.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
| * | hw/arm/aspeed: Allow machine to set UART defaultPeter Delevoryas2021-09-203-7/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When you run QEMU with an Aspeed machine and a single serial device using stdio like this: qemu -machine ast2600-evb -drive ... -serial stdio The guest OS can read and write to the UART5 registers at 0x1E784000 and it will receive from stdin and write to stdout. The Aspeed SoC's have a lot more UART's though (AST2500 has 5, AST2600 has 13) and depending on the board design, may be using any of them as the serial console. (See "stdout-path" in a DTS to check which one is chosen). Most boards, including all of those currently defined in hw/arm/aspeed.c, just use UART5, but some use UART1. This change adds some flexibility for different boards without requiring users to change their command-line invocation of QEMU. I tested this doesn't break existing code by booting an AST2500 OpenBMC image and an AST2600 OpenBMC image, each using UART5 as the console. Then I tested switching the default to UART1 and booting an AST2600 OpenBMC image that uses UART1, and that worked too. Signed-off-by: Peter Delevoryas <pdel@fb.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20210901153615.2746885-2-pdel@fb.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
| * | hw/arm/aspeed: Initialize AST2600 UART clock selection registersPeter Delevoryas2021-09-201-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | UART5 is typically used as the default debug UART on the AST2600, but UART1 is also designed to be a debug UART. All the AST2600 UART's have semi-configurable clock rates through registers in the System Control Unit (SCU), but only UART5 works out of the box with zero-initialized values. The rest of the UART's expect a few of the registers to be initialized to non-zero values, or else the clock rate calculation will yield zero or undefined (due to a divide-by-zero). For reference, the U-Boot clock rate driver here shows the calculation: https://github.com/facebook/openbmc-uboot/blob/15f7e0dc01d8/drivers/clk/aspeed/clk_ast2600.c#L357 To summarize, UART5 allows selection from 4 rates: 24 MHz, 192 MHz, 24 / 13 MHz, and 192 / 13 MHz. The other UART's allow selecting either the "low" rate (UARTCLK) or the "high" rate (HUARTCLK). UARTCLK and HUARTCLK are configurable themselves: UARTCLK = UXCLK * R / (N * 2) HUARTCLK = HUXCLK * HR / (HN * 2) UXCLK and HUXCLK are also configurable, and depend on the APLL and/or HPLL clock rates, which also derive from complicated calculations. Long story short, there's lots of multiplication and division from configurable registers, and most of these registers are zero-initialized in QEMU, which at best is unexpected and at worst causes this clock rate driver to hang from divide-by-zero's. This can also be difficult to diagnose, because it may cause U-Boot to hang before serial console initialization completes, requiring intervention from gdb. This change just initializes all of these registers with default values from the datasheet. To test this, I used Facebook's AST2600 OpenBMC image for "fuji", with the following diff applied (because fuji uses UART1 for console output, not UART5). @@ -323,8 +323,8 @@ static void aspeed_soc_ast2600_realize(DeviceState *dev, Error **errp) } /* UART - attach an 8250 to the IO space as our UART5 */ - serial_mm_init(get_system_memory(), sc->memmap[ASPEED_DEV_UART5], 2, - aspeed_soc_get_irq(s, ASPEED_DEV_UART5), + serial_mm_init(get_system_memory(), sc->memmap[ASPEED_DEV_UART1], 2, + aspeed_soc_get_irq(s, ASPEED_DEV_UART1), 38400, serial_hd(0), DEVICE_LITTLE_ENDIAN); /* I2C */ Without these clock rate registers being initialized, U-Boot hangs in the clock rate driver from a divide-by-zero, because the UART1 clock rate register reads return zero, and there's no console output. After initializing them with default values, fuji boots successfully. Signed-off-by: Peter Delevoryas <pdel@fb.com> Reviewed-by: Joel Stanley <joel@jms.id.au> [ clg: Removed _PARAM suffix ] Message-Id: <20210906134023.3711031-2-pdel@fb.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
| * | arm/aspeed: Add DPS310 to Witherspoon and RainierJoel Stanley2021-09-201-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Witherspoon uses the DPS310 as a temperature sensor. Rainier uses it as a temperature and humidity sensor. Signed-off-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20210629142336.750058-5-clg@kaod.org> Signed-off-by: Cédric Le Goater <clg@kaod.org>
| * | hw/misc: Add Infineon DPS310 sensor modelJoel Stanley2021-09-204-0/+231
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This contains some hardcoded register values that were obtained from the hardware after reading the temperature. It does enough to test the Linux kernel driver. The FIFO mode, IRQs and operation modes other than the default as used by Linux are not modelled. Signed-off-by: Joel Stanley <joel@jms.id.au> Message-Id: <20210616073358.750472-2-joel@jms.id.au> [ clg: - Fixed sequential reading - Reworked regs_reset_state array - Moved model under hw/sensor/ ] Message-Id: <20210629142336.750058-4-clg@kaod.org> Signed-off-by: Cédric Le Goater <clg@kaod.org>
| * | aspeed: Emulate the AST2600A3Joel Stanley2021-09-203-13/+35
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is the latest revision of the ASPEED 2600 SoC. As there is no need to model multiple revisions of the same SoC for the moment, update the SCU AST2600 to model the A3 revision instead of the A1 and adapt the AST2600 SoC and machines. Reset values are taken from v8 of the datasheet. Signed-off-by: Joel Stanley <joel@jms.id.au> [ clg: - Introduced an Aspeed "ast2600-a3" SoC class - Commit log update ] Message-Id: <20210629142336.750058-3-clg@kaod.org> Signed-off-by: Cédric Le Goater <clg@kaod.org>
| * | arm/aspeed: rainier: Add i2c eeproms and muxesJoel Stanley2021-09-201-0/+44
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | These are the devices documented by the Rainier device tree. With this we can see the guest discovering the multiplexers and probing the eeprom devices: i2c i2c-2: Added multiplexed i2c bus 16 i2c i2c-2: Added multiplexed i2c bus 17 i2c i2c-2: Added multiplexed i2c bus 18 i2c i2c-2: Added multiplexed i2c bus 19 i2c-mux-gpio i2cmux: 4 port mux on 1e78a180.i2c-bus adapter at24 20-0050: 8192 byte 24c64 EEPROM, writable, 1 bytes/write i2c i2c-4: Added multiplexed i2c bus 20 at24 21-0051: 8192 byte 24c64 EEPROM, writable, 1 bytes/write i2c i2c-4: Added multiplexed i2c bus 21 at24 22-0052: 8192 byte 24c64 EEPROM, writable, 1 bytes/write Signed-off-by: Joel Stanley <joel@jms.id.au> [ clg: Introduced aspeed_eeprom_init ] Message-Id: <20210629142336.750058-2-clg@kaod.org> Signed-off-by: Cédric Le Goater <clg@kaod.org>
| * | misc/pca9552: Fix LED status register indexing in pca955x_get_led()Andrew Jeffery2021-09-201-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There was a bit of a thinko in the state calculation where every odd pin in was reported in e.g. "pwm0" mode rather than "off". This was the result of an incorrect bit shift for the 2-bit field representing each LED state. Fixes: a90d8f84674d ("misc/pca9552: Add qom set and get") Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Reviewed-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20210723043624.348158-1-andrew@aj.id.au> Signed-off-by: Cédric Le Goater <clg@kaod.org>
| * | hw: aspeed_gpio: Clarify GPIO controller nameJoel Stanley2021-09-201-13/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There are two GPIO controllers in the ast2600; one is 3.3V and the other is 1.8V. Signed-off-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Rashmica Gupta <rashmica.g@gmail.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20210713065854.134634-4-joel@jms.id.au> Signed-off-by: Cédric Le Goater <clg@kaod.org>
| * | hw: aspeed_gpio: Simplify 1.8V definesJoel Stanley2021-09-201-37/+36Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There's no need to define the registers relative to the 0x800 offset where the controller is mapped, as the device is instantiated as it's own model at the correct memory address. Simplify the defines and remove the offset to save future confusion. Signed-off-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Rashmica Gupta <rashmica.g@gmail.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210713065854.134634-3-joel@jms.id.au> Signed-off-by: Cédric Le Goater <clg@kaod.org>
| * | watchdog: aspeed: Fix sequential control writesAndrew Jeffery2021-09-201-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The logic in the handling for the control register required toggling the enable state for writes to stick. Rework the condition chain to allow sequential writes that do not update the enable state. Fixes: 854123bf8d4b ("wdt: Add Aspeed watchdog device model") Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Reviewed-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20210709053107.1829304-3-andrew@aj.id.au> Signed-off-by: Cédric Le Goater <clg@kaod.org>
| * | watchdog: aspeed: Sanitize control register valuesAndrew Jeffery2021-09-201-2/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | While some of the critical fields remain the same, there is variation in the definition of the control register across the SoC generations. Reserved regions are adjusted, while in other cases the mutability or behaviour of fields change. Introduce a callback to sanitize the value on writes to ensure model behaviour reflects the hardware. Fixes: 854123bf8d4b ("wdt: Add Aspeed watchdog device model") Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Reviewed-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20210709053107.1829304-2-andrew@aj.id.au> Signed-off-by: Cédric Le Goater <clg@kaod.org>
| * | hw: arm: aspeed: Enable mac0/1 instead of mac1/2 for g220aGuenter Roeck2021-09-201-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | According to its dts file in the Linux kernel, we need mac0 and mac1 enabled instead of mac1 and mac2. Also, g220a is based on aspeed-g5 (ast2500) which doesn't even have the third interface. Signed-off-by: Guenter Roeck <linux@roeck-us.net> Reviewed-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20210810035742.550391-1-linux@roeck-us.net> Signed-off-by: Cédric Le Goater <clg@kaod.org>
| * | hw: arm: aspeed: Enable eth0 interface for aspeed-ast2600-evbGuenter Roeck2021-09-201-1/+2
| |/ | | | | | | | | | | | | | | | | | | | | | | Commit 7582591ae7 ("aspeed: Support AST2600A1 silicon revision") switched the silicon revision for AST2600 to revision A1. On revision A1, the first Ethernet interface is operational. Enable it. Signed-off-by: Guenter Roeck <linux@roeck-us.net> Reviewed-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20210808200457.889955-1-linux@roeck-us.net> Signed-off-by: Cédric Le Goater <clg@kaod.org>
* / virtio-net: fix use after unmap/free for sgJason Wang2021-09-171-7/+32
|/ | | | | | | | | | | | | | | | | | | When mergeable buffer is enabled, we try to set the num_buffers after the virtqueue elem has been unmapped. This will lead several issues, E.g a use after free when the descriptor has an address which belongs to the non direct access region. In this case we use bounce buffer that is allocated during address_space_map() and freed during address_space_unmap(). Fixing this by storing the elems temporarily in an array and delay the unmap after we set the the num_buffers. This addresses CVE-2021-3748. Reported-by: Alexander Bulekov <alxndr@bu.edu> Fixes: fbe78f4f55c6 ("virtio-net support") Cc: qemu-stable@nongnu.org Signed-off-by: Jason Wang <jasowang@redhat.com>
* Merge remote-tracking branch ↵Peter Maydell2021-09-166-13/+13
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 'remotes/vivier2/tags/trivial-branch-for-6.2-pull-request' into staging Trivial patches pull request 20210916 # gpg: Signature made Thu 16 Sep 2021 15:09:39 BST # gpg: using RSA key CD2F75DDC8E3A4DC2E4F5173F30C38BD3F2FBE3C # gpg: issuer "laurent@vivier.eu" # gpg: Good signature from "Laurent Vivier <lvivier@redhat.com>" [full] # gpg: aka "Laurent Vivier <laurent@vivier.eu>" [full] # gpg: aka "Laurent Vivier (Red Hat) <lvivier@redhat.com>" [full] # Primary key fingerprint: CD2F 75DD C8E3 A4DC 2E4F 5173 F30C 38BD 3F2F BE3C * remotes/vivier2/tags/trivial-branch-for-6.2-pull-request: target/sparc: Make sparc_cpu_dump_state() static target/avr: Fix compiler errors (-Werror=enum-conversion) hw/vfio: Fix typo in comments intel_iommu: Fix typo in comments target/i386: spelling: occured=>occurred, mininum=>minimum configure: add missing pc-bios/qemu_vga.ndrv symlink in build tree spelling: sytem => system qdev: Complete qdev_init_gpio_out() documentation hw/i386/acpi-build: Fix a typo util: Remove redundant checks in the openpty() Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * hw/vfio: Fix typo in commentsCai Huoqing2021-09-164-6/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fix typo in comments: *programatically ==> programmatically *disconecting ==> disconnecting *mulitple ==> multiple *timout ==> timeout *regsiter ==> register *forumula ==> formula Signed-off-by: Cai Huoqing <caihuoqing@baidu.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-Id: <20210730012613.2198-1-caihuoqing@baidu.com> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
| * intel_iommu: Fix typo in commentsCai Huoqing2021-09-161-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | Fix typo: *Unknwon ==> Unknown *futher ==> further *configed ==> configured Signed-off-by: Cai Huoqing <caihuoqing@baidu.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Acked-by: Peter Xu <peterx@redhat.com> Message-Id: <20210730014942.2311-1-caihuoqing@baidu.com> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
| * hw/i386/acpi-build: Fix a typoPhilippe Mathieu-Daudé2021-09-151-3/+3
| | | | | | | | | | | | | | | | | | Fix 'hotplugabble' -> 'hotpluggable' typo. Reviewed-by: Ani Sinha <ani@anisinha.ca> Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-Id: <20210911082036.436139-1-philmd@redhat.com> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
* | virtio-gpu: Add gl_flushed callbackVivek Kasireddy2021-09-151-2/+30
| | | | | | | | | | | | | | | | | | | | | | | | Adding this callback provides a way to resume the processing of cmds in fenceq and cmdq that were not processed because the UI was waiting on a fence and blocked cmd processing. Cc: Gerd Hoffmann <kraxel@redhat.com> Reviewed-by: Gerd Hoffmann <kraxel@redhat.com> Signed-off-by: Vivek Kasireddy <vivek.kasireddy@intel.com> Message-Id: <20210914211837.3229977-6-vivek.kasireddy@intel.com> Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
* | ui: Create sync objects and fences only for blobsVivek Kasireddy2021-09-151-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | Create sync objects and fences only for dmabufs that are blobs. Once a fence is created (after glFlush) and is signalled, graphic_hw_gl_flushed() will be called and virtio-gpu cmd processing will be resumed. Cc: Gerd Hoffmann <kraxel@redhat.com> Signed-off-by: Vivek Kasireddy <vivek.kasireddy@intel.com> Message-Id: <20210914211837.3229977-4-vivek.kasireddy@intel.com> Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
* | qxl: fix pre-save logicGerd Hoffmann2021-09-151-1/+1
|/ | | | | | | | | | | | Oops. Logic is backwards. Fixes: 39b8a183e2f3 ("qxl: remove assert in qxl_pre_save.") Resolves: https://gitlab.com/qemu-project/qemu/-/issues/610 Resolves: https://bugzilla.redhat.com//show_bug.cgi?id=2002907 Signed-off-by: Gerd Hoffmann <kraxel@redhat.com> Reviewed-by: Daniel P. Berrangé <berrange@redhat.com> Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com> Message-Id: <20210910094203.3582378-1-kraxel@redhat.com>
* Merge remote-tracking branch ↵Peter Maydell2021-09-1316-80/+1891
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 'remotes/pmaydell/tags/pull-target-arm-20210913-3' into staging target-arm queue: * mark MPS2/MPS3 board-internal i2c buses as 'full' so that command line user-created devices are not plugged into them * Take an exception if PSTATE.IL is set * Support an emulated ITS in the virt board * Add support for kudo-bmc board * Probe for KVM_CAP_ARM_VM_IPA_SIZE when creating scratch VM * cadence_uart: Fix clock handling issues that prevented u-boot from running # gpg: Signature made Mon 13 Sep 2021 21:04:52 BST # gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE # gpg: issuer "peter.maydell@linaro.org" # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [ultimate] # gpg: aka "Peter Maydell <pmaydell@gmail.com>" [ultimate] # gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [ultimate] # Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE * remotes/pmaydell/tags/pull-target-arm-20210913-3: (23 commits) hw/arm/mps2.c: Mark internal-only I2C buses as 'full' hw/arm/mps2-tz.c: Mark internal-only I2C buses as 'full' hw/arm/mps2-tz.c: Add extra data parameter to MakeDevFn qdev: Support marking individual buses as 'full' target/arm: Merge disas_a64_insn into aarch64_tr_translate_insn target/arm: Take an exception if PSTATE.IL is set tests/data/acpi/virt: Update IORT files for ITS hw/arm/virt: add ITS support in virt GIC tests/data/acpi/virt: Add IORT files for ITS hw/intc: GICv3 redistributor ITS processing hw/intc: GICv3 ITS Feature enablement hw/intc: GICv3 ITS Command processing hw/intc: GICv3 ITS command queue framework hw/intc: GICv3 ITS register definitions added hw/intc: GICv3 ITS initial framework hw/arm: Add support for kudo-bmc board. hw/arm/virt: KVM: Probe for KVM_CAP_ARM_VM_IPA_SIZE when creating scratch VM hw/char: cadence_uart: Log a guest error when device is unclocked or in reset hw/char: cadence_uart: Ignore access when unclocked or in reset for uart_{read, write}() hw/char: cadence_uart: Convert to memop_with_attrs() ops ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * hw/arm/mps2.c: Mark internal-only I2C buses as 'full'Peter Maydell2021-09-131-1/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The various MPS2 boards implemented in mps2.c have multiple I2C buses: a bus dedicated to the audio configuration, one for the LCD touchscreen controller, and two which are connected to the external Shield expansion connector. Mark the buses which are used only for board-internal devices as 'full' so that if the user creates i2c devices on the commandline without specifying a bus name then they will be connected to the I2C controller used for the Shield connector, where guest software will expect them. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210903151435.22379-5-peter.maydell@linaro.org
| * hw/arm/mps2-tz.c: Mark internal-only I2C buses as 'full'Peter Maydell2021-09-131-14/+43
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The various MPS2 boards have multiple I2C buses: typically a bus dedicated to the audio configuration, one for the LCD touchscreen controller, one for a DDR4 EEPROM, and two which are connected to the external Shield expansion connector. Mark the buses which are used only for board-internal devices as 'full' so that if the user creates i2c devices on the commandline without specifying a bus name then they will be connected to the I2C controller used for the Shield connector, where guest software will expect them. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210903151435.22379-4-peter.maydell@linaro.org
| * hw/arm/mps2-tz.c: Add extra data parameter to MakeDevFnPeter Maydell2021-09-131-13/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The mps2-tz boards use a data-driven structure to create the devices that sit behind peripheral protection controllers. Currently the functions which create these devices are passed an 'opaque' pointer which is always the address within the machine struct of the device to create, and some "all devices need this" information like irqs and addresses. If a specific device needs more information than this, it is currently not possible to pass that through from the PPCInfo data structure. Add support for passing an extra data parameter, so that we can more flexibly handle the needs of specific device types. To provide some type-safety we make this extra parameter a pointer to a union (which initially has no members). In particular, we would like to be able to indicate which of the i2c controllers are for on-board devices only and which are connected to the external 'shield' expansion port; a subsequent patch will use this mechanism for that purpose. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210903151435.22379-3-peter.maydell@linaro.org
| * hw/arm/virt: add ITS support in virt GICShashi Mallela2021-09-131-2/+27
| | | | | | | | | | | | | | | | | | | | | | | | Included creation of ITS as part of virt platform GIC initialization. This Emulated ITS model now co-exists with kvm ITS and is enabled in absence of kvm irq kernel support in a platform. Signed-off-by: Shashi Mallela <shashi.mallela@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20210910143951.92242-9-shashi.mallela@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * hw/intc: GICv3 redistributor ITS processingShashi Mallela2021-09-136-2/+193
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Implemented lpi processing at redistributor to get lpi config info from lpi configuration table,determine priority,set pending state in lpi pending table and forward the lpi to cpuif.Added logic to invoke redistributor lpi processing with translated LPI which set/clear LPI from ITS device as part of ITS INT,CLEAR,DISCARD command and GITS_TRANSLATER processing. Signed-off-by: Shashi Mallela <shashi.mallela@linaro.org> Tested-by: Neil Armstrong <narmstrong@baylibre.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20210910143951.92242-7-shashi.mallela@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * hw/intc: GICv3 ITS Feature enablementShashi Mallela2021-09-134-4/+27
| | | | | | | | | | | | | | | | | | | | | | | | Added properties to enable ITS feature and define qemu system address space memory in gicv3 common,setup distributor and redistributor registers to indicate LPI support. Signed-off-by: Shashi Mallela <shashi.mallela@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Tested-by: Neil Armstrong <narmstrong@baylibre.com> Message-id: 20210910143951.92242-6-shashi.mallela@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * hw/intc: GICv3 ITS Command processingShashi Mallela2021-09-132-1/+376
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Added ITS command queue handling for MAPTI,MAPI commands,handled ITS translation which triggers an LPI via INT command as well as write to GITS_TRANSLATER register,defined enum to differentiate between ITS command interrupt trigger and GITS_TRANSLATER based interrupt trigger. Each of these commands make use of other functionalities implemented to get device table entry,collection table entry or interrupt translation table entry required for their processing. Signed-off-by: Shashi Mallela <shashi.mallela@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20210910143951.92242-5-shashi.mallela@linaro.org [PMM: use INTERRUPT for ItsCmdType enum name to avoid conflict with INT type defined by Windows headers] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * hw/intc: GICv3 ITS command queue frameworkShashi Mallela2021-09-132-0/+359
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Added functionality to trigger ITS command queue processing on write to CWRITE register and process each command queue entry to identify the command type and handle commands like MAPD,MAPC,SYNC. Signed-off-by: Shashi Mallela <shashi.mallela@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Eric Auger <eric.auger@redhat.com> Tested-by: Neil Armstrong <narmstrong@baylibre.com> Message-id: 20210910143951.92242-4-shashi.mallela@linaro.org [PMM: fixed format string nit] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * hw/intc: GICv3 ITS register definitions addedShashi Mallela2021-09-132-0/+405
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Defined descriptors for ITS device table,collection table and ITS command queue entities.Implemented register read/write functions, extract ITS table parameters and command queue parameters,extended gicv3 common to capture qemu address space(which host the ITS table platform memories required for subsequent ITS processing) and initialize the same in ITS device. Signed-off-by: Shashi Mallela <shashi.mallela@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Eric Auger <eric.auger@redhat.com> Tested-by: Neil Armstrong <narmstrong@baylibre.com> Message-id: 20210910143951.92242-3-shashi.mallela@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * hw/intc: GICv3 ITS initial frameworkShashi Mallela2021-09-135-13/+334
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Added register definitions relevant to ITS,implemented overall ITS device framework with stubs for ITS control and translater regions read/write,extended ITS common to handle mmio init between existing kvm device and newer qemu device. Signed-off-by: Shashi Mallela <shashi.mallela@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Eric Auger <eric.auger@redhat.com> Tested-by: Neil Armstrong <narmstrong@baylibre.com> Message-id: 20210910143951.92242-2-shashi.mallela@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * hw/arm: Add support for kudo-bmc board.Chris Rauer2021-09-131-0/+34
| | | | | | | | | | | | | | | | | | | | | | | | | | | | kudo-bmc is a board supported by OpenBMC. https://github.com/openbmc/openbmc/tree/master/meta-fii/meta-kudo Since v1: - hyphenated Cortex-A9 Tested: Booted kudo firmware. Signed-off-by: Chris Rauer <crauer@google.com> Reviewed-by: Patrick Venture <venture@google.com> Message-id: 20210907223234.1165705-1-crauer@google.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * hw/char: cadence_uart: Log a guest error when device is unclocked or in resetBin Meng2021-09-131-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We've got SW that expects FSBL (Bootlooader) to setup clocks and resets. It's quite common that users run that SW on QEMU without FSBL (FSBL typically requires the Xilinx tools installed). That's fine, since users can stil use -device loader to enable clocks etc. To help folks understand what's going, a log (guest-error) message would be helpful here. In particular with the serial port since things will go very quiet if they get things wrong. Suggested-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20210901124521.30599-7-bmeng.cn@gmail.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * hw/char: cadence_uart: Ignore access when unclocked or in reset for ↵Bin Meng2021-09-131-5/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | uart_{read, write}() Read or write to uart registers when unclocked or in reset should be ignored. Add the check there, and as a result of this, the check in uart_write_tx_fifo() is now unnecessary. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20210901124521.30599-6-bmeng.cn@gmail.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * hw/char: cadence_uart: Convert to memop_with_attrs() opsBin Meng2021-09-131-11/+15
| | | | | | | | | | | | | | | | | | | | This converts uart_read() and uart_write() to memop_with_attrs() ops. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20210901124521.30599-5-bmeng.cn@gmail.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * hw/char: cadence_uart: Move clock/reset check to uart_can_receive()Bin Meng2021-09-131-7/+10
| | | | | | | | | | | | | | | | | | | | | | Currently the clock/reset check is done in uart_receive(), but we can move the check to uart_can_receive() which is earlier. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20210901124521.30599-4-bmeng.cn@gmail.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * hw/char: cadence_uart: Disable transmit when input clock is disabledBin Meng2021-09-131-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | At present when input clock is disabled, any character transmitted to tx fifo can still show on the serial line, which is wrong. Fixes: b636db306e06 ("hw/char/cadence_uart: add clock support") Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Message-id: 20210901124521.30599-3-bmeng.cn@gmail.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * hw/misc: zynq_slcr: Correctly compute output clocks in the reset exit phaseBin Meng2021-09-131-13/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | As of today, when booting upstream U-Boot for Xilinx Zynq, the UART does not receive anything. Debugging shows that the UART input clock frequency is zero which prevents the UART from receiving anything as per the logic in uart_receive(). From zynq_slcr_reset_exit() comment, it intends to compute output clocks according to ps_clk and registers. zynq_slcr_compute_clocks() is called to accomplish the task, inside which device_is_in_reset() is called to actually make the attempt in vain. Rework reset_hold() and reset_exit() so that in the reset exit phase, the logic can really compute output clocks in reset_exit(). With this change, upstream U-Boot boots properly again with: $ qemu-system-arm -M xilinx-zynq-a9 -m 1G -display none -serial null -serial stdio \ -device loader,file=u-boot-dtb.bin,addr=0x4000000,cpu-num=0 Fixes: 38867cb7ec90 ("hw/misc/zynq_slcr: add clock generation for uarts") Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Message-id: 20210901124521.30599-2-bmeng.cn@gmail.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* | Merge remote-tracking branch 'remotes/bonzini-gitlab/tags/for-upstream' into ↵Peter Maydell2021-09-131-0/+1
|\ \ | |/ |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | staging * Fixes for "-cpu max" on i386 TCG (Daniel) * vVMLOAD/VMSAVE and vGIF implementation (Lara) * Reorganize i386 targets documentation in preparation for SGX (myself) * Meson cleanups (myself, Thomas) * NVMM fixes (Reinoud) * Suppress bogus -Wstringop-overflow (Richard) # gpg: Signature made Mon 13 Sep 2021 12:56:33 BST # gpg: using RSA key F13338574B662389866C7682BFFBD25F78C7AE83 # gpg: issuer "pbonzini@redhat.com" # gpg: Good signature from "Paolo Bonzini <bonzini@gnu.org>" [full] # gpg: aka "Paolo Bonzini <pbonzini@redhat.com>" [full] # Primary key fingerprint: 46F5 9FBD 57D6 12E7 BFD4 E2F7 7E15 100C CD36 69B1 # Subkey fingerprint: F133 3857 4B66 2389 866C 7682 BFFB D25F 78C7 AE83 * remotes/bonzini-gitlab/tags/for-upstream: (21 commits) docs: link to archived Fedora code of conduct Fix nvmm_ram_block_added() function arguments Only check CONFIG_NVMM when NEED_CPU_H is defined util: Suppress -Wstringop-overflow in qemu_thread_start fw_cfg: add etc/msr_feature_control meson: remove dead variable meson: do not use python.full_path() unnecessarily meson: look up cp and dtrace with find_program() meson.build: Do not look for VNC-related libraries if have_system is not set docs/system: move x86 CPU configuration to a separate document docs/system: standardize man page sections to --- with overline docs: standardize directory index to --- with overline docs: standardize book titles to === with overline target/i386: Added vVMLOAD and vVMSAVE feature target/i386: Added changed priority check for VIRQ target/i386: Added ignore TPR check in ctl_has_irq target/i386: Added VGIF V_IRQ masking capability target/i386: Moved int_ctl into CPUX86State structure target/i386: Added VGIF feature target/i386: VMRUN and VMLOAD canonicalizations ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * fw_cfg: add etc/msr_feature_controlPaolo Bonzini2021-09-131-0/+1
| | | | | | | | | | | | | | | | The file already existed, but nobody had noticed the warning until now. Add it at the bottom, since that is where unknown files go in legacy mode. Fixes: 217f1b4a721 ("target-i386: Publish advised value of MSR_IA32_FEATURE_CONTROL via fw_cfg") Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
* | Merge remote-tracking branch ↵Peter Maydell2021-09-101-81/+133
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 'remotes/kraxel/tags/input-20210910-pull-request' into staging input: ps2 fixes. # gpg: Signature made Fri 10 Sep 2021 11:22:47 BST # gpg: using RSA key A0328CFFB93A17A79901FE7D4CB6D8EED3E87138 # gpg: Good signature from "Gerd Hoffmann (work) <kraxel@redhat.com>" [full] # gpg: aka "Gerd Hoffmann <gerd@kraxel.org>" [full] # gpg: aka "Gerd Hoffmann (private) <kraxel@gmail.com>" [full] # Primary key fingerprint: A032 8CFF B93A 17A7 9901 FE7D 4CB6 D8EE D3E8 7138 * remotes/kraxel/tags/input-20210910-pull-request: ps2: migration support for command reply queue ps2: use a separate keyboard command reply queue ps2: use the whole ps2 buffer but keep queue size Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * | ps2: migration support for command reply queueVolker Rümelin2021-09-101-6/+34
| | | | | | | | | | | | | | | | | | | | | | | | Add migration support for the PS/2 keyboard command reply queue. Signed-off-by: Volker Rümelin <vr_qemu@t-online.de> Message-Id: <20210810133258.8231-3-vr_qemu@t-online.de> Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
| * | ps2: use a separate keyboard command reply queueVolker Rümelin2021-09-101-31/+84
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | A PS/2 keyboard has a separate command reply queue that is independent of the key queue. This prevents that command replies and keyboard input mix. Keyboard command replies take precedence over queued keystrokes. A new keyboard command removes any remaining command replies from the command reply queue. Implement a separate keyboard command reply queue and clear the command reply queue before command execution. This brings the PS/2 keyboard emulation much closer to a real PS/2 keyboard. The command reply queue is located in a few free bytes directly in front of the scancode queue. Because the scancode queue has a maximum length of 16 bytes there are 240 bytes available for the command reply queue. At the moment only a maximum of 3 bytes are required. For compatibility reasons rptr, wptr and count kept their function. rptr is the start, wptr is the end and count is the length of the entire keyboard queue. The new variable cwptr is the end of the command reply queue or -1 if the queue is empty. To write to the command reply queue, rptr is moved backward by the number of required bytes and the command replies are written to the buffer starting at the new rptr position. After writing, cwptr is at the old rptr position. Copying cwptr to rptr clears the command reply queue. The command reply queue can't overflow because each new keyboard command clears the command reply queue. Resolves: https://gitlab.com/qemu-project/qemu/-/issues/501 Resolves: https://gitlab.com/qemu-project/qemu/-/issues/502 Signed-off-by: Volker Rümelin <vr_qemu@t-online.de> Message-Id: <20210810133258.8231-2-vr_qemu@t-online.de> Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
| * | ps2: use the whole ps2 buffer but keep queue sizeVolker Rümelin2021-09-101-49/+20Star
| |/ | | | | | | | | | | | | | | | | | | | | Extend the used ps2 buffer size to the available buffer size but keep the maximum ps2 queue size. The next patch needs a few bytes of the larger buffer size. Signed-off-by: Volker Rümelin <vr_qemu@t-online.de> Message-Id: <20210810133258.8231-1-vr_qemu@t-online.de> Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
* | Merge remote-tracking branch 'remotes/vivier/tags/q800-pull-request' into ↵Peter Maydell2021-09-102-307/+278Star
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | staging q800 pull request 20210908 mac_via: remove MAC_VIA device and prepare for Nubus IRQs # gpg: Signature made Wed 08 Sep 2021 16:35:03 BST # gpg: using RSA key CD2F75DDC8E3A4DC2E4F5173F30C38BD3F2FBE3C # gpg: issuer "laurent@vivier.eu" # gpg: Good signature from "Laurent Vivier <lvivier@redhat.com>" [full] # gpg: aka "Laurent Vivier <laurent@vivier.eu>" [full] # gpg: aka "Laurent Vivier (Red Hat) <lvivier@redhat.com>" [full] # Primary key fingerprint: CD2F 75DD C8E3 A4DC 2E4F 5173 F30C 38BD 3F2F BE3C * remotes/vivier/tags/q800-pull-request: mac_via: add qdev gpios for nubus slot interrupts to VIA2 mac_via: rename VIA2_IRQ_SLOT_BIT to VIA2_IRQ_NUBUS_BIT mac_via: remove explicit viaN prefix from VIA IRQ gpios mac_via: remove mac_via device mac_via: move VIA1 realize logic from mac_via_realize() to mos6522_q800_via1_realize() mac_via: move VIA1 reset logic from mac_via_reset() to mos6522_q800_via1_reset() mac_via: move q800 VIA1 timer variables to q800 VIA1 VMStateDescription mac_via: move ADB variables to MOS6522Q800VIA1State mac_via: move PRAM/RTC variables to MOS6522Q800VIA1State mac_via: move PRAM contents and block backend to MOS6522Q800VIA1State mac_via: move last_b variable into q800 VIA1 VMStateDescription mac_via: introduce new VMStateDescription for q800 VIA1 and VIA2 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * | mac_via: add qdev gpios for nubus slot interrupts to VIA2Mark Cave-Ayland2021-09-081-0/+23
| | | | | | | | | | | | | | | | | | | | | | | | | | | These will soon be required to enable nubus devices to support interrupts. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Message-Id: <20210830102447.10806-13-mark.cave-ayland@ilande.co.uk> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
| * | mac_via: remove explicit viaN prefix from VIA IRQ gpiosMark Cave-Ayland2021-09-082-12/+7Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Now that q800 VIA1 and VIA2 are completely separate devices there is no need to add a specific device prefix to ensure that the IRQ lines remain separate. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210830102447.10806-11-mark.cave-ayland@ilande.co.uk> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
| * | mac_via: remove mac_via deviceMark Cave-Ayland2021-09-082-81/+31Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Remove the mac_via device and wire up both q800 VIA1 and VIA2 directly for the m68k q800 machine. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Message-Id: <20210830102447.10806-10-mark.cave-ayland@ilande.co.uk> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
generated by cgit v1.2.3-55-g7522 (git 2.39.0) at 2025-01-29 21:07:31 +0100