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* hw/timer/stellaris-gptm: Use Clock input instead of system_clock_scalePeter Maydell2021-09-012-7/+31
| | | | | | | | | | | | | | | | | The stellaris-gptm timer currently uses system_clock_scale for one of its timer modes where the timer runs at the CPU clock rate. Make it use a Clock input instead. We don't try to make the timer handle changes in the clock frequency while the downcounter is running. This is not a change in behaviour from the previous system_clock_scale implementation -- we will pick up the new frequency only when the downcounter hits zero. Handling dynamic clock changes when the counter is running would require state that the current gptm implementation doesn't have. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Damien Hedde <damien.hedde@greensocs.com> Message-id: 20210812093356.1946-25-peter.maydell@linaro.org
* hw/arm/stellaris: Split stellaris-gptm into its own filePeter Maydell2021-09-015-320/+320
| | | | | | | | | | | | | The implementation of the Stellaris general purpose timer module device stellaris-gptm is currently in the same source file as the board model. Split it out into its own source file in hw/timer. Apart from the new file comment headers and the Kconfig and meson.build changes, this is just code movement. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Damien Hedde <damien.hedde@greensocs.com> Message-id: 20210812093356.1946-24-peter.maydell@linaro.org
* hw/arm/stellaris: Fix code style issues in GPTM codePeter Maydell2021-09-011-5/+8
| | | | | | | | | | Fix the code style issues in the Stellaris general purpose timer module code, so that when we move it to a different file in a following patch checkpatch doesn't complain. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Alexandre Iooss <erdnaxe@crans.org> Message-id: 20210812093356.1946-23-peter.maydell@linaro.org
* hw/timer/armv7m_systick: Use clock inputs instead of system_clock_scalePeter Maydell2021-09-011-28/+84
| | | | | | | | | | | | | | Now that all users of the systick devices wire up the clock inputs, use those instead of the system_clock_scale and the hardwired 1MHz value for the reference clock. This will fix various board models where we were incorrectly providing a 1MHz reference clock instead of some other value or instead of providing no reference clock at all. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Damien Hedde <damien.hedde@greensocs.com> Message-id: 20210812093356.1946-22-peter.maydell@linaro.org
* hw/arm/msf2-soc: Wire up refclkPeter Maydell2021-09-011-0/+23
| | | | | | | | | | | | Wire up the refclk for the msf2 SoC. This SoC runs the refclk at a frequency which is programmably either /4, /8, /16 or /32 of the main CPU clock. We don't currently model the register which allows the guest to set the divisor, so implement the refclk as a fixed /32 of the CPU clock (which is the value of the divisor at reset). Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Damien Hedde <damien.hedde@greensocs.com> Message-id: 20210812093356.1946-21-peter.maydell@linaro.org
* hw/arm/msf2: Use Clock input to MSF2_SOC instead of m3clk propertyPeter Maydell2021-09-012-12/+23
| | | | | | | | | | Instead of passing the MSF2 SoC an integer property specifying the CPU clock rate, pass it a Clock instead. This lets us wire that clock up to the armv7m object. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Alexandre Iooss <erdnaxe@crans.org> Message-id: 20210812093356.1946-20-peter.maydell@linaro.org
* hw/arm/msf2_soc: Don't allocate separate MemoryRegionsPeter Maydell2021-09-011-10/+7Star
| | | | | | | | | | | In the realize method of the msf2-soc SoC object, we call g_new() to create new MemoryRegion objects for the nvm, nvm_alias, and sram. This is unnecessary; make these MemoryRegions member fields of the device state struct instead. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Alexandre Iooss <erdnaxe@crans.org> Message-id: 20210812093356.1946-19-peter.maydell@linaro.org
* hw/arm/stellaris: Wire sysclk up to armv7mPeter Maydell2021-09-011-1/+4
| | | | | | | | | | Connect the sysclk to the armv7m object. This board's SoC does not connect up the systick reference clock, so we don't need to connect a refclk. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Alexandre Iooss <erdnaxe@crans.org> Message-id: 20210812093356.1946-18-peter.maydell@linaro.org
* hw/arm/stellaris: split stellaris_sys_init()Peter Maydell2021-09-011-31/+25Star
| | | | | | | | | | | | | | | | | | | Currently the stellaris_sys_init() function creates the TYPE_STELLARIS_SYS object, sets its properties, realizes it, maps its MMIO region and connects its IRQ. In order to support wiring the sysclk up to the armv7m object, we need to split this function apart, because to connect the clock output of the STELLARIS_SYS object to the armv7m object we need to create the STELLARIS_SYS object before the armv7m object, but we can't wire up the IRQ until after we've created the armv7m object. Remove the stellaris_sys_init() function, and instead put the create/configure/realize parts before we create the armv7m object and the mmio/irq connection parts afterwards. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Alexandre Iooss <erdnaxe@crans.org> Message-id: 20210812093356.1946-17-peter.maydell@linaro.org
* hw/arm/nrf51: Wire up sysclkPeter Maydell2021-09-011-0/+20
| | | | | | | | | | | | | Wire up the sysclk input to the armv7m object. Strictly this SoC should not have a systick device at all, but our armv7m container object doesn't currently support disabling the systick device. For the moment, add a TODO comment, but note that this is why we aren't wiring up a refclk (no need for one). Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Alexandre Iooss <erdnaxe@crans.org> Message-id: 20210812093356.1946-16-peter.maydell@linaro.org
* hw/arm/stm32vldiscovery: Delete trailing blank linePeter Maydell2021-09-011-1/+0Star
| | | | | | | | | | Delete the trailing blank line at the end of the source file. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Alexandre Iooss <erdnaxe@crans.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Luc Michel <luc@lmichel.fr> Message-id: 20210812093356.1946-15-peter.maydell@linaro.org
* hw/arm/stm32f405: Wire up sysclk and refclkPeter Maydell2021-09-012-5/+37
| | | | | | | | | | | | | | | | | | | | | Wire up the sysclk and refclk for the stm32f405 SoC. This SoC always runs the systick refclk at 1/8 the frequency of the main CPU clock, so the board code only needs to provide a single sysclk clock. Because there is only one board using this SoC, we convert the SoC and the board together, rather than splitting it into "add clock to SoC; connect clock in board; add error check in SoC code that clock is wired up". When the systick device starts honouring its clock inputs, this will fix an emulation inaccuracy in the netduinoplus2 board where the systick reference clock was running at 1MHz rather than 21MHz. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Alexandre Iooss <erdnaxe@crans.org> Reviewed-by: Luc Michel <luc@lmichel.fr> Message-id: 20210812093356.1946-14-peter.maydell@linaro.org
* hw/arm/stm32f205: Wire up sysclk and refclkPeter Maydell2021-09-012-5/+37
| | | | | | | | | | | | | | | | | | | | | Wire up the sysclk and refclk for the stm32f205 SoC. This SoC always runs the systick refclk at 1/8 the frequency of the main CPU clock, so the board code only needs to provide a single sysclk clock. Because there is only one board using this SoC, we convert the SoC and the board together, rather than splitting it into "add clock to SoC; connect clock in board; add error check in SoC code that clock is wired up". When the systick device starts honouring its clock inputs, this will fix an emulation inaccuracy in the netduino2 board where the systick reference clock was running at 1MHz rather than 15MHz. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Alexandre Iooss <erdnaxe@crans.org> Reviewed-by: Luc Michel <luc@lmichel.fr> Message-id: 20210812093356.1946-13-peter.maydell@linaro.org
* hw/arm/stm32f100: Wire up sysclk and refclkPeter Maydell2021-09-012-5/+37
| | | | | | | | | | | | | | | | | | | | | Wire up the sysclk and refclk for the stm32f100 SoC. This SoC always runs the systick refclk at 1/8 the frequency of the main CPU clock, so the board code only needs to provide a single sysclk clock. Because there is only one board using this SoC, we convert the SoC and the board together, rather than splitting it into "add clock to SoC; connect clock in board; add error check in SoC code that clock is wired up". When the systick device starts honouring its clock inputs, this will fix an emulation inaccuracy in the stm32vldiscovery board where the systick reference clock was running at 1MHz rather than 3MHz. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Alexandre Iooss <erdnaxe@crans.org> Reviewed-by: Luc Michel <luc@lmichel.fr> Message-id: 20210812093356.1946-12-peter.maydell@linaro.org
* hw/arm: Don't allocate separate MemoryRegions in stm32 SoC realizePeter Maydell2021-09-012-20/+14Star
| | | | | | | | | | | | | | | In the realize methods of the stm32f100 and stm32f205 SoC objects, we call g_new() to create new MemoryRegion objects for the sram, flash, and flash_alias. This is unnecessary (and leaves open the possibility of leaking the allocations if we exit from realize with an error). Make these MemoryRegions member fields of the device state struct instead, as stm32f405 already does. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Alexandre Iooss <erdnaxe@crans.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Luc Michel <luc@lmichel.fr> Message-id: 20210812093356.1946-11-peter.maydell@linaro.org
* clock: Provide builtin multiplier/dividerPeter Maydell2021-09-013-5/+67
| | | | | | | | | | | | | | | | | | | | | | | | | | It is quite common for a clock tree to involve possibly programmable clock multipliers or dividers, where the frequency of a clock is for instance divided by 8 to produce a slower clock to feed to a particular device. Currently we provide no convenient mechanism for modelling this. You can implement it by having an input Clock and an output Clock, and manually setting the period of the output clock in the period-changed callback of the input clock, but that's quite clunky. This patch adds support in the Clock objects themselves for setting a multiplier or divider. The effect of setting this on a clock is that when the clock's period is changed, all the children of the clock are set to period * multiplier / divider, rather than being set to the same period as the parent clock. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Alexandre Iooss <erdnaxe@crans.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Luc Michel <luc@lmichel.fr> Reviewed-by: Damien Hedde <damien.hedde@greensocs.com> Message-id: 20210812093356.1946-10-peter.maydell@linaro.org
* hw/arm/mps2.c: Connect up armv7m clocksPeter Maydell2021-09-011-0/+15
| | | | | | | | | | | | | | | Connect up the armv7m clocks on the mps2-an385/386/500/511. Connect up the armv7m object's clocks on the MPS boards defined in mps2.c. The documentation for these FPGA images doesn't specify what systick reference clock is used (if any), so for the moment we provide a 1MHz refclock, which will result in no behavioural change from the current hardwired 1MHz clock implemented in armv7m_systick.c:systick_scale(). Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Luc Michel <luc@lmichel.fr> Message-id: 20210812093356.1946-9-peter.maydell@linaro.org
* armsse: Wire up systick cpuclk clockPeter Maydell2021-09-011-0/+3
| | | | | | | | | | | | | | | | | Wire up the cpuclk for the systick devices to the SSE object's existing mainclk clock. We do not wire up the refclk because the SSE subsystems do not provide a refclk. (This is documented in the IoTKit and SSE-200 TRMs; the SSE-300 TRM doesn't mention it but we assume it follows the same approach.) When we update the systick device later to honour "no refclk connected" this will fix a minor emulation inaccuracy for the SSE-based boards. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Acked-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Luc Michel <luc@lmichel.fr> Message-id: 20210812093356.1946-8-peter.maydell@linaro.org
* hw/arm/armv7m: Create input clocksPeter Maydell2021-09-011-0/+23
| | | | | | | | | | | Create input clocks on the armv7m container object which pass through to the systick timers, so that users of the armv7m object can specify the clocks being used. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Luc Michel <luc@lmichel.fr> Message-id: 20210812093356.1946-7-peter.maydell@linaro.org
* hw/timer/armv7m_systick: Add input clocksPeter Maydell2021-09-011-2/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The v7M systick timer can be programmed to run from either of two clocks: * an "external reference clock" (when SYST_CSR.CLKSOURCE == 0) * the main CPU clock (when SYST_CSR.CLKSOURCE == 1) Our implementation currently hardwires the external reference clock to be 1MHz, and allows boards to set the main CPU clock frequency via the global 'system_clock_scale'. (Most boards set that to a constant value; the Stellaris boards allow the guest to reprogram it via the board-specific RCC registers). As the first step in converting this to use the Clock infrastructure, add input clocks to the systick device for the reference clock and the CPU clock. The device implementation ignores them; once we have made all the users of the device correctly wire up the new Clocks we will switch the implementation to use them and ignore the old system_clock_scale. This is a migration compat break for all M-profile boards, because of the addition of the new clock objects to the vmstate struct. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Luc Michel <luc@lmichel.fr> Message-id: 20210812093356.1946-6-peter.maydell@linaro.org
* arm: Move system PPB container handling to armv7mPeter Maydell2021-09-012-142/+103Star
| | | | | | | | | | | | | | | | Instead of having the NVIC device provide a single sysbus memory region covering the whole of the "System PPB" space, which implements the default behaviour for unimplemented ranges and provides the NS alias window to the sysregs as well as the main sysreg MR, move this handling to the container armv7m device. The NVIC now provides a single memory region which just implements the system registers. This consolidates all the handling of "map various devices in the PPB" into the armv7m container where it belongs. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Alexandre Iooss <erdnaxe@crans.org> Reviewed-by: Luc Michel <luc@lmichel.fr> Message-id: 20210812093356.1946-4-peter.maydell@linaro.org
* arm: Move systick device creation from NVIC to ARMv7M objectPeter Maydell2021-09-012-73/+125
| | | | | | | | | | | | | | | | | | There's no particular reason why the NVIC should be owning the SysTick device objects; move them into the ARMv7M container object instead, as part of consolidating the "create the devices which are built into an M-profile CPU and map them into their architected locations in the address space" work into one place. This involves temporarily creating a duplicate copy of the nvic_sysreg_ns_ops struct and its read/write functions (renamed as v7m_sysreg_ns_*), but we will delete the NVIC's copy of this code in a subsequent patch. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Acked-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Luc Michel <luc@lmichel.fr> Message-id: 20210812093356.1946-3-peter.maydell@linaro.org
* arm: Move M-profile RAS register block into its own devicePeter Maydell2021-09-014-56/+107
| | | | | | | | | | | | | | | Currently we implement the RAS register block within the NVIC device. It isn't really very tightly coupled with the NVIC proper, so instead move it out into a sysbus device of its own and have the top level ARMv7M container create it and map it into memory at the right address. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Alexandre Iooss <erdnaxe@crans.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Luc Michel <luc@lmichel.fr> Reviewed-by: Damien Hedde <damien.hedde@greensocs.com> Message-id: 20210812093356.1946-2-peter.maydell@linaro.org
* hw/arm/virt: target-arm: Add A64FX processor support to virt machineShuuichirou Ishii2021-09-011-0/+1
| | | | | | | | | | Add -cpu a64fx to use A64FX processor when -machine virt option is specified. In addition, add a64fx to the Supported guest CPU types in the virt.rst document. Signed-off-by: Shuuichirou Ishii <ishii.shuuichir@fujitsu.com> Reviewed-by: Andrew Jones <drjones@redhat.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* hw: Add compat machines for 6.2Yanan Wang2021-09-017-6/+65
| | | | | | | | | | | Add 6.2 machine types for arm/i440fx/q35/s390x/spapr. Signed-off-by: Yanan Wang <wangyanan55@huawei.com> Acked-by: David Gibson <david@gibson.dropbear.id.au> Reviewed-by: Andrew Jones <drjones@redhat.com> Reviewed-by: Cornelia Huck <cohuck@redhat.com> Reviewed-by: Pankaj Gupta <pankaj.gupta@ionos.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* hw/intc/arm_gicv3: Replace mis-used MEMTX_* constants by booleansPhilippe Mathieu-Daudé2021-09-011-95/+106
| | | | | | | | | | | | | | | | | | | | Quoting Peter Maydell: These MEMTX_* aren't from the memory transaction API functions; they're just being used by gicd_readl() and friends as a way to indicate a success/failure so that the actual MemoryRegionOps read/write fns like gicv3_dist_read() can log a guest error. Arguably this is a bit of a misuse of the MEMTX_* constants and perhaps we should have gicd_readl etc return a bool instead. Follow his suggestion and replace the MEMTX_* constants by boolean values, simplifying a bit the gicv3_dist_read() / gicv3_dist_write() handlers. Suggested-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-id: 20210826180704.2131949-3-philmd@redhat.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* hw/intc/arm_gicv3_dist: Rename 64-bit accessors with 'q' suffixPhilippe Mathieu-Daudé2021-09-011-6/+6
| | | | | | | | | | QEMU load/store API (docs/devel/loads-stores.rst) uses the 'q' suffix for 64-bit accesses. Rename the current 'll' suffix to have the GIC dist accessors better match the rest of the codebase. Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-id: 20210826180704.2131949-2-philmd@redhat.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* hw/arm/raspi: Remove deprecated raspi2/raspi3 aliasesPhilippe Mathieu-Daudé2021-09-011-2/+0Star
| | | | | | | | | | Remove the raspi2/raspi3 machine aliases, deprecated since commit 155e1c82ed0. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-id: 20210827060815.2384760-3-f4bug@amsat.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* hw/core/register: Add more 64-bit utilitiesJoe Komlodi2021-09-011-0/+12
| | | | | | | | | | | | We already have some utilities to handle 64-bit wide registers, so this just adds some more for: - Initializing 64-bit registers - Extracting and depositing to an array of 64-bit registers Signed-off-by: Joe Komlodi <joe.komlodi@xilinx.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 1626805903-162860-2-git-send-email-joe.komlodi@xilinx.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
* hw/intc/sifive_clint: Fix muldiv64 overflow in sifive_clint_write_timecmp()David Hoppenbrouwers2021-09-011-2/+23
| | | | | | | | | | | | | | | | | | | | | | | | `muldiv64` would overflow in cases where the final 96-bit value does not fit in a `uint64_t`. This would result in small values that cause an interrupt to be triggered much sooner than intended. The overflow can be detected in most cases by checking if the new value is smaller than the previous value. If the final result is larger than `diff` it is either correct or it doesn't matter as it is effectively infinite anyways. `next` is an `uint64_t` value, but `timer_mod` takes an `int64_t`. This resulted in high values such as `UINT64_MAX` being converted to `-1`, which caused an immediate timer interrupt. By limiting `next` to `INT64_MAX` no overflow will happen while the timer will still be effectively set to "infinitely" far in the future. Resolves: https://gitlab.com/qemu-project/qemu/-/issues/493 Signed-off-by: David Hoppenbrouwers <david@salt-inc.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20210827152324.5201-1-david@salt-inc.org Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
* hw/riscv/virt.c: Assemble plic_hart_config string with g_strjoinv()Peter Maydell2021-09-011-13/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | In the riscv virt machine init function, We assemble a string plic_hart_config which is a comma-separated list of N copies of the VIRT_PLIC_HART_CONFIG string. The code that does this has a misunderstanding of the strncat() length argument. If the source string is too large strncat() will write a maximum of length+1 bytes (length bytes from the source string plus a trailing NUL), but the code here assumes that it will write only length bytes at most. This isn't an actual bug because the code has correctly precalculated the amount of memory it needs to allocate so that it will never be too small (i.e. we could have used plain old strcat()), but it does mean that the code looks like it has a guard against accidental overrun when it doesn't. Rewrite the string handling here to use the glib g_strjoinv() function, which means we don't need to do careful accountancy of string lengths, and makes it clearer that what we're doing is "create a comma-separated string". Fixes: Coverity 1460752 Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20210812144647.10516-1-peter.maydell@linaro.org Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
* hw/riscv: virt: Move flash node to rootBin Meng2021-09-011-1/+1
| | | | | | | | | | | The flash is not inside the SoC, so it's inappropriate to put it under the /soc node. Move it to root instead. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20210807035641.22449-1-bmeng.cn@gmail.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
* hw/char: Add config for shakti uartVijai Kumar K2021-09-013-5/+5
| | | | | | | | | | Use a dedicated UART config(CONFIG_SHAKTI_UART) to select shakti uart. Signed-off-by: Vijai Kumar K <vijai@behindbytes.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20210731190229.137483-1-vijai@behindbytes.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
* Merge remote-tracking branch 'remotes/dg-gitlab/tags/ppc-for-6.2-20210827' ↵Peter Maydell2021-08-277-44/+60
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | into staging ppc patch queue 2021-08-27 First ppc pull request for qemu-6.2. As usual, there's a fair bit here, since it's been queued during the 6.1 freeze. Highlights are: * Some fixes for 128 bit arithmetic and some vector opcodes that use them * Significant improvements to the powernv to support POWER10 cpus (more to come though) * Several cleanups to the ppc softmmu code * A few other assorted fixes # gpg: Signature made Fri 27 Aug 2021 08:09:12 BST # gpg: using RSA key 75F46586AE61A66CC44E87DC6C38CACA20D9B392 # gpg: Good signature from "David Gibson <david@gibson.dropbear.id.au>" [full] # gpg: aka "David Gibson (Red Hat) <dgibson@redhat.com>" [full] # gpg: aka "David Gibson (ozlabs.org) <dgibson@ozlabs.org>" [full] # gpg: aka "David Gibson (kernel.org) <dwg@kernel.org>" [unknown] # Primary key fingerprint: 75F4 6586 AE61 A66C C44E 87DC 6C38 CACA 20D9 B392 * remotes/dg-gitlab/tags/ppc-for-6.2-20210827: target/ppc: fix vector registers access in gdbstub for little-endian include/qemu/int128.h: introduce bswap128s target/ppc: fix vextu[bhw][lr]x helpers include/qemu/int128.h: define struct Int128 according to the host endianness ppc/xive: Export xive_presenter_notify() ppc/xive: Export PQ get/set routines ppc/pnv: add a chip topology index for POWER10 ppc/pnv: Distribute RAM among the chips ppc/pnv: Use a simple incrementing index for the chip-id ppc/pnv: powerpc_excp: Do not discard HDECR exception when entering power-saving mode ppc/pnv: Change the POWER10 machine to support DD2 only ppc: Add a POWER10 DD2 CPU ppc/pnv: update skiboot to commit 820d43c0a775. target/ppc: moved store_40x_sler to helper_regs.c target/ppc: moved ppc_store_sdr1 to mmu_common.c target/ppc: divided mmu_helper.c in 2 files spapr_pci: Fix leak in spapr_phb_vfio_get_loc_code() with g_autofree xive: Remove extra '0x' prefix in trace events Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * ppc/xive: Export xive_presenter_notify()Cédric Le Goater2021-08-271-4/+4
| | | | | | | | | | | | | | | | | | | | It's generic enough to be used from the XIVE2 router and avoid more duplication. Reviewed-by: Greg Kurz <groug@kaod.org> Signed-off-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20210809134547.689560-9-clg@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
| * ppc/xive: Export PQ get/set routinesCédric Le Goater2021-08-272-7/+7
| | | | | | | | | | | | | | | | | | These will be shared with the XIVE2 router. Reviewed-by: Greg Kurz <groug@kaod.org> Signed-off-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20210809134547.689560-8-clg@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
| * ppc/pnv: add a chip topology index for POWER10Cédric Le Goater2021-08-271-0/+2
| | | | | | | | | | | | Signed-off-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20210809134547.689560-7-clg@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
| * ppc/pnv: Distribute RAM among the chipsCédric Le Goater2021-08-271-8/+25
| | | | | | | | | | | | | | | | | | But always give the first 1GB to chip 0 as skiboot requires it. Signed-off-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20210809134547.689560-6-clg@kaod.org> Reviewed-by: Greg Kurz <groug@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
| * ppc/pnv: Use a simple incrementing index for the chip-idCédric Le Goater2021-08-271-5/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When the QEMU PowerNV machine was introduced, multi chip support modeled a two socket system with dual chip modules as found on some P8 Tuleta systems (8286-42A). But this is hardly used and not relevant for QEMU. Use a simple index instead. With this change, we can now increase the max socket number to 16 as found on high end systems. Signed-off-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20210809134547.689560-5-clg@kaod.org> Reviewed-by: Greg Kurz <groug@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
| * ppc/pnv: Change the POWER10 machine to support DD2 onlyCédric Le Goater2021-08-272-2/+2
| | | | | | | | | | | | | | | | | | | | There is no need to keep the DD1 chip model as it will never be publicly available. Signed-off-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20210809134547.689560-3-clg@kaod.org> Reviewed-by: Greg Kurz <groug@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
| * spapr_pci: Fix leak in spapr_phb_vfio_get_loc_code() with g_autofreeDavid Gibson2021-08-271-13/+9Star
| | | | | | | | | | | | | | | | | | | | | | This uses g_autofree to simplify logic in spapr_phb_vfio_get_loc_code(), in the process fixing a leak in one of the paths. I'm told this fixes Coverity error CID 1460454 Reported-by: Peter Maydell <peter.maydell@linaro.org> Fixes: 16b0ea1d852 ("spapr_pci: populate ibm,loc-code") Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
| * xive: Remove extra '0x' prefix in trace eventsCédric Le Goater2021-08-271-5/+5
| | | | | | | | | | | | | | | | | | | | | | Cc: thuth@redhat.com Fixes: 4e960974d4ee ("xive: Add trace events") Resolves: https://gitlab.com/qemu-project/qemu/-/issues/519 Signed-off-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20210809085227.288523-1-clg@kaod.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
* | Merge remote-tracking branch 'remotes/armbru/tags/pull-error-2021-08-26' ↵Peter Maydell2021-08-279-43/+35Star
|\ \ | |/ |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | into staging Error reporting patches for 2021-08-26 # gpg: Signature made Thu 26 Aug 2021 16:17:05 BST # gpg: using RSA key 354BC8B3D7EB2A6B68674E5F3870B400EB918653 # gpg: issuer "armbru@redhat.com" # gpg: Good signature from "Markus Armbruster <armbru@redhat.com>" [full] # gpg: aka "Markus Armbruster <armbru@pond.sub.org>" [full] # Primary key fingerprint: 354B C8B3 D7EB 2A6B 6867 4E5F 3870 B400 EB91 8653 * remotes/armbru/tags/pull-error-2021-08-26: vl: Clean up -smp error handling Remove superfluous ERRP_GUARD() vhost: Clean up how VhostOpts method vhost_backend_init() fails vhost: Clean up how VhostOpts method vhost_get_config() fails microvm: Drop dead error handling in microvm_machine_state_init() migration: Handle migration_incoming_setup() errors consistently migration: Unify failure check for migrate_add_blocker() whpx nvmm: Drop useless migrate_del_blocker() vfio: Avoid error_propagate() after migrate_add_blocker() i386: Never free migration blocker objects instead of sometimes vhost-scsi: Plug memory leak on migrate_add_blocker() failure multi-process: Fix pci_proxy_dev_realize() error handling spapr: Explain purpose of ->fwnmi_migration_blocker more clearly spapr: Plug memory leak when we can't add a migration blocker error: Use error_fatal to simplify obvious fatal errors (again) Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * Remove superfluous ERRP_GUARD()Markus Armbruster2021-08-261-3/+0Star
| | | | | | | | | | | | | | | | | | | | Macro ERRP_GUARD() is only needed when we want to dereference @errp or pass it to error_prepend() or error_append_hint(). Delete superfluous ones. Signed-off-by: Markus Armbruster <armbru@redhat.com> Message-Id: <20210720125408.387910-15-armbru@redhat.com> Acked-by: Michael S. Tsirkin <mst@redhat.com>
| * vhost: Clean up how VhostOpts method vhost_backend_init() failsMarkus Armbruster2021-08-262-4/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | vhost_user_backend_init() can fail without setting an error. Unclean. Its caller vhost_dev_init() compensates by substituting a generic error then. Goes back to commit 28770ff935 "vhost: Distinguish errors in vhost_backend_init()". Clean up by moving the generic error from vhost_dev_init() to all the failure paths that neglect to set an error. Cc: Kevin Wolf <kwolf@redhat.com> Cc: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Markus Armbruster <armbru@redhat.com> Message-Id: <20210720125408.387910-14-armbru@redhat.com> Acked-by: Michael S. Tsirkin <mst@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
| * vhost: Clean up how VhostOpts method vhost_get_config() failsMarkus Armbruster2021-08-262-8/+4Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | vhost_user_get_config() can fail without setting an error. Unclean. Its caller vhost_dev_get_config() compensates by substituting a generic error then. Goes back to commit 50de51387f "vhost: Distinguish errors in vhost_dev_get_config()". Clean up by moving the generic error from vhost_dev_get_config() to all the failure paths that neglect to set an error. Cc: Kevin Wolf <kwolf@redhat.com> Cc: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Markus Armbruster <armbru@redhat.com> Message-Id: <20210720125408.387910-13-armbru@redhat.com> Acked-by: Michael S. Tsirkin <mst@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> [Sign of error_setg_errno()'s second argument fixed in both calls]
| * microvm: Drop dead error handling in microvm_machine_state_init()Markus Armbruster2021-08-261-5/+0Star
| | | | | | | | | | | | | | | | | | | | | | | | | | Stillborn in commit 0ebf007dda "hw/i386: Introduce the microvm machine type". Cc: Sergio Lopez <slp@redhat.com> Signed-off-by: Markus Armbruster <armbru@redhat.com> Message-Id: <20210720125408.387910-12-armbru@redhat.com> Reviewed-by: Sergio Lopez <slp@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Pankaj Gupta <pankaj.gupta@ionos.com> Acked-by: Michael S. Tsirkin <mst@redhat.com>
| * migration: Unify failure check for migrate_add_blocker()Markus Armbruster2021-08-261-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Most callers check the return value. Some check whether it set an error. Functionally equivalent, but the former tends to be easier on the eyes, so do that everywhere. Prior art: commit c6ecec43b2 "qemu-option: Check return value instead of @err where convenient". Signed-off-by: Markus Armbruster <armbru@redhat.com> Message-Id: <20210720125408.387910-10-armbru@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Acked-by: Michael S. Tsirkin <mst@redhat.com>
| * vfio: Avoid error_propagate() after migrate_add_blocker()Markus Armbruster2021-08-261-4/+2Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When migrate_add_blocker(blocker, &err) is followed by error_propagate(errp, err), we can often just as well do migrate_add_blocker(..., errp). This is the case in vfio_migration_probe(). Prior art: commit 386f6c07d2 "error: Avoid error_propagate() after migrate_add_blocker()". Cc: Kirti Wankhede <kwankhede@nvidia.com> Cc: Alex Williamson <alex.williamson@redhat.com> Signed-off-by: Markus Armbruster <armbru@redhat.com> Message-Id: <20210720125408.387910-8-armbru@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed by: Kirti Wankhede <kwankhede@nvidia.com> Acked-by: Michael S. Tsirkin <mst@redhat.com>
| * vhost-scsi: Plug memory leak on migrate_add_blocker() failureMarkus Armbruster2021-08-261-2/+2
| | | | | | | | | | | | | | Cc: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Markus Armbruster <armbru@redhat.com> Message-Id: <20210720125408.387910-6-armbru@redhat.com> Acked-by: Michael S. Tsirkin <mst@redhat.com>
generated by cgit v1.2.3-55-g7522 (git 2.39.0) at 2025-01-16 06:15:18 +0100