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* softmmu: move all load/store functions to cpu_ldst.hPaolo Bonzini2014-06-055-363/+368
| | | | | | | | Unify pieces of cpu-all.h, exec-all.h, softmmu_exec.h and tcg/tcg.h into a single new header file with all helpers. Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
* softmmu: introduce cpu_ldst.hPaolo Bonzini2014-06-051-0/+35
| | | | | | | | | | This will collect all load and store helpers soon. For now it is just a replacement for softmmu_exec.h, which this patch stops including directly, but we also include it where this will be necessary in order to simplify the next patch. Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
* softmmu: move softmmu_template.h out of include/Paolo Bonzini2014-06-051-533/+0Star
| | | | | | | It is only included in cputlb.c now. Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
* softmmu: commonize helper definitionsPaolo Bonzini2014-06-051-0/+2
| | | | | | | | | They do not need to be in op_helper.c. Because cputlb.c now includes softmmu_template.h twice for each size, io_readX must be elided the second time through. Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
* softmmu: make do_unaligned_access a method of CPUPaolo Bonzini2014-06-051-12/+18
| | | | | | | | | We will reference it from more files in the next patch. To avoid ruining the small steps we're making towards multi-target, make it a method of CPU rather than just a global. Reviewed-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
* softmmu: move definition of CPU_MMU_INDEX to inclusion site, drop ACCESS_TYPEPaolo Bonzini2014-06-053-27/+16Star
| | | | | Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
* softmmu: move MMUSUFFIX under SOFTMMU_CODE_ACCESSPaolo Bonzini2014-06-051-9/+2Star
| | | | | Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
* softmmu: start introducing SOFTMMU_CODE_ACCESS in softmmu_header.hPaolo Bonzini2014-06-052-5/+5
| | | | | | | | | This preprocessor symbol is already used in softmmu_template.h. We will use it to distinguish the two "fake" ACCESS_TYPEs NB_MMU_MODES and NB_MMU_MODES + 1. Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
* tcg: Move size effects out of dh_argRichard Henderson2014-05-282-50/+39Star
| | | | | | | Tidying the initialization of the args arrays at the same time. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg: Remove sizemask and flags arguments to tcg_gen_callNRichard Henderson2014-05-282-14/+7Star
| | | | | | Take them from the TCGHelperInfo struct instead. Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg: Save flags and computed sizemask in TCGHelperInfoRichard Henderson2014-05-281-16/+28
| | | | Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg: Move side effects out of dh_sizemaskRichard Henderson2014-05-282-15/+8Star
| | | | | | Moving them into dh_arg instead. Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg: Inline tcg_gen_helperNRichard Henderson2014-05-281-6/+6
| | | | | Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg: Push tcg-runtime routines into exec/helper-*Richard Henderson2014-05-284-4/+11
| | | | | | | | Rather than special casing them, use the standard mechanisms for tcg helper generation. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg: Invert the inclusion of helper.hRichard Henderson2014-05-284-143/+166
| | | | | | | | | | Rather than include helper.h with N values of GEN_HELPER, include a secondary file that sets up the macros to include helper.h. This minimizes the files that must be rebuilt when changing the macros for file N. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg-mips: Enable direct chaining of TBsRichard Henderson2014-05-241-2/+2
| | | | | | | | Now that the code_gen_buffer is constrained to not cross 256mb regions, we are assured that we can use J to reach another TB. Reviewed-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Richard Henderson <rth@twiddle.net>
* Merge remote-tracking branch 'remotes/rth/tags/pull-tcg-s390-20140515' into ↵Peter Maydell2014-05-151-0/+9
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | staging tcg/s390 updates # gpg: Signature made Thu 15 May 2014 17:24:40 BST using RSA key ID 4DD0279B # gpg: Can't check signature: public key not found * remotes/rth/tags/pull-tcg-s390-20140515: tcg-s390: Implement direct chaining of TBs tcg-s390: Don't force -march=z990 tcg-s390: Improve setcond tcg-s390: Allow immediate operands to add2 and sub2 tcg-s390: Implement tcg_register_jit tcg-s390: Use more risbg in the tlb sequence tcg-s390: Move ldst helpers out of line tcg-s390: Convert to new ldst opcodes tcg-s390: Integrate endianness into TCGMemOp tcg-s390: Convert to TCGMemOp tcg-s390: Fix off-by-one in wraparound andi Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * tcg-s390: Implement direct chaining of TBsRichard Henderson2014-05-151-0/+9
| | | | | | | | Signed-off-by: Richard Henderson <rth@twiddle.net>
* | Merge remote-tracking branch 'remotes/kvm/uq/master' into stagingPeter Maydell2014-05-151-3/+5
|\ \ | |/ |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * remotes/kvm/uq/master: pc: port 92 reset requires a low->high transition cpu: make CPU_INTERRUPT_RESET available on all targets apic: do not accept SIPI on the bootstrap processor target-i386: preserve FPU and MSR state on INIT target-i386: fix set of registers zeroed on reset kvm: forward INIT signals coming from the chipset kvm: reset state from the CPU's reset method target-i386: the x86 CPL is stored in CS.selector - auto update hflags accordingly. target-i386: set eflags prior to calling cpu_x86_load_seg_cache() in seg_helper.c target-i386: set eflags and cr0 prior to calling cpu_x86_load_seg_cache() in smm_helper.c target-i386: set eflags prior to calling svm_load_seg_cache() in svm_helper.c pci-assign: limit # of msix vectors pci-assign: Fix a bug when map MSI-X table memory failed kvm: make one_reg helpers available for everyone target-i386: Remove unused data from local array Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * cpu: make CPU_INTERRUPT_RESET available on all targetsPaolo Bonzini2014-05-131-3/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On the x86, some devices need access to the CPU reset pin (INIT#). Provide a generic service to do this, using one of the internal cpu_interrupt targets. Generalize the PPC-specific code for CPU_INTERRUPT_RESET to other targets. Since PPC does not support migration across QEMU versions (its machine types are not versioned yet), I picked the value that is used on x86, CPU_INTERRUPT_TGT_INT_1. Consequently, TGT_INT_2 and TGT_INT_3 are shifted down by one while keeping their value. Reviewed-by: Anthony Liguori <aliguori@us.ibm.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
* | exec-all.h: Use stl_le_p instead of stl_p patching x86Richard Henderson2014-05-131-1/+1
| | | | | | | | | | | | | | | | We got the wrong version of stl_p, the one that bswaps as appropriate for the target. Since x86 is always little-endian, the "_le_" routine will resolve to what we want. Signed-off-by: Richard Henderson <rth@twiddle.net>
* | tcg: Define tcg_insn_unit for code pointersRichard Henderson2014-05-121-1/+1
| | | | | | | | | | | | | | | | | | To be defined by the tcg backend based on the elemental unit of the ISA. During the transition, allow TCG_TARGET_INSN_UNIT_SIZE to be undefined, which allows us to default tcg_insn_unit to the current uint8_t. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
* | exec-all.h: Use stl_p to avoid undefined behaviour patching x86 jumpsPeter Maydell2014-05-121-1/+1
|/ | | | | | | | | | | | | | | | | | | The code which patches x86 jump instructions assumes it can do an unaligned write of a uint32_t. This is actually safe on x86, but it's still undefined behaviour. We have infrastructure for doing efficient unaligned accesses which doesn't engage in undefined behaviour, so use it. This is technically fractionally less efficient, at least with gcc 4.6; instead of one instruction: 7b2: 89 3e mov %edi,(%rsi) we get an extra spurious store to the stack slot: 7b2: 89 7c 24 64 mov %edi,0x64(%rsp) 7b6: 89 3e mov %edi,(%rsi) Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
* docs/memory.txt: Fix document on MMIO operationsFam Zheng2014-05-071-1/+1
| | | | | | | | | | | .impl.valid should be .impl.unaligned and the description needs some fixes. .old_portio is removed since commit b40acf99b (ioport: Switch dispatching to memory core layer). Signed-off-by: Fam Zheng <famz@redhat.com> Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
* tcg: Fix missed pointer size != TCG_TARGET_REG_BITS changesRichard Henderson2014-04-281-1/+1
| | | | Signed-off-by: Richard Henderson <rth@twiddle.net>
* target-arm: A64: Implement DC ZVAPeter Maydell2014-04-171-0/+52
| | | | | | | | | | | Implement the DC ZVA instruction, which clears a block of memory. The fast path obtains a pointer to the underlying RAM via the TCG TLB data structure so we can do a direct memset(), with fallback to a simple byte-store loop in the slow path. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net> Acked-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
* exec-all.h: Increase MAX_OP_PER_INSTR for ARM A64 decoderPeter Maydell2014-03-171-1/+1
| | | | | | | | | | The ARM A64 decoder's worst case number of TCG ops per instruction is 266 (for insn 0x4c800000, a post-indexed ST4 multiple-structures store). Raise the MAX_OP_PER_INSTR define accordingly. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net> Message-id: 1394822294-14837-17-git-send-email-peter.maydell@linaro.org
* cputlb: Change tlb_set_page() argument to CPUStateAndreas Färber2014-03-131-1/+1
| | | | Signed-off-by: Andreas Färber <afaerber@suse.de>
* cputlb: Change tlb_flush() argument to CPUStateAndreas Färber2014-03-131-2/+2
| | | | Signed-off-by: Andreas Färber <afaerber@suse.de>
* cputlb: Change tlb_flush_page() argument to CPUStateAndreas Färber2014-03-131-2/+2
| | | | Signed-off-by: Andreas Färber <afaerber@suse.de>
* exec: Change cpu_abort() argument to CPUStateAndreas Färber2014-03-131-3/+0Star
| | | | Signed-off-by: Andreas Färber <afaerber@suse.de>
* exec: Change memory_region_section_get_iotlb() argument to CPUStateAndreas Färber2014-03-131-1/+1
| | | | | | It no longer needs CPUArchState since moving watchpoints to CPUState. Signed-off-by: Andreas Färber <afaerber@suse.de>
* cputlb: Change tlb_unprotect_code_phys() argument to CPUStateAndreas Färber2014-03-131-1/+1
| | | | | | Note that the argument is unused. Signed-off-by: Andreas Färber <afaerber@suse.de>
* cpu-exec: Change cpu_resume_from_signal() argument to CPUStateAndreas Färber2014-03-131-1/+1
| | | | Signed-off-by: Andreas Färber <afaerber@suse.de>
* exec: Change cpu_breakpoint_{insert,remove{,_by_ref,_all}} argumentAndreas Färber2014-03-131-15/+0Star
| | | | | | Use CPUState. Allows to clean up CPUArchState in gdbstub. Signed-off-by: Andreas Färber <afaerber@suse.de>
* exec: Change cpu_watchpoint_{insert,remove{,_by_ref,_all}} argumentAndreas Färber2014-03-131-6/+0Star
| | | | | | Use CPUState. This lets us drop a few local env usages. Signed-off-by: Andreas Färber <afaerber@suse.de>
* translate-all: Change tb_flush_jmp_cache() argument to CPUStateAndreas Färber2014-03-131-1/+1
| | | | Signed-off-by: Andreas Färber <afaerber@suse.de>
* translate-all: Change tb_gen_code() argument to CPUStateAndreas Färber2014-03-131-1/+1
| | | | Signed-off-by: Andreas Färber <afaerber@suse.de>
* translate-all: Change cpu_io_recompile() argument to CPUStateAndreas Färber2014-03-132-3/+3
| | | | Signed-off-by: Andreas Färber <afaerber@suse.de>
* translate-all: Change cpu_restore_state() argument to CPUStateAndreas Färber2014-03-131-1/+1
| | | | | | This lets us drop some local variables in tlb_fill() functions. Signed-off-by: Andreas Färber <afaerber@suse.de>
* cpu-exec: Change cpu_loop_exit() argument to CPUStateAndreas Färber2014-03-131-1/+1
| | | | Signed-off-by: Andreas Färber <afaerber@suse.de>
* exec: Change tlb_fill() argument to CPUStateAndreas Färber2014-03-132-5/+5
| | | | Signed-off-by: Andreas Färber <afaerber@suse.de>
* cpu: Move breakpoints field from CPU_COMMON to CPUStateAndreas Färber2014-03-131-10/+0Star
| | | | | | | | Most targets were using offsetof(CPUFooState, breakpoints) to determine how much of CPUFooState to clear on reset. Use the next field after CPU_COMMON instead, if any, or sizeof(CPUFooState) otherwise. Signed-off-by: Andreas Färber <afaerber@suse.de>
* cpu: Move watchpoint fields from CPU_COMMON to CPUStateAndreas Färber2014-03-131-10/+0Star
| | | | Signed-off-by: Andreas Färber <afaerber@suse.de>
* cpu: Move opaque field from CPU_COMMON to CPUStateAndreas Färber2014-03-131-3/+0Star
| | | | Signed-off-by: Andreas Färber <afaerber@suse.de>
* cpu: Move exception_index field from CPU_COMMON to CPUStateAndreas Färber2014-03-131-3/+0Star
| | | | Signed-off-by: Andreas Färber <afaerber@suse.de>
* cpu: Move jmp_env field from CPU_COMMON to CPUStateAndreas Färber2014-03-131-2/+0Star
| | | | Signed-off-by: Andreas Färber <afaerber@suse.de>
* cpu: Move tb_jmp_cache field from CPU_COMMON to CPUStateAndreas Färber2014-03-131-4/+0Star
| | | | | | Clear it on reset. Signed-off-by: Andreas Färber <afaerber@suse.de>
* cpu: Move icount_decr field from CPU_COMMON to CPUStateAndreas Färber2014-03-132-22/+4Star
| | | | Signed-off-by: Andreas Färber <afaerber@suse.de>
* cpu: Move icount_extra field from CPU_COMMON to CPUStateAndreas Färber2014-03-131-1/+0Star
| | | | | | Reset it. Signed-off-by: Andreas Färber <afaerber@suse.de>
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