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* arm: include cpu-qom.h in files that require ARMCPUPaolo Bonzini2016-05-194-1/+4
| | | | | | | | This will keep things working when cpu.h will not be included indirectly almost everywhere (either directly or through qemu-common.h). Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
* i.MX: Add i.MX6 SOC implementation.Jean-Christophe DUBOIS2016-05-121-0/+450
| | | | | | | | | | | | | | | | | | | | For now we only support the following devices: * up to 4 Cortex A9 cores * A9 MPCORE (SCU, GIC, TWD) * 5 i.MX UARTs * 2 EPIT timers * 1 GPT timer * 3 I2C controllers * 7 GPIO controllers * 6 SDHC controllers * 5 SPI controllers * 1 CCM device * 1 SRC device * various ROM/RAM areas. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Jean-Christophe Dubois <jcd@tribudubois.net> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* bcm2835_dma: add emulation of Raspberry Pi DMA controllerGrégory ESTRADE2016-03-161-0/+2
| | | | | | | | | | | | | | | At present, all DMA transfers complete inline (so a looping descriptor queue will lock up the device). We also do not model pause/abort, arbitrarion/priority, or debug features. Signed-off-by: Grégory ESTRADE <gregory.estrade@gmail.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Andrew Baumann <Andrew.Baumann@microsoft.com> Message-id: 1457467526-8840-6-git-send-email-Andrew.Baumann@microsoft.com [AB: implement 2D mode, cleanup/refactoring for upstream submission] Signed-off-by: Andrew Baumann <Andrew.Baumann@microsoft.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* bcm2835_fb: add framebuffer device for Raspberry PiGrégory ESTRADE2016-03-161-0/+2
| | | | | | | | | | | | | | | The framebuffer occupies the upper portion of memory (64MiB by default), but it can only be controlled/configured via a system mailbox or property channel (to be added by a subsequent patch). Signed-off-by: Grégory ESTRADE <gregory.estrade@gmail.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Andrew Baumann <Andrew.Baumann@microsoft.com> Message-id: 1457467526-8840-4-git-send-email-Andrew.Baumann@microsoft.com [AB: added Windows (BGR) support and cleanup/refactoring for upstream submission] Signed-off-by: Andrew Baumann <Andrew.Baumann@microsoft.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* bcm2835_aux: add emulation of BCM2835 AUX (aka UART1) blockAndrew Baumann2016-03-161-0/+2
| | | | | | | | | | | | | | | | At present only the core UART functions (data path for tx/rx) are implemented, which is enough for UEFI to boot. The following features/registers are unimplemented: * Line/modem control * Scratch register * Extra control * Baudrate * SPI interfaces Signed-off-by: Andrew Baumann <Andrew.Baumann@microsoft.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1457467526-8840-3-git-send-email-Andrew.Baumann@microsoft.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* hw/arm: Add ASPEED AST2400 SoC modelAndrew Jeffery2016-03-161-0/+35
| | | | | | | | | | | | | While the ASPEED AST2400 SoC[1] has a broad range of capabilities this implementation is minimal, comprising an ARM926 processor, ASPEED VIC and timer devices, and a 8250 UART. [1] http://www.aspeedtech.com/products.php?fPath=20&rId=376 Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Message-id: 1458096317-25223-4-git-send-email-andrew@aj.id.au Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* arm: boot: Support big-endian elfsPeter Crosthwaite2016-03-041-0/+9
| | | | | | | | | | | | | | | Support ARM big-endian ELF files in system-mode emulation. When loading an elf, determine the endianness mode expected by the elf, and set the relevant CPU state accordingly. With this, big-endian modes are now fully supported via system-mode LE, so there is no need to restrict the elf loading to the TARGET endianness so the ifdeffery on TARGET_WORDS_BIGENDIAN goes away. Signed-off-by: Peter Crosthwaite <crosthwaite.peter@gmail.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> [PMM: fix typo in comments] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* hw/arm/virt: Provide a secure-only RAM if booting in Secure modePeter Maydell2016-03-041-0/+1
| | | | | | | | | If we're booting in Secure mode, provide a secure-only RAM (just 16MB) so that secure firmware has somewhere to run from that won't be accessible to the Non-secure guest. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1455288361-30117-2-git-send-email-peter.maydell@linaro.org
* arm/boot: move highbank secure board setup code to common routineAndrew Baumann2016-02-031-0/+5
| | | | | | | | | | | The new version is slightly different, to support Rasbperry Pi (in particular, Pi1's arm11 core which doesn't support v7 instructions such as MOVW). Tested-by: Peter Crosthwaite <crosthwaite.peter@gmail.com> Reviewed-by: Peter Crosthwaite <crosthwaite.peter@gmail.com> Signed-off-by: Andrew Baumann <Andrew.Baumann@microsoft.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* bcm2836: add bcm2836 SoC deviceAndrew Baumann2016-02-031-0/+35
| | | | | | | | This is the SoC for Raspberry Pi 2. Reviewed-by: Peter Crosthwaite <crosthwaite.peter@gmail.com> Signed-off-by: Andrew Baumann <Andrew.Baumann@microsoft.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* bcm2835_peripherals: add rollup device for bcm2835 peripheralsAndrew Baumann2016-02-032-0/+170
| | | | | | | | | | This device maintains all the non-CPU peripherals on bcm2835 (Pi1) which are also present on bcm2836 (Pi2). It also implements the private address spaces used for DMA and mailboxes. Reviewed-by: Peter Crosthwaite <crosthwaite.peter@gmail.com> Signed-off-by: Andrew Baumann <Andrew.Baumann@microsoft.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* arm: virt-acpi: each MADT.GICC entry as enabled unconditionallyIgor Mammedov2016-02-031-1/+0Star
| | | | | | | | | | | | | | | | | | | | in current impl. condition build_madt() { ... if (test_bit(i, cpuinfo->found_cpus)) is always true since loop handles only present CPUs in range [0..smp_cpus). But to fill usless cpuinfo->found_cpus we do unnecessary scan over QOM tree to find the same CPUs. So mark GICC as present always and drop not needed code that fills cpuinfo->found_cpus. Signed-off-by: Igor Mammedov <imammedo@redhat.com> Reviewed-by: Shannon Zhao <shannon.zhao@linaro.org> Message-id: 1454323689-248759-1-git-send-email-imammedo@redhat.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* hw/arm/virt: add secure memory region and UARTPeter Maydell2016-01-211-0/+1
| | | | | | | | | | | Add a secure memory region to the virt board, which is the same as the nonsecure memory region except that it also has a secure-only UART in it. This is only created if the board is started with the '-machine secure=on' property. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Acked-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
* xlnx-zynqmp: Connect the SPI devicesAlistair Francis2016-01-211-0/+3
| | | | | | | | | | | | | Connect the Xilinx SPI devices to the ZynqMP model. Signed-off-by: Alistair Francis <alistair.francis@xilinx.com> Reviewed-by: Peter Crosthwaite <crosthwaite.peter@gmail.com> [ PC changes * Use QOM alias for bus connectivity on SoC level ] Signed-off-by: Peter Crosthwaite <crosthwaite.peter@gmail.com> [PMM: free the g_strdup_printf() string when finished with it] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* xlnx-zynqmp: Add support for high DDR memory regionsAlistair Francis2016-01-151-0/+12
| | | | | | | | | | | | | | | | | | | | | | The Xilinx ZynqMP SoC and EP108 board supports three memory regions: - A 2GB region starting at 0 - A 32GB region starting at 32GB - A 256GB region starting at 768GB This patch adds support for the first two memory regions, which is automatically created based on the size specified by the QEMU memory command line argument. On hardware the physical memory region is one continuous region, it is then mapped into the three different regions by the DDRC. As we don't model the DDRC this is done at startup by QEMU. The board creates the memory region and then passes that memory region to the SoC. The SoC then maps the memory regions. Signed-off-by: Alistair Francis <alistair.francis@xilinx.com> Reviewed-by: Peter Crosthwaite <crosthwaite.peter@gmail.com> Message-id: a1e47db941d65733724a300fcd98b74fbeeaaf22.1452637205.git.alistair.francis@xilinx.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* i.MX: Add an i.MX25 specific CCM class/instanceJean-Christophe Dubois2015-12-171-2/+2
| | | | | | | | | With this CCM, i.MX25 timer is accurate with "real world time". Signed-off-by: Jean-Christophe Dubois <jcd@tribudubois.net> Message-id: 2c0cf90be767bfc8520661eca891ab22c61f18fe.1449528242.git.jcd@tribudubois.net Reviewed-by Peter Crosthwaite <crosthwaite.peter@gmail.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* i.MX: Split the CCM class into an abstract base class and a concrete classJean-Christophe Dubois2015-12-172-4/+4
| | | | | | | | | | | | | | | | | | The IMX_CCM class is now the base abstract class that is used by EPIT and GPT timer implementation. IMX31_CCM class is the concrete class implementing CCM for i.MX31 SOC. For now the i.MX25 continues to use the i.MX31 CCM implementation. An i.MX25 specific CCM will be introduced in a later patch. We also rework initialization to stop using deprecated sysbus device init. Signed-off-by: Jean-Christophe Dubois <jcd@tribudubois.net> Reviewed-by: Peter Crosthwaite <crosthwaite.peter@gmail.com> Message-id: fd3c7f87b50f5ebc99ec91f01413db35017f116d.1449528242.git.jcd@tribudubois.net Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* ARM: Virt: Add a GPIO controllerShannon Zhao2015-12-171-0/+1
| | | | | | | | | | | | | | ACPI 5.0 supports GPIO-signaled ACPI Events. This can be used for powerdown, hotplug evnets. Add a GPIO controller in machine virt, to support powerdown, maybe can be used for cpu hotplug. And here we use pl061. Signed-off-by: Shannon Zhao <zhaoshenglong@huawei.com> Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org> Reviewed-by: Wei Huang <wei@redhat.com> Tested-by: Wei Huang <wei@redhat.com> Message-id: 1449804086-3464-4-git-send-email-zhaoshenglong@huawei.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* arm: boot: Add secure_board_setup flagPeter Crosthwaite2015-11-101-0/+6
| | | | | | | | | | | | | Add a flag that when set, will cause the primary CPU to start in secure mode, even if the overall boot is non-secure. This is useful for when there is a board-setup blob that needs to run from secure mode, but device and secondary CPU init should still be done as-normal for a non- secure boot. Signed-off-by: Peter Crosthwaite <crosthwaite.peter@gmail.com> Message-id: d1170774d5446d715fced7739edfc61a5be931f9.1447007690.git.crosthwaite.peter@gmail.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* arm: allwinner-a10: Add SATAPeter Crosthwaite2015-11-061-0/+4
| | | | | | | | | Add the Allwinner A10 AHCI controller module to the SoC. Signed-off-by: Peter Crosthwaite <crosthwaite.peter@gmail.com> Reviewed-by: John Snow <jsnow@redhat.com> Message-id: 69d6962f2d14a218bd07e9ac4ccd1947737cc30f.1445917756.git.crosthwaite.peter@gmail.com Signed-off-by: John Snow <jsnow@redhat.com>
* armv7-m: Return DeviceState* from armv7m_init()Michael Davidsaver2015-11-031-1/+1
| | | | | | | | | | | Change armv7m_init to return the DeviceState* for the NVIC. This allows access to all GPIO blocks, not just the IRQ inputs. Move qdev_get_gpio_in() calls out of armv7m_init() into board code for stellaris and stm32f205 boards. Signed-off-by: Michael Davidsaver <mdavidsaver@gmail.com> Reviewed-by: Peter Crosthwaite <crosthwaite.peter@gmail.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* arm: boot: Add board specific setup code APIPeter Crosthwaite2015-11-031-0/+10
| | | | | | | | | | | | | | | | | | | | Add an API for boards to inject their own preboot software (or firmware) sequence. The software then returns to the bootloader via the link register. This allows boards to do their own little bits of firmware setup without needed to replace the bootloader completely (which is the requirement for existing firmware support). The blob is loaded by a callback if and only if doing a linux boot (similar to the existing write_secondary support). Rewrite the comment for the primary boot blob. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Crosthwaite <crosthwaite.peter@gmail.com> Message-id: 070295644c6ac84696d743913296e8cfefb48c15.1446182614.git.crosthwaite.peter@gmail.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* target-arm: xlnx-zynqmp: Add sdhci support.Sai Pavan Boddu2015-10-291-0/+3
| | | | | | | | Add two SYSBUS_SDHCI devices for xlnx-zynqmp Signed-off-by: Sai Pavan Boddu <saipava@xilinx.com> Reviewed-by: Peter Crosthwaite <crosthwaite.peter@gmail.com> Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
* hw/arm/virt: Add gic-version option to virt machinePavel Fedin2015-09-242-1/+4
| | | | | | | | | | | | | | | | | | | Add gic_version to VirtMachineState, set it to value of the option and pass it around where necessary. Instantiate devices and fdt nodes according to the choice. max_cpus for virt machine increased to 123 (calculated from redistributor space available in the memory map). GICv2 compatibility check happens inside arm_gic_common_realize(). ITS region is added to the memory map too, however currently it not used, just reserved. Signed-off-by: Pavel Fedin <p.fedin@samsung.com> Tested-by: Ashok kumar <ashoks@broadcom.com> [PMM: Added missing cpu_to_le* calls, thanks to Shannon Zhao] Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* i.MX: Add GPIO devices to i.MX25 SOCJean-Christophe Dubois2015-09-141-0/+15
| | | | | | | Signed-off-by: Jean-Christophe Dubois <jcd@tribudubois.net> Reviewed-by: Peter Crosthwaite <crosthwaite.peter@gmail.com> Message-id: 2eb129ba8713aedfe877eaa3d8de80061d880fbb.1441828793.git.jcd@tribudubois.net Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* i.MX: Add GPIO devices to i.MX31 SOCJean-Christophe Dubois2015-09-141-0/+12
| | | | | | | Signed-off-by: Jean-Christophe Dubois <jcd@tribudubois.net> Reviewed-by: Peter Crosthwaite <crosthwaite.peter@gmail.com> Message-id: 60b67c9a8b948159f4b4163ead86fbf701c011c6.1441828793.git.jcd@tribudubois.net Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* arm: xlnx-zynqmp: Fix up GIC region sizeNathan Rossi2015-09-141-1/+1
| | | | | | | | | | | | The GIC in ZynqMP cover a 64K address space, however the actual registers are decoded within a 4K address space and mirrored at the 4K boundaries. This change fixes the defined size for these regions as it was set to 0x4000/16K incorrectly. Signed-off-by: Nathan Rossi <nathan@nathanrossi.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Message-id: 1441719672-25296-1-git-send-email-nathan@nathanrossi.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* xlnx-zynqmp: Connect the sysbus AHCI to ZynqMPAlistair Francis2015-09-081-0/+3
| | | | | | | | | Connect the Sysbus AHCI device to ZynqMP. Signed-off-by: Alistair Francis <alistair.francis@xilinx.com> Reviewed-by: Sai Pavan Boddu <saipava@xilinx.com> [PMM: removed unnecessary brackets in error_propagate call] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* hw/arm: new interface for devices which need to behave differently for ↵Peter Maydell2015-09-081-0/+43
| | | | | | | | | | | | | | | | | | | | | | | | kernel boot For ARM we have a little minimalist bootloader in hw/arm/boot.c which takes the place of firmware if we're directly booting a Linux kernel. Unfortunately a few devices need special case handling in this situation to do the initialization which on real hardware would be done by firmware. (In particular if we're booting a kernel in NonSecure state then we need to make a TZ-aware GIC put all its interrupts into Group 1, or the guest will be unable to use them.) Create a new QOM interface which can be implemented by devices which need to do something different from their default reset behaviour. The callback will be called after machine initialization and before first reset. Suggested-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Tested-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Message-id: 1441383782-24378-3-git-send-email-peter.maydell@linaro.org
* i.MX: Add i2C devices to i.MX31 SOCJean-Christophe Dubois2015-09-071-0/+11
| | | | | | | Signed-off-by: Jean-Christophe Dubois <jcd@tribudubois.net> Reviewed-by: Peter Crosthwaite <crosthwaite.peter@gmail.com> Message-id: fb20e6bf5cf946c4530b2cfb55c7e37f5a0fc051.1441057361.git.jcd@tribudubois.net Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* i.MX: Add qtest support for I2C device emulator.Jean-Christophe Dubois2015-09-071-0/+1
| | | | | | | | | | This is using a ds1338 RTC chip on the I2C bus. This RTC chip is not present on the real 3DS PDK board. Signed-off-by: Jean-Christophe Dubois <jcd@tribudubois.net> Acked-by: Peter Crosthwaite <crosthwaite.peter@gmail.com> Message-id: 05601683a2a95c881cbc9f22651a044d969bd0ae.1441057361.git.jcd@tribudubois.net Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* i.MX: Add SOC support for i.MX25Jean-Christophe Dubois2015-09-071-0/+234
| | | | | | | | | | | | | | | | | For now we support the following devices: * CPU: ARM926 * Interrupt Controller: AVIC * CCM * UART x 5 * EPIT x 2 * GPT x 4 * FEC * I2C x 3 Signed-off-by: Jean-Christophe Dubois <jcd@tribudubois.net> Reviewed-by: Peter Crosthwaite <crosthwaite.peter@gmail.com> Message-id: 62218bfa90f9101f79098e768c3d58bd92dcb7f3.1441057361.git.jcd@tribudubois.net Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* i.MX: KZM: use standalone i.MX31 SOC supportJean-Christophe Dubois2015-09-071-26/+0Star
| | | | | | | | | | | | | | | | | | Convert the KZM board to use the i.MX31 SoC defintition instead of redefining the entire SoC on the machine level. Major rewrite of the machine init code. While touching the memory map comment de-indent to the correct level of indentation. This obsoletes the legacy i.MX device device creation helpers which are removed. Tested by booting a minimal Linux system on the emulated platform Signed-off-by: Jean-Christophe Dubois <jcd@tribudubois.net> Reviewed-by: Peter Crosthwaite <crosthwaite.peter@gmail.com> Message-id: 5e783561f092e1c939562fdff001f1ab1194b07f.1441057361.git.jcd@tribudubois.net Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* i.MX: Add SOC support for i.MX31Jean-Christophe Dubois2015-09-071-0/+98
| | | | | | | | | | | | | | | For now we support the following devices: * CPU: ARM1136 * Interrupt Controller: AVIC * CCM * UART x 2 * EPIT x 2 * GPT Signed-off-by: Jean-Christophe Dubois <jcd@tribudubois.net> Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Message-id: f146d819594e41568daec42a1d0f440cdfe3df76.1441057361.git.jcd@tribudubois.net Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* hw/arm/virt: Add high MMIO PCI region, 512G in sizePavel Fedin2015-09-072-0/+2
| | | | | | | | | | | | | | | | | This large region is necessary for some devices like ivshmem and video cards 32-bit kernels can be built without LPAE support. In this case such a kernel will not be able to use PCI controller which has windows in high addresses. In order to work around the problem, "highmem" option is introduced. It defaults to on on, but can be manually set to off in order to be able to run those old 32-bit guests. Signed-off-by: Pavel Fedin <p.fedin@samsung.com> Reviewed-by: Alexander Graf <agraf@suse.de> Reviewed-by: Igor Mammedov <imammedo@redhat.com> Reviewed-by: Shannon Zhao <shannon.zhao@linaro.org> [PMM: Added missing ULL suffixes and a comment to the a15memmap[] entry] Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* xlnx-zynqmp: Connect the four OCM banksAlistair Francis2015-08-251-0/+6
| | | | | | | | | | | The Xilinx EP108 has four separate OCM banks which are located adjacent to each other. This patch adds the four banks to the ZynqMP SoC. Signed-off-by: Alistair Francis <alistair.francis@xilinx.com> Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Message-id: afa6ba31163a5d541a0bef4b0dc11f2597e0c495.1436813543.git.alistair.francis@xilinx.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* i.MX: Split CCM emulator in a header file and a source fileJean-Christophe Dubois2015-08-131-10/+2Star
| | | | | | | Signed-off-by: Jean-Christophe Dubois <jcd@tribudubois.net> Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Message-id: b1d6f990229b2608bbaba24f4ff359571c0b07da.1437080501.git.jcd@tribudubois.net Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* Stop including qemu-common.h in memory.hPeter Maydell2015-07-061-0/+1
| | | | | | | | | | | | | | | | | | | | Including qemu-common.h from other header files is generally a bad idea, because it means it's very easy to end up with a circular dependency. For instance, if we wanted to include memory.h from qom/cpu.h we'd end up with this loop: memory.h -> qemu-common.h -> cpu.h -> cpu-qom.h -> qom/cpu.h -> memory.h Remove the include from memory.h. This requires us to fix up a few other files which were inadvertently getting declarations indirectly through memory.h. The biggest change is splitting the fprintf_function typedef out into its own header so other headers can get at it without having to include qemu-common.h. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-Id: <1435933104-15216-1-git-send-email-peter.maydell@linaro.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
* arm: xlnx-zynqmp: Add 2xCortexR5 CPUsPeter Crosthwaite2015-06-191-0/+2
| | | | | | | | | | Add the 2xCortexR5 CPUs to zynqmp board. They are powered off on reset (this is true of real hardware) by default or selectable as the boot processor. Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Message-id: da34128c73ca13fc4f8c3293e1a33d1e1e345655.1434501320.git.peter.crosthwaite@xilinx.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* arm: xlnx-zynqmp: Add boot-cpu propertyPeter Crosthwaite2015-06-191-0/+3
| | | | | | | | | | | Add a string property that specifies the primary boot cpu. All CPUs except the one selected will start-powered-off. This allows for elf boots on any CPU, which prepares support for booting R5 elfs directly on the R5 processors. Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Message-id: 53331c00d80c7ce9c6a83712348773f1b38fae2b.1434501320.git.peter.crosthwaite@xilinx.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* arm: xlnx-zynqmp: Preface CPU variables with "apu"Peter Crosthwaite2015-06-191-2/+2
| | | | | | | | | | | | The CPUs currently supported by zynqmp are the APU (application processing unit) CPUs. There are other CPUs in Zynqmp so unqualified "cpus" in ambiguous. Preface the variables with "APU" accordingly, to prepare support adding the RPU (realtime processing unit) processors. Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Message-id: ce32287fc365aea898465e981da3546a227e0811.1434501320.git.peter.crosthwaite@xilinx.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* hw/arm/sysbus-fdt: enable vfio-calxeda-xgmac dynamic instantiationEric Auger2015-06-191-0/+34
| | | | | | | | | | | | | This patch allows the instantiation of the vfio-calxeda-xgmac device from the QEMU command line (-device vfio-calxeda-xgmac,host="<device>"). A specialized device tree node is created for the guest, containing compat, dma-coherent, reg and interrupts properties. Signed-off-by: Eric Auger <eric.auger@linaro.org> Acked-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1434455898-17895-1-git-send-email-eric.auger@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* hw/arm/virt: add dynamic sysbus device supportEric Auger2015-06-021-0/+1
| | | | | | | | | | | | | | | | | | | Allows sysbus devices to be instantiated from command line by using -device option. Machvirt creates a platform bus at init. The dynamic sysbus devices are attached to this platform bus device. The platform bus device registers a machine init done notifier whose role will be to bind the dynamic sysbus devices. Indeed dynamic sysbus devices are created after machine init. machvirt also registers a notifier that will build the device tree nodes for the platform bus and its children dynamic sysbus devices. Signed-off-by: Eric Auger <eric.auger@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Message-id: 1433244554-12898-4-git-send-email-eric.auger@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* hw/arm/boot: arm_load_kernel implemented as a machine init done notifierEric Auger2015-06-021-0/+28
| | | | | | | | | | | | | | | | | | | | | Device tree nodes for the platform bus and its children dynamic sysbus devices are added in a machine init done notifier. To load the dtb once, after those latter nodes are built and before ROM freeze, the actual arm_load_kernel existing code is moved into a notifier notify function, arm_load_kernel_notify. arm_load_kernel now only registers the corresponding notifier. Machine files that do not support platform bus stay unchanged. Machine files willing to support dynamic sysbus devices must call arm_load_kernel before sysbus-fdt arm_register_platform_bus_fdt_creator to make sure dynamic sysbus device nodes are integrated in the dtb. Signed-off-by: Eric Auger <eric.auger@linaro.org> Reviewed-by: Shannon Zhao <zhaoshenglong@huawei.com> Reviewed-by: Alexander Graf <agraf@suse.de> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Message-id: 1433244554-12898-3-git-send-email-eric.auger@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* hw/arm/sysbus-fdt: helpers for platform bus nodes additionEric Auger2015-06-021-0/+60
| | | | | | | | | | | | | | | | | | | | This new C module will be used by ARM machine files to generate platform bus node and their dynamic sysbus device tree nodes. Dynamic sysbus device node addition is done in a machine init done notifier. arm_register_platform_bus_fdt_creator does the registration of this latter and is supposed to be called by ARM machine files that support platform bus and their dynamic sysbus. Addition of dynamic sysbus nodes is done only if the user did not provide any dtb. Signed-off-by: Alexander Graf <agraf@suse.de> Signed-off-by: Eric Auger <eric.auger@linaro.org> Reviewed-by: Shannon Zhao <zhaoshenglong@huawei.com> Reviewed-by: Alexander Graf <agraf@suse.de> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Message-id: 1433244554-12898-2-git-send-email-eric.auger@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* target-arm: Add the GICv2m to the virt boardChristoffer Dall2015-06-021-0/+2
| | | | | | | | | | | | Add a GICv2m device to the virt board to enable MSIs on the generic PCI host controller. We allocate 64 SPIs in the IRQ space for now (this can be increased/decreased later) and map the GICv2m right after the GIC in the memory map. Reviewed-by: Eric Auger <eric.auger@linaro.org> Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org> Message-id: 1432897270-7780-5-git-send-email-christoffer.dall@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* hw/arm/virt-acpi-build: Generate GTDT tableShannon Zhao2015-05-291-0/+5
| | | | | | | | | | | | ACPI v5.1 defines GTDT for ARM devices as a place to describe timer related information in the system. The Arch Timer interrupts must be provided for GTDT. Signed-off-by: Shannon Zhao <zhaoshenglong@huawei.com> Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Message-id: 1432522520-8068-11-git-send-email-zhaoshenglong@huawei.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* hw/arm/virt-acpi-build: Generate MADT tableShannon Zhao2015-05-291-0/+3
| | | | | | | | | | | MADT describes GIC enabled ARM platforms. The GICC and GICD subtables are used to define the GIC regions. Signed-off-by: Shannon Zhao <zhaoshenglong@huawei.com> Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Message-id: 1432522520-8068-10-git-send-email-zhaoshenglong@huawei.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* hw/arm/virt-acpi-build: Basic framework for building ACPI tables on ARMShannon Zhao2015-05-291-0/+41
| | | | | | | | | | | | | | | | | | | | | Introduce a preliminary framework in virt-acpi-build.c with the main ACPI build functions. It exposes the generated ACPI contents to guest over fw_cfg. The required ACPI v5.1 tables for ARM are: - RSDP: Initial table that points to XSDT - RSDT: Points to FADT GTDT MADT tables - FADT: Generic information about the machine - GTDT: Generic timer description table - MADT: Multiple APIC description table - DSDT: Holds all information about system devices/peripherals, pointed by FADT Signed-off-by: Shannon Zhao <zhaoshenglong@huawei.com> Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Igor Mammedov <imammedo@redhat.com> Message-id: 1432522520-8068-5-git-send-email-zhaoshenglong@huawei.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* hw/arm/virt: Record PCIe ranges in MemMapEntry arrayShannon Zhao2015-05-291-0/+3
| | | | | | | | | | | To generate ACPI table for PCIe controller, we need the base and size of the PCIe ranges. Record these ranges in MemMapEntry array, then we could share and use them for generating ACPI table. Signed-off-by: Shannon Zhao <zhaoshenglong@huawei.com> Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org> Message-id: 1432522520-8068-4-git-send-email-zhaoshenglong@huawei.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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