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* aspeed/i2c: Add support for DMA transfersCédric Le Goater2019-12-161-0/+5
| | | | | | | | | | | | | | | | | | The I2C controller of the Aspeed AST2500 and AST2600 SoCs supports DMA transfers to and from DRAM. A pair of registers defines the buffer address and the length of the DMA transfer. The address should be aligned on 4 bytes and the maximum length should not exceed 4K. The receive or transmit DMA transfer can then be initiated with specific bits in the Command/Status register of the controller. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Tested-by: Jae Hyun Yoo <jae.hyun.yoo@linux.intel.com> Signed-off-by: Cédric Le Goater <clg@kaod.org> Message-id: 20191119141211.25716-5-clg@kaod.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* aspeed/i2c: Check SRAM enablement on AST2500Cédric Le Goater2019-12-161-0/+3
| | | | | | | | | | | | The SRAM must be enabled before using the Buffer Pool mode or the DMA mode. This is not required on other SoCs. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Tested-by: Jae Hyun Yoo <jae.hyun.yoo@linux.intel.com> Signed-off-by: Cédric Le Goater <clg@kaod.org> Message-id: 20191119141211.25716-3-clg@kaod.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* aspeed/i2c: Add support for pool buffer transfersCédric Le Goater2019-12-161-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Aspeed I2C controller can operate in different transfer modes : - Byte Buffer mode, using a dedicated register to transfer a byte. This is what the model supports today. - Pool Buffer mode, using an internal SRAM to transfer multiple bytes in the same command sequence. Each SoC has different SRAM characteristics. On the AST2400, 2048 bytes of SRAM are available at offset 0x800 of the controller AHB window. The pool buffer can be configured from 1 to 256 bytes per bus. On the AST2500, the SRAM is at offset 0x200 and the pool buffer is of 16 bytes per bus. On the AST2600, the SRAM is at offset 0xC00 and the pool buffer is of 32 bytes per bus. It can be splitted in two for TX and RX but the current model does not add support for it as it it unused by known drivers. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Tested-by: Jae Hyun Yoo <jae.hyun.yoo@linux.intel.com> Signed-off-by: Cédric Le Goater <clg@kaod.org> Message-id: 20191119141211.25716-2-clg@kaod.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* aspeed/i2c: Add AST2600 supportCédric Le Goater2019-10-151-1/+4
| | | | | | | | | | | The I2C controller of the AST2400 and AST2500 SoCs have one IRQ shared by all I2C busses. The AST2600 SoC I2C controller has one IRQ per bus and 16 busses. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Message-id: 20190925143248.10000-17-clg@kaod.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* aspeed/i2c: Introduce an object class per SoCCédric Le Goater2019-10-151-0/+15
| | | | | | | | | It prepares ground for register differences between SoCs. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Message-id: 20190925143248.10000-16-clg@kaod.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* Include hw/qdev-properties.h lessMarkus Armbruster2019-08-161-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | In my "build everything" tree, changing hw/qdev-properties.h triggers a recompile of some 2700 out of 6600 objects (not counting tests and objects that don't depend on qemu/osdep.h). Many places including hw/qdev-properties.h (directly or via hw/qdev.h) actually need only hw/qdev-core.h. Include hw/qdev-core.h there instead. hw/qdev.h is actually pointless: all it does is include hw/qdev-core.h and hw/qdev-properties.h, which in turn includes hw/qdev-core.h. Replace the remaining uses of hw/qdev.h by hw/qdev-properties.h. While there, delete a few superfluous inclusions of hw/qdev-core.h. Touching hw/qdev-properties.h now recompiles some 1200 objects. Cc: Paolo Bonzini <pbonzini@redhat.com> Cc: "Daniel P. Berrangé" <berrange@redhat.com> Cc: Eduardo Habkost <ehabkost@redhat.com> Signed-off-by: Markus Armbruster <armbru@redhat.com> Reviewed-by: Eduardo Habkost <ehabkost@redhat.com> Message-Id: <20190812052359.30071-22-armbru@redhat.com>
* Include exec/memory.h slightly lessMarkus Armbruster2019-08-162-0/+2
| | | | | | | | | | Drop unnecessary inclusions from headers. Downgrade a few more to exec/hwaddr.h. Signed-off-by: Markus Armbruster <armbru@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-Id: <20190812052359.30071-17-armbru@redhat.com>
* include: Make headers more self-containedMarkus Armbruster2019-08-161-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Back in 2016, we discussed[1] rules for headers, and these were generally liked: 1. Have a carefully curated header that's included everywhere first. We got that already thanks to Peter: osdep.h. 2. Headers should normally include everything they need beyond osdep.h. If exceptions are needed for some reason, they must be documented in the header. If all that's needed from a header is typedefs, put those into qemu/typedefs.h instead of including the header. 3. Cyclic inclusion is forbidden. This patch gets include/ closer to obeying 2. It's actually extracted from my "[RFC] Baby steps towards saner headers" series[2], which demonstrates a possible path towards checking 2 automatically. It passes the RFC test there. [1] Message-ID: <87h9g8j57d.fsf@blackfin.pond.sub.org> https://lists.nongnu.org/archive/html/qemu-devel/2016-03/msg03345.html [2] Message-Id: <20190711122827.18970-1-armbru@redhat.com> https://lists.nongnu.org/archive/html/qemu-devel/2019-07/msg02715.html Signed-off-by: Markus Armbruster <armbru@redhat.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20190812052359.30071-2-armbru@redhat.com> Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com>
* hw/i2c/bitbang_i2c: Use in-place rather than malloc'd bitbang_i2c_interface ↵Peter Maydell2019-07-032-2/+38
| | | | | | | | | | | | | | | | | | | | | | | | | | | | struct Currently the bitbang_i2c_init() function allocates a bitbang_i2c_interface struct which it returns. This is unfortunate because it means that if the function is used from a DeviceState init method then the memory will be leaked by an "init then delete" cycle, as used by the qmp/hmp commands that list device properties. Since three out of four of the uses of this function are in device init methods, switch the function to do an in-place initialization of a struct that can be embedded in the device state struct of the caller. This fixes LeakSanitizer leak warnings that have appeared in the patchew configuration (which only tries to run the sanitizers for the x86_64-softmmu target) now that we use the bitbang-i2c code in an x86-64 config. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: BALATON Zoltan <balaton@eik.bme.hu> Tested-by: BALATON Zoltan <balaton@eik.bme.hu> Acked-by: David Gibson <david@gibson.dropbear.id.au> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-id: 20190702163844.20458-1-peter.maydell@linaro.org Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
* i2c: Move bitbang_i2c.h to include/hw/i2c/BALATON Zoltan2019-06-283-3/+15
| | | | | | | | | | | | | | | The bitbang i2c implementation is also useful for other device models such as DDC in display controllers. Move the header to include/hw/i2c/ to allow it to be used from other device models and adjust users of this include. This also reverts commit 2b4c1125ac which is no longer needed. Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com> Acked-by: Corey Minyard <cminyard@mvista.com> Message-id: 5d1fe4db846ab9be4b77ddb0d43cc74cd200a003.1561028123.git.balaton@eik.bme.hu Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
* Include qemu-common.h exactly where neededMarkus Armbruster2019-06-121-1/+0Star
| | | | | | | | | | | | | | | | No header includes qemu-common.h after this commit, as prescribed by qemu-common.h's file comment. Signed-off-by: Markus Armbruster <armbru@redhat.com> Message-Id: <20190523143508.25387-5-armbru@redhat.com> [Rebased with conflicts resolved automatically, except for include/hw/arm/xlnx-zynqmp.h hw/arm/nrf51_soc.c hw/arm/msf2-soc.c block/qcow2-refcount.c block/qcow2-cluster.c block/qcow2-cache.c target/arm/cpu.h target/lm32/cpu.h target/m68k/cpu.h target/mips/cpu.h target/moxie/cpu.h target/nios2/cpu.h target/openrisc/cpu.h target/riscv/cpu.h target/tilegx/cpu.h target/tricore/cpu.h target/unicore32/cpu.h target/xtensa/cpu.h; bsd-user/main.c and net/tap-bsd.c fixed up]
* i2c-ddc: move it to hw/displayPaolo Bonzini2019-05-071-40/+0Star
| | | | | | | | | | Move it together with the other EDID code. hw/i2c should only include the core and the adapters, not the slaves. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-id: 20190325155923.30987-1-pbonzini@redhat.com Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
* i2c:smbus_slave: Add an SMBus vmstate structureCorey Minyard2019-02-281-3/+21
| | | | | | | | | | | There is no vmstate handling for SMBus, so no device sitting on SMBus can have a state transfer that works reliably. So add it. Signed-off-by: Corey Minyard <cminyard@mvista.com> Cc: Paolo Bonzini <pbonzini@redhat.com> Cc: Michael S. Tsirkin <mst@redhat.com> Cc: Dr. David Alan Gilbert <dgilbert@redhat.com> Reviewed-by: Dr. David Alan Gilbert <dgilbert@redhat.com>
* i2c:pm_smbus: Fix state transferCorey Minyard2019-02-281-0/+9
| | | | | | | | | | | Transfer the state information for the SMBus registers and internal data so it will work on a VM transfer. Signed-off-by: Corey Minyard <cminyard@mvista.com> Cc: Michael S. Tsirkin <mst@redhat.com> Cc: Paolo Bonzini <pbonzini@redhat.com> Cc: Dr. David Alan Gilbert <dgilbert@redhat.com> Reviewed-by: Dr. David Alan Gilbert <dgilbert@redhat.com>
* i2c:pm_smbus: Fix pm_smbus handling of I2C block readCorey Minyard2019-02-281-0/+6
| | | | | | | | | | | | | | | | | | | The I2C block read function of pm_smbus was completely broken. It required doing some direct I2C handling because it didn't have a defined size, the OS code just reads bytes until it marks the transaction finished. This also required adjusting how the AMIBIOS workaround code worked, the I2C block mode was setting STS_HOST_BUSY during a transaction, so that bit could no longer be used to inform the host status read code to start the transaction. Create a explicit bool for that operation. Also, don't read the next byte from the device in byte-by-byte mode unless the OS is actually clearing the byte done bit. Just assuming that's what the OS is doing is a bad idea. Signed-off-by: Corey Minyard <cminyard@mvista.com>
* i2c:smbus: Simplify read handlingCorey Minyard2019-02-281-7/+10
| | | | | | | | | There were two different read functions, and with the removal of the command passed in there is no functional difference. So remove one of them. With that you don't need one of the states, so that can be removed, too. Signed-off-by: Corey Minyard <cminyard@mvista.com>
* i2c:smbus: Simplify write operationCorey Minyard2019-02-281-8/+13
| | | | | | | | | | | | There were two different write functions and the SMBus code kept track of the command. Keeping track of the command wasn't useful, in fact it wasn't quite correct for the eeprom_smbus code. And there is no need for two write functions. Just have one write function and the first byte in the buffer is the command. Signed-off-by: Corey Minyard <cminyard@mvista.com>
* i2c:smbus: Correct the working of quick commandsCorey Minyard2019-02-281-0/+5
| | | | | | | | | The logic of handling quick SMBus commands was wrong. If you get a finish event with no data, that's a quick command. Document the quick command while we are at it. Signed-off-by: Corey Minyard <cminyard@mvista.com>
* i2c: have I2C receive operation return uint8_tCorey Minyard2019-02-281-4/+3Star
| | | | | | | | | | | It is never supposed to fail and cannot return an error, so just have it return the proper type. Have it return 0xff on nothing available, since that's what would happen on a real bus. Signed-off-by: Corey Minyard <cminyard@mvista.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com>
* i2c: Split smbus into partsCorey Minyard2019-02-284-36/+96
| | | | | | | | | | smbus.c and smbus.h had device side code, master side code, and smbus.h has some smbus_eeprom.c definitions. Split them into separate files. Signed-off-by: Corey Minyard <cminyard@mvista.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com>
* smbus: Add a helper to generate SPD EEPROM dataBALATON Zoltan2019-02-041-0/+3
| | | | | | | | | | | There are several boards with SPD EEPROMs that are now using duplicated or slightly different hard coded data. Add a helper to generate SPD data for a memory module of given type and size that could be used by these boards (either as is or with further changes if needed) which should help cleaning this up and avoid further duplication. Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
* arm: Stub out NRF51 TWI magnetometer/accelerometer detectionSteffen Görtz2019-01-291-0/+42
| | | | | | | | | | | | | Recent microbit firmwares panic if the TWI magnetometer/accelerometer devices are not detected during startup. We don't implement TWI (I2C) so let's stub out these devices just to let the firmware boot. Signed-off by: Steffen Görtz <contrib@steffen-goertz.de> Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com> Message-id: 20190110094020.18354-2-stefanha@redhat.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> [PMM: fixed comment style] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* hw/i2c/smbus: Remove SMBusDevice from "qemu/typedefs.h"Philippe Mathieu-Daudé2019-01-221-0/+2
| | | | | | | | | | Files requiring SMBusDevice already include "hw/i2c/smbus.h". To clean "qemu/typedefs.h", move the forward declaration to "hw/i2c/smbus.h". Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
* i2c: Move typedef of bitbang_i2c_interface to i2c.hBALATON Zoltan2018-12-122-3/+2Star
| | | | | | | | | | | | Clang 3.4 considers duplicate typedef in ppc4xx_i2c.h and bitbang_i2c.h an error even if they are identical. Move it to a common place to allow building with this clang version. Reported-by: Thomas Huth <thuth@redhat.com> Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu> Acked-by: David Gibson <david@gibson.dropbear.id.au> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
* i2c: switch ddc to use the new edid generatorGerd Hoffmann2018-10-151-1/+3
| | | | | | | | | | | | This also makes the default display resolution configurable, via xres and yres properties. The default is 1024x768. The old code had a hard-coded resolution of 1600x1200. Cc: Linus Walleij <linus.walleij@linaro.org> Cc: BALATON Zoltan <balaton@eik.bme.hu> Signed-off-by: Gerd Hoffmann <kraxel@redhat.com> Message-id: 20181005110837.28209-1-kraxel@redhat.com
* i2c: pm_smbus: Add the ability to force block transfer enableCorey Minyard2018-08-231-1/+1
| | | | | | | | | | | | | The PIIX4 hardware has block transfer buffer always enabled in the hardware, but the i801 does not. Add a parameter to pm_smbus_init to force on the block transfer so the PIIX4 handler can enable this by default, as it was disabled by default before. Signed-off-by: Corey Minyard <cminyard@mvista.com> Cc: Michael S. Tsirkin <mst@redhat.com> Cc: Paolo Bonzini <pbonzini@redhat.com> Message-Id: <1534796770-10295-9-git-send-email-minyard@acm.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
* i2c: pm_smbus: Add interrupt handlingCorey Minyard2018-08-231-0/+2
| | | | | | | | | | | Add the necessary code so that interrupts actually work from the pm_smbus device. Signed-off-by: Corey Minyard <cminyard@mvista.com> Cc: Michael S. Tsirkin <mst@redhat.com> Cc: Paolo Bonzini <pbonzini@redhat.com> Message-Id: <1534796770-10295-7-git-send-email-minyard@acm.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
* i2c: pm_smbus: Add block transfer capabilityCorey Minyard2018-08-231-2/+18
| | | | | | | | | | | | | | There was no block transfer code in pm_smbus.c, and it is needed for some devices. So add it. This adds both byte-by-byte block transfers and buffered block transfers. Signed-off-by: Corey Minyard <cminyard@mvista.com> Cc: Michael S. Tsirkin <mst@redhat.com> Cc: Paolo Bonzini <pbonzini@redhat.com> Message-Id: <1534796770-10295-5-git-send-email-minyard@acm.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
* i2c: pm_smbus: Fix the semantics of block I2C transfersCorey Minyard2018-08-231-2/+15
| | | | | | | | | | | | | | | | | The I2C block transfer commands was not implemented correctly, it read a length byte and such like it was an smbus transfer. So fix the smbus_read_block() and smbus_write_block() functions so they can properly handle I2C transfers, and normal SMBus transfers (for upcoming changes). Pass in a transfer size and a bool to know whether to use the size byte (like SMBus) or use the length given (like I2C). Signed-off-by: Corey Minyard <cminyard@mvista.com> Cc: Michael S. Tsirkin <mst@redhat.com> Cc: Paolo Bonzini <pbonzini@redhat.com> Message-Id: <1534796770-10295-3-git-send-email-minyard@acm.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
* ppc4xx_i2c: Rewrite to model hardware more closelyBALATON Zoltan2018-07-031-1/+2
| | | | | | | | | | | | Rewrite to make it closer to how real device works so that guest OS drivers can access I2C devices. Previously this was only a hack to allow U-Boot to get past accessing SPD EEPROMs but to support other I2C devices and allow guests to access them we need to model real device more properly. Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu> Reviewed-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
* ppc4xx_i2c: Implement directcntl registerBALATON Zoltan2018-06-211-0/+4
| | | | | | | | | | | | | As well as being able to generate its own i2c transactions, the ppc4xx i2c controller has a DIRECTCNTL register which allows explicit control of the i2c lines. Using this register an OS can directly bitbang i2c operations. In order to let emulated i2c devices respond to this, we need to wire up the DIRECTCNTL register to qemu's bitbanged i2c handling code. Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
* ppc4xx_i2c: Remove unimplemented sdata and intr registersBALATON Zoltan2018-06-211-3/+1Star
| | | | | | | | | | | | | | We don't emulate slave mode so related registers are not needed. [lh]sadr are only retained to avoid too many warnings and simplify debugging but sdata is not even correct because device has a 4 byte FIFO instead so just remove this unimplemented register for now. The intr register is also not implemented correctly, it is for diagnostics and normally not even visible on device without explicitly enabling it. As no guests are known to need this remove it as well. Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
* smbus: add a smbus_eeprom_init_one() routineCédric Le Goater2018-06-081-0/+1
| | | | | | | | | | | This is an helper routine to add a single EEPROM on an I2C bus. It can be directly used by smbus_eeprom_init() which adds a certain number of EEPROMs on mips and x86 machines. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-id: 20180530064049.27976-5-clg@kaod.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* hw/i2c: Use DeviceClass::realize instead of I2CSlaveClass::initPhilippe Mathieu-Daudé2018-06-011-3/+0Star
| | | | | | | | | | | I2CSlaveClass::init is no more used, remove it. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20180419212727.26095-3-f4bug@amsat.org> Reviewed-by: Markus Armbruster <armbru@redhat.com> Signed-off-by: Markus Armbruster <armbru@redhat.com> Message-Id: <20180528144509.15812-3-armbru@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
* hw/i2c/smbus: Use DeviceClass::realize instead of SMBusDeviceClass::initPhilippe Mathieu-Daudé2018-06-011-1/+0Star
| | | | | | | | | | | SMBusDeviceClass::init is no more used, remove it. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20180419212727.26095-2-f4bug@amsat.org> Reviewed-by: Markus Armbruster <armbru@redhat.com> Signed-off-by: Markus Armbruster <armbru@redhat.com> Message-Id: <20180528144509.15812-2-armbru@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
* i2c: Move the bus class to i2c.hCorey Minyard2018-03-011-0/+17
| | | | | | | | | | Some devices need access to it. Signed-off-by: Corey Minyard <cminyard@mvista.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Message-id: 20180227104903.21353-3-linus.walleij@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* i2c: Fix some brace style issuesCorey Minyard2018-03-011-4/+2Star
| | | | | | | | Signed-off-by: Corey Minyard <cminyard@mvista.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Message-id: 20180227104903.21353-2-linus.walleij@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* hw/audio/wm8750: move WM8750 declarations from i2c/i2c.h to audio/wm8750.hPhilippe Mathieu-Daudé2018-02-021-9/+0Star
| | | | | | | | while here use TYPE_WM8750 and declare a data_req_cb() typedef. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-id: 20170919123053.32675-1-f4bug@amsat.org Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
* ppc4xx_i2c: Implement basic I2C functionsBALATON Zoltan2018-01-101-0/+3
| | | | | | | | | Enough to please U-Boot and make it able to detect SDRAM SPD EEPROMs Signed-off-by: François Revol <revol@free.fr> Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
* hw: remove "qemu/osdep.h" from header filesPhilippe Mathieu-Daudé2017-12-181-1/+0Star
| | | | | | | | | | applied using ./scripts/clean-includes Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Corey Minyard <cminyard@mvista.com> Tested-by: Corey Minyard <cminyard@mvista.com> Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
* ppc4xx_i2c: QOMifyBALATON Zoltan2017-09-081-0/+61
| | | | | Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
* i2c: Allow I2C devices to NAK start eventsCorey Minyard2017-01-091-4/+12
| | | | | | | | | | | | | | | | | | | | Add a return value to the event handler. Some I2C devices will NAK if they have no data, so allow them to do this. This required the following changes: Go through all the event handlers and change them to return int and return 0. Modify i2c_start_transfer to terminate the transaction on a NAK. Modify smbus handing to not assert if a NAK occurs on a second operation, and terminate the transaction and return -1 instead. Add some information on semantics to I2CSlaveClass. Signed-off-by: Corey Minyard <cminyard@mvista.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* Clean up decorations and whitespace around header guardsMarkus Armbruster2016-07-121-1/+1
| | | | | | | Cleaned up with scripts/clean-header-guards.pl. Signed-off-by: Markus Armbruster <armbru@redhat.com> Reviewed-by: Richard Henderson <rth@twiddle.net>
* Clean up ill-advised or unusual header guardsMarkus Armbruster2016-07-122-6/+6
| | | | | | | Cleaned up with scripts/clean-header-guards.pl. Signed-off-by: Markus Armbruster <armbru@redhat.com> Reviewed-by: Richard Henderson <rth@twiddle.net>
* Use #include "..." for our own headers, <...> for othersMarkus Armbruster2016-07-121-1/+1
| | | | | | | | | | | | Tracked down with an ugly, brittle and probably buggy Perl script. Also move includes converted to <...> up so they get included before ours where that's obviously okay. Signed-off-by: Markus Armbruster <armbru@redhat.com> Reviewed-by: Eric Blake <eblake@redhat.com> Tested-by: Eric Blake <eblake@redhat.com> Reviewed-by: Richard Henderson <rth@twiddle.net>
* hw/i2c-ddc.c: Implement DDC I2C slavePeter Maydell2016-06-141-0/+38
| | | | | | | | | | | | | | | | | | | | Implement an I2C slave which implements DDC and returns the EDID data for an attached monitor. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@xilinx.com> Tested-by: Hyun Kwon <hyun.kwon@xilinx.com> Signed-off-by: KONRAD Frederic <fred.konrad@greensocs.com> Message-id: 1465833014-21982-7-git-send-email-fred.konrad@greensocs.com - Rebased on the current master. - Modified for QOM. Signed-off-by: KONRAD Frederic <fred.konrad@greensocs.com> Reviewed-by: Alistair Francis <alistair.francis@xilinx.com> Tested-By: Hyun Kwon <hyun.kwon@xilinx.com> [PMM: actually wire up the vmstate to dc->vmsd] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* i2c: Factor our send() and recv() common logicPeter Crosthwaite2016-06-141-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | Most of the control flow logic between send and recv (error checking etc) is the same. Factor this out into a common send_recv() API. This is then usable by clients, where the control logic for send and receive differs only by a boolean. E.g. if (send) i2c_send(...): else i2c_recv(...); becomes: i2c_send_recv(... , send); Signed-off-by: Peter Crosthwaite <crosthwaite.peter@gmail.com> Reviewed-by: Alistair Francis <alistair.francis@xilinx.com> Signed-off-by: KONRAD Frederic <fred.konrad@greensocs.com> Message-id: 1465833014-21982-4-git-send-email-fred.konrad@greensocs.com Changes from FK: * Rebased on master. * Rebased on my i2c broadcast patch. Signed-off-by: KONRAD Frederic <fred.konrad@greensocs.com> Reviewed-by: Alistair Francis <alistair.francis@xilinx.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* i2c: add aspeed i2c controllerCédric Le Goater2016-06-061-0/+62
| | | | | | | | | | | | | | | | | | | | | | | The Aspeed AST2400 integrates a set of 14 I2C/SMBus bus controllers directly connected to the APB bus. They can be programmed as master or slave but the propopsed model only supports the master mode. On the TODO list, we also have : - improve and harden the state machine. - bus recovery support (used by the Linux driver). - transfer mode state machine bits. this is not strictly necessary as it is mostly used for debug. The bus busy bit is deducted from the I2C core engine of qemu. - support of the pool buffer: 2048 bytes of internal SRAM (not used by the Linux driver). Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Andrew Jeffery <andrew@aj.id.au> Message-id: 1464704307-25178-1-git-send-email-clg@kaod.org [PMM: removed unused functions aspeed_i2c_bus_get_state() and aspeed_i2c_bus_set_state()] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* i.MX: Add I2C controller emulatorJean-Christophe Dubois2015-09-071-0/+87
| | | | | | | | | The slave mode is not implemented. Signed-off-by: Jean-Christophe Dubois <jcd@tribudubois.net> Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Message-id: 508dbf2ebe26ec383d3a12a1db5a7890ac8acf20.1441057361.git.jcd@tribudubois.net Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* smbus: return -1 if nothing found at the given addressPaolo Bonzini2014-05-071-6/+6
| | | | | | | Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Acked-by: Michael S. Tsirkin <mst@redhat.com> Reviewed-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
generated by cgit v1.2.3-55-g7522 (git 2.39.0) at 2024-12-22 19:08:00 +0100