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* riscv/opentitan: Connect the UART deviceAlistair Francis2020-06-191-0/+13
* riscv/opentitan: Connect the PLIC deviceAlistair Francis2020-06-191-0/+3
* sifive_e: Support the revB machineAlistair Francis2020-06-191-0/+1
* riscv: Fix type of SiFive[EU]SocState, member parent_objMarkus Armbruster2020-06-152-2/+2
* riscv: Initial commit of OpenTitan machineAlistair Francis2020-06-031-0/+68
* riscv/boot: Add a missing header includeAlistair Francis2020-06-031-0/+1
* riscv: sifive_e: Manually define the machineAlistair Francis2020-06-031-0/+4
* hw/riscv: spike: Remove deprecated ISA specific machinesAlistair Francis2020-06-031-4/+2Star
* hw/riscv: Add optional symbol callback ptr to riscv_load_firmware()Anup Patel2020-04-291-2/+4
* riscv/sifive_u: Add a serial property to the sifive_u machineBin Meng2020-04-291-0/+1
* riscv/sifive_u: Add a serial property to the sifive_u SoCAlistair Francis2020-04-291-0/+2
* hw/riscv: Provide rdtime callback for TCG in CLINT emulationAnup Patel2020-02-271-1/+2
* riscv: virt: Use Goldfish RTC deviceAnup Patel2020-02-101-0/+2
* hw/riscv: Add optional symbol callback ptr to riscv_load_kernel()Zhuang, Siwei (Data61, Kensington NSW)2019-11-251-1/+2
* riscv/virt: Add the PFlash CFI01 deviceAlistair Francis2019-10-281-0/+3
* riscv/virt: Manually define the machineAlistair Francis2019-10-281-1/+6
* riscv/sifive_u: Add the start-in-flash propertyAlistair Francis2019-10-281-0/+2
* riscv/sifive_u: Manually define the machineAlistair Francis2019-10-281-1/+6
* riscv/sifive_u: Add QSPI memory regionAlistair Francis2019-10-281-0/+1
* riscv/sifive_u: Add L2-LIM cache memoryAlistair Francis2019-10-281-0/+1
* riscv: hw: Drop "clock-frequency" property of cpu nodesBin Meng2019-10-283-9/+0Star
* riscv: sifive_u: Remove handcrafted clock nodes for UART and ethernetBin Meng2019-09-171-2/+1Star
* riscv: sifive_u: Fix broken GEM supportBin Meng2019-09-171-1/+2
* riscv: sifive_u: Instantiate OTP memory with a serial numberBin Meng2019-09-171-0/+3
* riscv: sifive: Implement a model for SiFive FU540 OTPBin Meng2019-09-171-0/+80
* riscv: sifive_u: Update UART base addresses and IRQsBin Meng2019-09-171-2/+2
* riscv: sifive_u: Reference PRCI clocks in UART and ethernet nodesBin Meng2019-09-171-0/+10
* riscv: sifive_u: Add PRCI block to the SoCBin Meng2019-09-171-0/+3
* riscv: sifive_u: Generate hfclk and rtcclk nodesBin Meng2019-09-171-0/+2
* riscv: sifive: Implement PRCI model for FU540Bin Meng2019-09-171-0/+81
* riscv: sifive_u: Update hart configuration to reflect the real FU540 SoCBin Meng2019-09-171-1/+5
* riscv: sifive_u: Set the minimum number of cpus to 2Bin Meng2019-09-171-0/+2
* riscv: hart: Add a "hartid-base" property to RISC-V hart arrayBin Meng2019-09-171-0/+1
* riscv: Add a sifive_cpu.h to include both E and U cpu type definesBin Meng2019-09-173-12/+33
* riscv: sifive_e: prci: Update the PRCI register block sizeBin Meng2019-09-171-0/+2
* riscv: sifive: Rename sifive_prci.{c, h} to sifive_e_prci.{c, h}Bin Meng2019-09-172-71/+69Star
* riscv: sifive_test: Add reset functionalityBin Meng2019-09-171-1/+2
* riscv: Add a helper routine for finding firmwareBin Meng2019-09-171-0/+1
* riscv: plic: Remove unused interrupt functionsAlistair Francis2019-09-171-3/+0Star
* Clean up inclusion of sysemu/sysemu.hMarkus Armbruster2019-08-161-1/+0Star
* Include hw/hw.h exactly where neededMarkus Armbruster2019-08-161-1/+0Star
* include: Make headers more self-containedMarkus Armbruster2019-08-1611-1/+23
* hw/riscv: Load OpenSBI as the default firmwareAlistair Francis2019-07-181-0/+3
* hw/riscv: Add support for loading a firmwareAlistair Francis2019-06-271-0/+2
* hw/riscv: Split out the boot functionsAlistair Francis2019-06-271-0/+27
* RISC-V: Fix a memory leak when realizing a sifive_ePalmer Dabbelt2019-06-241-0/+2
* sifive_prci: Read and write PRCI registersNathaniel Graff2019-06-241-0/+32
* target/riscv: Add a base 32 and 64 bit CPUAlistair Francis2019-05-241-2/+2
* SiFive RISC-V GPIO DeviceFabien Chouteau2019-05-242-2/+78
* Clean up decorations and whitespace around header guardsMarkus Armbruster2019-05-131-1/+0Star
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