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* Clean up ill-advised or unusual header guardsMarkus Armbruster2016-07-1228-80/+85
| | | | | | | Cleaned up with scripts/clean-header-guards.pl. Signed-off-by: Markus Armbruster <armbru@redhat.com> Reviewed-by: Richard Henderson <rth@twiddle.net>
* Clean up header guards that don't match their file nameMarkus Armbruster2016-07-1229-67/+73
| | | | | | | | | | | | Header guard symbols should match their file name to make guard collisions less likely. Offenders found with scripts/clean-header-guards.pl -vn. Cleaned up with scripts/clean-header-guards.pl, followed by some renaming of new guard symbols picked by the script to better ones. Signed-off-by: Markus Armbruster <armbru@redhat.com> Reviewed-by: Richard Henderson <rth@twiddle.net>
* spapr_pci: Include spapr.h instead of playing games with #errorMarkus Armbruster2016-07-121-3/+1Star
| | | | | | | | | | | include/hw/pci-host/spapr.h needs hw/ppc/spapr.h. It checks whether its header guard is defined, and errors out if it isn't. Playing games with some other header's guard symbol is not a good idea. Just include the frackin' header already. Signed-off-by: Markus Armbruster <armbru@redhat.com> Reviewed-by: Richard Henderson <rth@twiddle.net>
* Use #include "..." for our own headers, <...> for othersMarkus Armbruster2016-07-129-11/+11
| | | | | | | | | | | | Tracked down with an ugly, brittle and probably buggy Perl script. Also move includes converted to <...> up so they get included before ours where that's obviously okay. Signed-off-by: Markus Armbruster <armbru@redhat.com> Reviewed-by: Eric Blake <eblake@redhat.com> Tested-by: Eric Blake <eblake@redhat.com> Reviewed-by: Richard Henderson <rth@twiddle.net>
* Merge remote-tracking branch 'remotes/lalrae/tags/mips-20160712' into stagingPeter Maydell2016-07-124-0/+291
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | MIPS patches 2016-07-12 Changes: * support 10-bit ASIDs * MIPS64R6-generic renamed to I6400 * initial GIC support * implement RESET_BASE register in CM GCR # gpg: Signature made Tue 12 Jul 2016 11:49:50 BST # gpg: using RSA key 0x52118E3C0B29DA6B # gpg: Good signature from "Leon Alrae <leon.alrae@imgtec.com>" # Primary key fingerprint: 8DD3 2F98 5495 9D66 35D4 4FC0 5211 8E3C 0B29 DA6B * remotes/lalrae/tags/mips-20160712: target-mips: enable 10-bit ASIDs in I6400 CPU target-mips: support CP0.Config4.AE bit target-mips: change ASID type to hold more than 8 bits target-mips: add ASID mask field and replace magic values target-mips: replace MIPS64R6-generic with the real I6400 CPU model hw/mips_cmgcr: implement RESET_BASE register in CM GCR hw/mips_cpc: make VP correctly start from the reset vector target-mips: add exception base to MIPS CPU hw/mips/cps: create GIC block inside CPS hw/mips: implement Global Interrupt Controller hw/mips: implement GIC Interval Timer Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * hw/mips_cmgcr: implement RESET_BASE register in CM GCRLeon Alrae2016-07-121-0/+18
| | | | | | | | | | | | | | | | | | | | | | Implement RESET_BASE register which is local to each VP and a write to it changes VP's reset exception base. Also, add OTHER register to allow a software running on one VP to access other VP's local registers. Guest can use this mechanism to specify custom address from which a VP will start execution. Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
| * hw/mips/cps: create GIC block inside CPSLeon Alrae2016-07-122-0/+11
| | | | | | | | | | | | Add GIC to CPS and expose its interrupt pins instead of CPU's. Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
| * hw/mips: implement Global Interrupt ControllerYongbok Kim2016-07-121-0/+216
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Global Interrupt Controller (GIC) is responsible for mapping each internal and external interrupt to the correct location for servicing. The internal representation of registers is different from the specification in order to consolidate information for each GIC Interrupt Sources and Virtual Processors with same functionalities. For example SH_MAP00_VP00 registers are defined like each bit represents a VP but in this implementation the equivalent map_vp contains VP number in integer form for ease accesses. When it is being accessed via read write functions an internal data is converted back into the original format as the specification. Limitations: Level triggering only GIC CounterHi not implemented (Countbits = 32bits) DINT not implemented Local WatchDog, Fast Debug Channel, Perf Counter not implemented Signed-off-by: Yongbok Kim <yongbok.kim@imgtec.com> Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
| * hw/mips: implement GIC Interval TimerYongbok Kim2016-07-121-0/+46
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The interval timer is similar to the CP0 Count/Compare timer within each processor. The difference is the GIC_SH_COUNTER register is global to the system so that all processors have the same time reference. To ease implementation, all VPs are having its own QEMU timer but sharing global settings and registers such as GIC_SH_CONFIG.COUTNSTOP and GIC_SH_COUNTER. MIPS GIC Interval Timer does support upto 64 bits of Count register but in this implementation it is limited to 32 bits only. Signed-off-by: Yongbok Kim <yongbok.kim@imgtec.com> Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
* | Merge remote-tracking branch 'remotes/cohuck/tags/s390x-20160711' into stagingPeter Maydell2016-07-113-0/+50
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Last round of s390x patches for 2.7: - A large update of the s390x PCI code, bringing it in line with the architecture - Fixes and improvements in the ipl (boot) code - Refactoring in the css code # gpg: Signature made Mon 11 Jul 2016 09:04:51 BST # gpg: using RSA key 0xDECF6B93C6F02FAF # gpg: Good signature from "Cornelia Huck <huckc@linux.vnet.ibm.com>" # gpg: aka "Cornelia Huck <cornelia.huck@de.ibm.com>" # Primary key fingerprint: C3D0 D66D C362 4FF6 A8C0 18CE DECF 6B93 C6F0 2FAF * remotes/cohuck/tags/s390x-20160711: (25 commits) s390x/pci: make hot-unplug handler smoother s390x/pci: replace fid with idx in msg data of msix s390x/pci: fix stpcifc_service_call s390x/pci: refactor list_pci s390x/pci: refactor s390_pci_find_dev_by_idx s390x/pci: add checkings in CLP_SET_PCI_FN s390x/pci: enable zpci hot-plug/hot-unplug s390x/pci: enable uid-checking s390x/pci: introduce S390PCIBusDevice qdev s390x/pci: introduce S390PCIIOMMU s390x/pci: introduce S390PCIBus s390x/pci: enforce zPCI state checking s390x/pci: refactor s390_pci_find_dev_by_fh s390x/pci: unify FH_ macros s390x/pci: write fid in CLP_QUERY_PCI_FN s390x/pci: acceleration for getting S390pciState s390x/pci: fix failures of dma map/unmap s390x/css: Unplug handler of virtual css bridge s390x/css: Factor out virtual css bridge and bus s390x/css: use define for "virtual-css-bridge" literal ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * | s390x/pci: enforce zPCI state checkingYi Min Zhao2016-07-111-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Current code uses some fields combinatorially to indicate the state of a s390 pci device. This patch introduces device states in order to make the code more readable and more logical. Signed-off-by: Yi Min Zhao <zyimin@linux.vnet.ibm.com> Reviewed-by: Pierre Morel <pmorel@linux.vnet.ibm.com> Signed-off-by: Cornelia Huck <cornelia.huck@de.ibm.com>
| * | s390x/css: Factor out virtual css bridge and busJing Liu2016-07-111-0/+31
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently, common base layers virtual css bridge and bus are defined in hw/s390x/virtio-ccw.c(h). In order to support multiple types of devices in the virtual channel subsystem, especially non virtio-ccw, refactoring work needs to be done. This work is just a pure code move without any functional change except dropping an empty function virtual_css_bridge_init() and virtio_ccw_busdev_unplug() changing. virtio_ccw_busdev_unplug() is specific to virtio-ccw but gets referenced from the common virtual css bridge code. To keep the functional changes to a minimum we export this function from virtio-ccw.c and continue to reference it inside virtual_css_bridge_class_init() (now living in hw/s390x/css-bridge.c). A follow-up patch will clean this up. Signed-off-by: Jing Liu <liujbjl@linux.vnet.ibm.com> Reviewed-by: Sascha Silbe <silbe@linux.vnet.ibm.com> Reviewed-by: Dong Jia Shi <bjsdjshi@linux.vnet.ibm.com> Signed-off-by: Cornelia Huck <cornelia.huck@de.ibm.com>
| * | s390x/css: factor out some generic code from virtio_ccw_device_realize()Sascha Silbe2016-07-111-0/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | A lot of what virtio_ccw_device_realize() does isn't specific to virtio; it would apply to emulated CCW as well. Factor it out to make it easier to implement emulated CCW devices later on. Signed-off-by: Sascha Silbe <silbe@linux.vnet.ibm.com> Reviewed-by: Dong Jia Shi <bjsdjshi@linux.vnet.ibm.com> Reviewed-by: Halil Pasic <pasic@linux.vnet.ibm.com> Signed-off-by: Cornelia Huck <cornelia.huck@de.ibm.com>
* | | machine: Add machine_register_compat_props() functionEduardo Habkost2016-07-071-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | Move the compat_props handling to core machine code. Reviewed-by: Marcel Apfelbaum <marcel@redhat.com> Reviewed-by: Markus Armbruster <armbru@redhat.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
* | | qdev: GlobalProperty.errp fieldEduardo Habkost2016-07-071-0/+4
|/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | | The new field will allow error handling to be configured by qdev_prop_register_global() callers: &error_fatal and &error_abort can be used to make QEMU exit or abort if any errors are reported when applying the properties. While doing it, change the error message from "global %s.%s=%s ignored" to "can't apply global %s.%s=%s". Suggested-by: Paolo Bonzini <pbonzini@redhat.com> Reviewed-by: Igor Mammedov <imammedo@redhat.com> Reviewed-by: Markus Armbruster <armbru@redhat.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
* | i.MX: split the GPT timer implementation into per SOC definitionsJean-Christophe Dubois2016-07-072-2/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In various Freescale SOCs, the GPT timers can be configured to select its input clock. Depending on the SOC the set of available input clocks may vary. The actual single GPT definition was no good enough and because of it booting the sabrelite board with a i.MX6DL device tree would fail because of an incorrect input clock definition for the i.MX6DL SOC. This patch fixes the i.MX6DL boot failure by adding the ability to define a different set of input clocks depending on the considered SOC. A different class has been defined for i.MX25, i.MX31 and i.MX6 each with its specific set of input clocks. The patch has been tested by booting KZM, i.MX25 PDK, i.MX6Q sabrelite and i.MX6DL sabrelite. Signed-off-by: Jean-Christophe Dubois <jcd@tribudubois.net> Message-id: 1467325619-8374-1-git-send-email-jcd@tribudubois.net Reviewed-by: Peter Maydell <peter.maydell@linaro.org> [PMM: fixed spacing round '/' operator] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* | aux: Rename aux.[ch] to auxbus.[ch] for the benefit of WindowsPeter Maydell2016-07-072-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On Windows 'aux.*' is a reserved name and cannot be used for filenames; see https://msdn.microsoft.com/en-gb/library/windows/desktop/aa365247(v=vs.85).aspx This prevents cloning the QEMU git repo on Windows: C:\Java\sources\kvm> git clone https://github.com/qemu/qemu.git Cloning into 'qemu'... remote: Counting objects: 279563, done. remote: Total 279563 (delta 0), reused 0 (delta 0), pack-reused 279563R Receiving objects: 100% (279563/279563), 122.45 MiB | 3.52 MiB/s, done. Resolving deltas: 100% (221942/221942), done. Checking connectivity... done. error: unable to create file hw/misc/aux.c (No such file or directory) error: unable to create file include/hw/misc/aux.h (No such file or directory) Checking out files: 100% (4795/4795), done. fatal: unable to checkout working tree warning: Clone succeeded, but checkout failed. You can inspect what was checked out with 'git status' and retry the checkout with 'git checkout -f HEAD' (bug https://bugs.launchpad.net/bugs/1595240) Rename the offending files for the benefit of Windows. Reported-by: Алексей Курган <akurgan@yandex.ru> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Eric Blake <eblake@redhat.com> Reviewed-by: Wei Huang <wei@redhat.com> Tested-by: KONRAD Frederic <fred.konrad@greensocs.com> Message-id: 1467377145-32385-1-git-send-email-peter.maydell@linaro.org
* | tap: vhost busy polling supportJason Wang2016-07-072-1/+5
| | | | | | | | | | | | | | | | | | | | | | This patch add the capability of basic vhost net busy polling which is supported by recent kernel. User could configure the maximum number of us that could be spent on busy polling through a new property of tap "poll-us". Cc: Greg Kurz <groug@kaod.org> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Jason Wang <jasowang@redhat.com>
* | virgl: count the calls to gl_blockMarc-André Lureau2016-07-061-1/+1
| | | | | | | | | | | | | | | | | | | | In virgl_cmd_resource_flush(), when several consoles are updated, it needs to keep blocking until all spice gl draws are done. This fixes an assert() in spice when using multiple monitors with virgl. Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com> Message-id: 1465911849-30423-2-git-send-email-marcandre.lureau@redhat.com Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
* | Merge remote-tracking branch 'remotes/mst/tags/for_upstream' into stagingPeter Maydell2016-07-054-8/+5Star
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | pc, pci, virtio: new features, cleanups, fixes iommus can not be added with -device. cleanups and fixes all over the place Signed-off-by: Michael S. Tsirkin <mst@redhat.com> # gpg: Signature made Tue 05 Jul 2016 11:18:32 BST # gpg: using RSA key 0x281F0DB8D28D5469 # gpg: Good signature from "Michael S. Tsirkin <mst@kernel.org>" # gpg: aka "Michael S. Tsirkin <mst@redhat.com>" # Primary key fingerprint: 0270 606B 6F3C DF3D 0B17 0970 C350 3912 AFBE 8E67 # Subkey fingerprint: 5D09 FD08 71C8 F85B 94CA 8A0D 281F 0DB8 D28D 5469 * remotes/mst/tags/for_upstream: (30 commits) vmw_pvscsi: remove unnecessary internal msi state flag e1000e: remove unnecessary internal msi state flag vmxnet3: remove unnecessary internal msi state flag mptsas: remove unnecessary internal msi state flag megasas: remove unnecessary megasas_use_msi() pci: Convert msi_init() to Error and fix callers to check it pci bridge dev: change msi property type megasas: change msi/msix property type mptsas: change msi property type intel-hda: change msi property type usb xhci: change msi/msix property type change pvscsi_init_msi() type to void tests: add APIC.cphp and DSDT.cphp blobs tests: acpi: add CPU hotplug testcase log: Permit -dfilter 0..0xffffffffffffffff range: Replace internal representation of Range range: Eliminate direct Range member access log: Clean up misuse of Range for -dfilter pci_register_bar: cleanup Revert "virtio-net: unbreak self announcement and guest offloads after migration" ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * | pci: Convert msi_init() to Error and fix callers to check itCao jin2016-07-051-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | msi_init() reports errors with error_report(), which is wrong when it's used in realize(). Fix by converting it to Error. Fix its callers to handle failure instead of ignoring it. For those callers who don't handle the failure, it might happen: when user want msi on, but he doesn't get what he want because of msi_init fails silently. cc: Gerd Hoffmann <kraxel@redhat.com> cc: John Snow <jsnow@redhat.com> cc: Dmitry Fleytman <dmitry@daynix.com> cc: Jason Wang <jasowang@redhat.com> cc: Michael S. Tsirkin <mst@redhat.com> cc: Hannes Reinecke <hare@suse.de> cc: Paolo Bonzini <pbonzini@redhat.com> cc: Alex Williamson <alex.williamson@redhat.com> cc: Markus Armbruster <armbru@redhat.com> cc: Marcel Apfelbaum <marcel@redhat.com> Reviewed-by: Markus Armbruster <armbru@redhat.com> Signed-off-by: Cao jin <caoj.fnst@cn.fujitsu.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com> Reviewed-by: Hannes Reinecke <hare@suse.com>
| * | pc: Eliminate PcPciInfoMarkus Armbruster2016-07-042-6/+1Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | PcPciInfo has two (ill-named) members: Range w32 is the PCI hole, and w64 is the PCI64 hole. Three users: * I440FXState and MCHPCIState have a member PcPciInfo pci_info, but only pci_info.w32 is actually used. This is confusing. Replace by Range pci_hole. * acpi_build() uses auto PcPciInfo pci_info to forward both PCI holes from acpi_get_pci_info() to build_dsdt(). Replace by two variables Range pci_hole, pci_hole64. Rename acpi_get_pci_info() to acpi_get_pci_holes(). PcPciInfo is now unused; drop it. Signed-off-by: Markus Armbruster <armbru@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com> Reviewed-by: Eric Blake <eblake@redhat.com> Reviewed-by: Marcel Apfelbaum <marcel@redhat.com>
| * | machine: remove iommu propertyMarcel Apfelbaum2016-07-041-1/+0Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | Since iommu devices can be created with '-device' there is no need to keep iommu as machine and mch property. Signed-off-by: Marcel Apfelbaum <marcel@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
| * | hw/pci: delay bus_master_enable_region initializationMarcel Apfelbaum2016-07-041-0/+2
| |/ | | | | | | | | | | | | | | | | | | Skip bus_master_enable region creation on PCI device init in order to be sure the IOMMU device (if present) would be created in advance. Add this memory region at machine_done time. Signed-off-by: Marcel Apfelbaum <marcel@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
* | Merge remote-tracking branch 'remotes/kraxel/tags/pull-ipxe-20160704-1' into ↵Peter Maydell2016-07-051-0/+4
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | staging ipxe: update submodule from 4e03af8ec to 041863191 e1000e+vmxnet3: add boot rom # gpg: Signature made Mon 04 Jul 2016 07:25:46 BST # gpg: using RSA key 0x4CB6D8EED3E87138 # gpg: Good signature from "Gerd Hoffmann (work) <kraxel@redhat.com>" # gpg: aka "Gerd Hoffmann <gerd@kraxel.org>" # gpg: aka "Gerd Hoffmann (private) <kraxel@gmail.com>" # Primary key fingerprint: A032 8CFF B93A 17A7 9901 FE7D 4CB6 D8EE D3E8 7138 * remotes/kraxel/tags/pull-ipxe-20160704-1: build: add pc-bios to config-host.mak deps ipxe: add new roms to BLOBS ipxe: update prebuilt binaries vmxnet3: add boot rom e1000e: add boot rom ipxe: add vmxnet3 rom ipxe: add e1000e rom ipxe: update submodule from 4e03af8ec to 041863191 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * | vmxnet3: add boot romGerd Hoffmann2016-06-241-0/+4
| | | | | | | | | | | | | | | | | | Disable for old machine types as this is a guest visible change. Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
* | | spapr_pci/spapr_pci_vfio: Support Dynamic DMA Windows (DDW)Alexey Kardashevskiy2016-07-052-2/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This adds support for Dynamic DMA Windows (DDW) option defined by the SPAPR specification which allows to have additional DMA window(s) The "ddw" property is enabled by default on a PHB but for compatibility the pseries-2.6 machine and older disable it. This also creates a single DMA window for the older machines to maintain backward migration. This implements DDW for PHB with emulated and VFIO devices. The host kernel support is required. The advertised IOMMU page sizes are 4K and 64K; 16M pages are supported but not advertised by default, in order to enable them, the user has to specify "pgsz" property for PHB and enable huge pages for RAM. The existing linux guests try creating one additional huge DMA window with 64K or 16MB pages and map the entire guest RAM to. If succeeded, the guest switches to dma_direct_ops and never calls TCE hypercalls (H_PUT_TCE,...) again. This enables VFIO devices to use the entire RAM and not waste time on map/unmap later. This adds a "dma64_win_addr" property which is a bus address for the 64bit window and by default set to 0x800.0000.0000.0000 as this is what the modern POWER8 hardware uses and this allows having emulated and VFIO devices on the same bus. This adds 4 RTAS handlers: * ibm,query-pe-dma-window * ibm,create-pe-dma-window * ibm,remove-pe-dma-window * ibm,reset-pe-dma-window These are registered from type_init() callback. These RTAS handlers are implemented in a separate file to avoid polluting spapr_iommu.c with PCI. This changes sPAPRPHBState::dma_liobn to an array to allow 2 LIOBNs and updates all references to dma_liobn. However this does not add 64bit LIOBN to the migration stream as in fact even 32bit LIOBN is rather pointless there (as it is a PHB property and the management software can/should pass LIOBNs via CLI) but we keep it for the backward migration support. Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
* | | vfio/spapr: Create DMA window dynamically (SPAPR IOMMU v2)Alexey Kardashevskiy2016-07-051-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | New VFIO_SPAPR_TCE_v2_IOMMU type supports dynamic DMA window management. This adds ability to VFIO common code to dynamically allocate/remove DMA windows in the host kernel when new VFIO container is added/removed. This adds a helper to vfio_listener_region_add which makes VFIO_IOMMU_SPAPR_TCE_CREATE ioctl and adds just created IOMMU into the host IOMMU list; the opposite action is taken in vfio_listener_region_del. When creating a new window, this uses heuristic to decide on the TCE table levels number. This should cause no guest visible change in behavior. Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> [dwg: Added some casts to prevent printf() warnings on certain targets where the kernel headers' __u64 doesn't match uint64_t or PRIx64] Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
* | | vfio: Add host side DMA window capabilitiesAlexey Kardashevskiy2016-07-051-2/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There are going to be multiple IOMMUs per a container. This moves the single host IOMMU parameter set to a list of VFIOHostDMAWindow. This should cause no behavioral change and will be used later by the SPAPR TCE IOMMU v2 which will also add a vfio_host_win_del() helper. Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
* | | vfio: spapr: Add DMA memory preregistering (SPAPR IOMMU v2)Alexey Kardashevskiy2016-07-051-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This makes use of the new "memory registering" feature. The idea is to provide the userspace ability to notify the host kernel about pages which are going to be used for DMA. Having this information, the host kernel can pin them all once per user process, do locked pages accounting (once) and not spent time on doing that in real time with possible failures which cannot be handled nicely in some cases. This adds a prereg memory listener which listens on address_space_memory and notifies a VFIO container about memory which needs to be pinned/unpinned. VFIO MMIO regions (i.e. "skip dump" regions) are skipped. The feature is only enabled for SPAPR IOMMU v2. The host kernel changes are required. Since v2 does not need/support VFIO_IOMMU_ENABLE, this does not call it when v2 is detected and enabled. This enforces guest RAM blocks to be host page size aligned; however this is not new as KVM already requires memory slots to be host page size aligned. Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> [dwg: Fix compile error on 32-bit host] Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
* | | ast2400: add SPI flash slavesCédric Le Goater2016-07-041-0/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Each controller on the ast2400 has a memory range on which it maps its flash module slaves. Each slave is assigned a memory segment for its mapping that can be changed at bootime with the Segment Address Register. This is not supported in the current implementation so we are using the defaults provided by the specs. Each SPI flash slave can then be accessed in two modes: Command and User. When in User mode, accesses to the memory segment of the slaves are translated in SPI transfers. When in Command mode, the HW generates the SPI commands automatically and the memory segment is accessed as if doing a MMIO. Other SPI controllers call that mode linear addressing mode. For this purpose, we are adding below each crontoller an array of structs gathering for each SPI flash module, a segment rank, a MemoryRegion to handle the memory accesses and the associated SPI slave device, which should be a m25p80. Only the User mode is supported for now but we are preparing ground for the Command mode. The framework is sufficient to support Linux. Signed-off-by: Cédric Le Goater <clg@kaod.org> Message-id: 1467138270-32481-8-git-send-email-clg@kaod.org [PMM: Use g_new0() rather than g_malloc0()] Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* | | ast2400: add SMC controllers (FMC and SPI)Cédric Le Goater2016-07-042-0/+82
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Aspeed AST2400 soc includes a static memory controller for the BMC which supports NOR, NAND and SPI flash memory modules. This controller has two modes : the SMC for the legacy interface which supports only one module and the FMC for the new interface which supports up to five modules. The AST2400 also includes a SPI only controller used for the host firmware, commonly called BIOS on Intel. It can be used in three mode : a SPI master, SPI slave and SPI pass-through Below is the initial framework for the SMC controller (FMC mode only) and the SPI controller: the sysbus object, MMIO for registers configuration and controls. Each controller has a SPI bus and a configurable number of CS lines for SPI flash slaves. The differences between the controllers are small, so they are abstracted using indirections on the register numbers. Only SPI flash modules are supported. Signed-off-by: Cédric Le Goater <clg@kaod.org> Message-id: 1467138270-32481-7-git-send-email-clg@kaod.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> [PMM: added one missing error_propagate] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* | | ssi: change ssi_slave_init to be a realize opsCédric Le Goater2016-07-041-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This enables qemu to handle late inits and report errors. All the SSI slave routine names were changed accordingly. Code was modified to handle errors when possible (m25p80 and ssi-sd) Tested with the m25p80 slave object. Suggested-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Cédric Le Goater <clg@kaod.org> Message-id: 1467138270-32481-2-git-send-email-clg@kaod.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* | | dma: Add Xilinx Zynq devcfg device modelAlistair Francis2016-07-041-0/+62
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add a minimal model for the devcfg device which is part of Zynq. This model supports DMA capabilities and interrupt generation. Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Signed-off-by: Alistair Francis <alistair.francis@xilinx.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 83df49d8fa2d203a421ca71620809e4b04754e65.1467053537.git.alistair.francis@xilinx.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* | | register: Add block initialise helperPeter Crosthwaite2016-07-041-0/+40
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add a helper that will scan a static RegisterAccessInfo Array and populate a container MemoryRegion with registers as defined. Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Signed-off-by: Alistair Francis <alistair.francis@xilinx.com> Message-id: 347b810b2799e413c98d5bbeca97bcb1557946c3.1467053537.git.alistair.francis@xilinx.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* | | register: QOMifyPeter Crosthwaite2016-07-041-0/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | QOMify registers as a child of TYPE_DEVICE. This allows registers to define GPIOs. Define an init helper that will do QOM initialisation. Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Signed-off-by: Alistair Francis <alistair.francis@xilinx.com> Reviewed-by: KONRAD Frederic <fred.konrad@greensocs.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 2545f71db26bf5586ca0c08a3e3cf1b217450552.1467053537.git.alistair.francis@xilinx.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* | | register: Define REG and FIELD macrosPeter Crosthwaite2016-07-041-0/+46
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Define some macros that can be used for defining registers and fields. The REG32 macro will define A_FOO, for the byte address of a register as well as R_FOO for the uint32_t[] register number (A_FOO / 4). The FIELD macro will define FOO_BAR_MASK, FOO_BAR_SHIFT and FOO_BAR_LENGTH constants for field BAR in register FOO. Finally, there are some shorthand helpers for extracting/depositing fields from registers based on these naming schemes. Usage can greatly reduce the verbosity of device code. The deposit and extract macros (eg FIELD_EX32, FIELD_DP32 etc.) can be used to generate extract and deposits without any repetition of the name stems. Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Alistair Francis <alistair.francis@xilinx.com> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Message-id: bbd87a3c03b1f173b1ed73a6d502c0196c18a72f.1467053537.git.alistair.francis@xilinx.com [ EI Changes: * Add Deposit macros ] Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Signed-off-by: Alistair Francis <alistair.francis@xilinx.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* | | register: Add Memory API glueAlistair Francis2016-07-041-0/+43
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add memory io handlers that glue the register API to the memory API. Just translation functions at this stage. Although it does allow for devices to be created without all-in-one mmio r/w handlers. This patch also adds the RegisterInfoArray struct, which allows all of the individual RegisterInfo structs to be grouped into a single memory region. Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Signed-off-by: Alistair Francis <alistair.francis@xilinx.com> Message-id: f7704d8ac6ac0f469ed35401f8151a38bd01468b.1467053537.git.alistair.francis@xilinx.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* | | register: Add Register APIAlistair Francis2016-07-041-0/+112
| |/ |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This API provides some encapsulation of registers and factors out some common functionality to common code. Bits of device state (usually MMIO registers) often have all sorts of access restrictions and semantics associated with them. This API allows you to define what those restrictions are on a bit-by-bit basis. Helper functions are then used to access the register which observe the semantics defined by the RegisterAccessInfo struct. Some features: Bits can be marked as read_only (ro field) Bits can be marked as write-1-clear (w1c field) Bits can be marked as reserved (rsvd field) Reset values can be defined (reset) Bits can be marked clear on read (cor) Pre and post action callbacks can be added to read and write ops Verbose debugging info can be enabled/disabled Useful for defining device register spaces in a data driven way. Cuts down on a lot of the verbosity and repetition in the switch-case blocks in the standard foo_mmio_read/write functions. Also useful for automated generation of device models from hardware design sources. Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Signed-off-by: Alistair Francis <alistair.francis@xilinx.com> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 40d62c7e1bf6e63bb4193ec46b15092a7d981e59.1467053537.git.alistair.francis@xilinx.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* | ppc/xics: Replace "icp" with "xics" in most placesBenjamin Herrenschmidt2016-07-014-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The "ICP" is a different object than the "XICS". For historical reasons, we have a number of places where we name a variable "icp" while it contains a XICSState pointer. There *is* an ICPState structure too so this makes the code really confusing. This is a mechanical replacement of all those instances to use the name "xics" instead. There should be no functional change. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> [spapr_cpu_init has been moved to spapr_cpu_core.c, change there] Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
* | ppc/xics: Implement H_IPOLL using an accessorBenjamin Herrenschmidt2016-07-011-0/+1
| | | | | | | | | | | | | | | | | | | | None of the other presenter functions directly mucks with the internal state, so don't do it there either. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
* | ppc/xics: Move SPAPR specific code to a separate fileBenjamin Herrenschmidt2016-07-011-0/+21
| | | | | | | | | | | | | | | | | | | | | | Leave the core ICP/ICS logic in xics.c and move the top level class wrapper, hypercall and RTAS handlers to xics_spapr.c Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> [add cpu.h in xics_spapr.c, move set_nr_irqs and set_nr_servers to xics_spapr.c] Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
* | ppc/xics: Rename existing xics to xics_spaprBenjamin Herrenschmidt2016-07-011-12/+18
| | | | | | | | | | | | | | | | | | | | | | | | The common class doesn't change, the KVM one is sPAPR specific. Rename variables and functions to xics_spapr. Retain the type name as "xics" to preserve migration for existing sPAPR guests. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
* | pcspk: fix KVMPaolo Bonzini2016-06-302-8/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The link property that was added to the pcspk device has the wrong type: it is only correct for TCG and for KVM's userspace or split irqchip options. The default KVM option (fully in-kernel irqchip) breaks because it uses a PIT whose type is a sibling of TYPE_I8254. Fixes: 873b4d3f0571a1e415cf089a67a230ea8a12d059 Tested-by: Peter Lieven <pl@kamp.de> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Message-id: 1467298657-6588-1-git-send-email-pbonzini@redhat.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* | Merge remote-tracking branch 'remotes/bonzini/tags/for-upstream' into stagingPeter Maydell2016-06-2910-7/+1143
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * serial port fixes (Paolo) * Q35 modeling improvements (Paolo, Vasily) * chardev cleanup improvements (Marc-André) * iscsi bugfix (Peter L.) * cpu_exec patch from multi-arch patches (Peter C.) * pci-assign tweak (Lin Ma) # gpg: Signature made Wed 29 Jun 2016 15:56:30 BST # gpg: using RSA key 0xBFFBD25F78C7AE83 # gpg: Good signature from "Paolo Bonzini <bonzini@gnu.org>" # gpg: aka "Paolo Bonzini <pbonzini@redhat.com>" # Primary key fingerprint: 46F5 9FBD 57D6 12E7 BFD4 E2F7 7E15 100C CD36 69B1 # Subkey fingerprint: F133 3857 4B66 2389 866C 7682 BFFB D25F 78C7 AE83 * remotes/bonzini/tags/for-upstream: (35 commits) socket: unlink unix socket on remove socket: add listen feature char: clean up remaining chardevs when leaving vhost-user: disable chardev handlers on close vhost-user-test: fix g_cond_wait_until compat implementation vl: smp_parse: fix regression ich9: implement SCI_IRQ_SEL register ich9: implement ACPI_EN register serial: reinstate watch after migration serial: remove watch on reset char: change qemu_chr_fe_add_watch to return unsigned serial: separate serial_xmit and serial_watch_cb serial: simplify tsr_retry reset serial: make tsr_retry unsigned iscsi: fix assertion in is_sector_request_lun_aligned target-*: Don't redefine cpu_exec() pci-assign: Move "Invalid ROM" error message to pci-assign-load-rom.c vnc: generalize "VNC server running on ..." message scsi: esp: fix migration MC146818 RTC: add GPIO access to output IRQ ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * | ich9: implement SCI_IRQ_SEL registerPaolo Bonzini2016-06-291-0/+1
| | | | | | | | | | | | Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
| * | serial: remove watch on resetPaolo Bonzini2016-06-291-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Otherwise, this can cause serial_xmit to be entered with LSR.TEMT=0, which is invalid and causes an assertion failure. Reported-by: Bret Ketchum <bcketchum@gmail.com> Tested-by: Bret Ketchum <bcketchum@gmail.com> Reviewed-by: Dr. David Alan Gilbert <dgilbert@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
| * | serial: make tsr_retry unsignedPaolo Bonzini2016-06-291-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | It can never become negative; reflect this in the type of the field and simplify the conditions. Tested-by: Bret Ketchum <bcketchum@gmail.com> Reviewed-by: Dr. David Alan Gilbert <dgilbert@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
| * | isa: introduce wrapper isa_connect_gpio_outEfimov Vasily2016-06-291-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently a direct access to the device structure field is used to connect ISA device IRQ to the bus. GPIO access should be used instead if possible. The patch adds wrapper isa_connect_gpio_out. The function connects specified output GPIO to specified ISA IRQ. Signed-off-by: Efimov Vasily <real@ispras.ru> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
| * | ICH9 LPC: handle GSI as qdev GPIOEfimov Vasily2016-06-291-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The ICH9 LPC bridge has 24 output IRQs connected to GSI. Currently the IRQs are referenced by pointers. The pointers are initialized at startup by direct access to the structure fields. This violates Qemu device model. The patch makes the IRQs handling to use GPIO model. Signed-off-by: Efimov Vasily <real@ispras.ru> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
generated by cgit v1.2.3-55-g7522 (git 2.39.0) at 2025-01-10 06:58:10 +0100