summaryrefslogtreecommitdiffstats
path: root/include
Commit message (Collapse)AuthorAgeFilesLines
...
| * qapi: Eliminate QCO_NO_OPTIONS for a slight simplificationMarkus Armbruster2021-10-291-1/+0Star
| | | | | | | | | | | | | | Signed-off-by: Markus Armbruster <armbru@redhat.com> Reviewed-by: Juan Quintela <quintela@redhat.com> Reviewed-by: John Snow <jsnow@redhat.com> Message-Id: <20211028102520.747396-4-armbru@redhat.com>
* | Merge remote-tracking branch ↵Richard Henderson2021-10-295-3/+12
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 'remotes/alistair23/tags/pull-riscv-to-apply-20211029-1' into staging Fifth RISC-V PR for QEMU 6.2 - Use a shared PLIC config helper function - Fixup the OpenTitan PLIC configuration - Add support for the experimental J extension - Update the fmin/fmax handling - Fixup VS interrupt forwarding # gpg: Signature made Fri 29 Oct 2021 12:03:47 AM PDT # gpg: using RSA key F6C4AC46D4934868D3B8CE8F21E10D29DF977054 # gpg: Good signature from "Alistair Francis <alistair@alistair23.me>" [full] * remotes/alistair23/tags/pull-riscv-to-apply-20211029-1: target/riscv: change the api for RVF/RVD fmin/fmax softfloat: add APIs to handle alternative sNaN propagation for fmax/fmin target/riscv: remove force HS exception target/riscv: fix VS interrupts forwarding to HS target/riscv: Allow experimental J-ext to be turned on target/riscv: Implement address masking functions required for RISC-V Pointer Masking extension target/riscv: Support pointer masking for RISC-V for i/c/f/d/a types of instructions target/riscv: Print new PM CSRs in QEMU logs target/riscv: Add J extension state description target/riscv: Support CSRs required for RISC-V PM extension except for the h-mode target/riscv: Add CSR defines for RISC-V PM extension target/riscv: Add J-extension into RISC-V hw/riscv: opentitan: Fixup the PLIC context addresses hw/riscv: virt: Use the PLIC config helper function hw/riscv: microchip_pfsoc: Use the PLIC config helper function hw/riscv: sifive_u: Use the PLIC config helper function hw/riscv: boot: Add a PLIC config string function hw/riscv: virt: Don't use a macro for the PLIC configuration Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * | softfloat: add APIs to handle alternative sNaN propagation for fmax/fminChih-Min Chao2021-10-291-0/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For "fmax/fmin ft0, ft1, ft2" and if one of the inputs is sNaN, The original logic: Return NaN and set invalid flag if ft1 == sNaN || ft2 == sNan. The alternative path: Set invalid flag if ft1 == sNaN || ft2 == sNaN. Return NaN only if ft1 == NaN && ft2 == NaN. The IEEE 754 spec allows both implementation and some architecture such as riscv choose different defintions in two spec versions. (riscv-spec-v2.2 use original version, riscv-spec-20191213 changes to alternative) Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com> Signed-off-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20211021160847.2748577-2-frank.chang@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
| * | hw/riscv: microchip_pfsoc: Use the PLIC config helper functionAlistair Francis2021-10-281-1/+0Star
| | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> Message-id: 20211022060133.3045020-4-alistair.francis@opensource.wdc.com
| * | hw/riscv: sifive_u: Use the PLIC config helper functionAlistair Francis2021-10-281-1/+0Star
| | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> Message-id: 20211022060133.3045020-3-alistair.francis@opensource.wdc.com
| * | hw/riscv: boot: Add a PLIC config string functionAlistair Francis2021-10-281-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | Add a generic function that can create the PLIC strings. Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Message-id: 20211022060133.3045020-2-alistair.francis@opensource.wdc.com
| * | hw/riscv: virt: Don't use a macro for the PLIC configurationAlistair Francis2021-10-281-1/+0Star
| |/ | | | | | | | | | | | | | | | | | | | | Using a macro for the PLIC configuration doesn't make the code any easier to read. Instead it makes it harder to figure out what is going on, so let's remove it. Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-id: 20211022060133.3045020-1-alistair.francis@opensource.wdc.com
* | host-utils: add 128-bit quotient support to divu128/divs128Luis Pires2021-10-282-12/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | These will be used to implement new decimal floating point instructions from Power ISA 3.1. The remainder is now returned directly by divu128/divs128, freeing up phigh to receive the high 64 bits of the quotient. Signed-off-by: Luis Pires <luis.pires@eldorado.org.br> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20211025191154.350831-4-luis.pires@eldorado.org.br> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* | host-utils: move udiv_qrnnd() to host-utilsLuis Pires2021-10-282-82/+81Star
| | | | | | | | | | | | | | | | | | | | Move udiv_qrnnd() from include/fpu/softfloat-macros.h to host-utils, so it can be reused by divu128(). Signed-off-by: Luis Pires <luis.pires@eldorado.org.br> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20211025191154.350831-3-luis.pires@eldorado.org.br> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* | host-utils: move checks out of divu128/divs128Luis Pires2021-10-282-25/+16Star
| | | | | | | | | | | | | | | | | | | | | | In preparation for changing the divu128/divs128 implementations to allow for quotients larger than 64 bits, move the div-by-zero and overflow checks to the callers. Signed-off-by: Luis Pires <luis.pires@eldorado.org.br> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20211025191154.350831-2-luis.pires@eldorado.org.br> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* | qemu/int128: Add int128_{not,xor}Frédéric Pétrot2021-10-281-0/+20
|/ | | | | | | | | | | Addition of not and xor on 128-bit integers. Signed-off-by: Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr> Co-authored-by: Fabien Portas <fabien.portas@grenoble-inp.org> Message-Id: <20211025122818.168890-3-frederic.petrot@univ-grenoble-alpes.fr> [rth: Split out logical operations.] Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* qapi: Implement deprecated-input={reject,crash} for enum valuesMarkus Armbruster2021-10-271-1/+5
| | | | | | | | | | | | This copies the code implementing the policy from qapi/qmp-dispatch.c to qapi/qobject-input-visitor.c. Tolerable, but if we acquire more copies, we should look into factoring them out. Signed-off-by: Markus Armbruster <armbru@redhat.com> Reviewed-by: Eric Blake <eblake@redhat.com> Tested-by: Peter Krempa <pkrempa@redhat.com> Acked-by: Peter Krempa <pkrempa@redhat.com> Message-Id: <20211025042405.3762351-5-armbru@redhat.com>
* qapi: Move compat policy from QObject to generic visitorMarkus Armbruster2021-10-274-8/+12
| | | | | | | | | The next commit needs to access compat policy from the generic visitor core. Move it there from qobject input and output visitor. Signed-off-by: Markus Armbruster <armbru@redhat.com> Reviewed-by: Eric Blake <eblake@redhat.com> Message-Id: <20211025042405.3762351-4-armbru@redhat.com>
* Merge remote-tracking branch ↵Richard Henderson2021-10-231-2/+1Star
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 'remotes/vivier/tags/trivial-branch-for-6.2-pull-request' into staging Trivial patches pull request 20211023 # gpg: Signature made Sat 23 Oct 2021 11:30:42 AM PDT # gpg: using RSA key CD2F75DDC8E3A4DC2E4F5173F30C38BD3F2FBE3C # gpg: issuer "laurent@vivier.eu" # gpg: Good signature from "Laurent Vivier <lvivier@redhat.com>" [full] # gpg: aka "Laurent Vivier <laurent@vivier.eu>" [full] # gpg: aka "Laurent Vivier (Red Hat) <lvivier@redhat.com>" [full] * remotes/vivier/tags/trivial-branch-for-6.2-pull-request: analyze-migration.py: fix extract contents ('-x') errors analyze-migration.py: fix a long standing typo README: Fix some documentation URLs hw/nvram: Fix Memory Leak in Xilinx ZynqMP eFuse device hw/nvram: Fix Memory Leak in Xilinx Versal eFuse device hw/nvram: Fix Memory Leak in Xilinx eFuse QOM softmmu/physmem.c: Fix typo in comment MAINTAINERS: Add myself as reviewer of 'Machine core' API disas/nios2: Simplify endianess conversion disas/nios2: Fix style in print_insn_nios2() po: update turkish translation Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * disas/nios2: Simplify endianess conversionPhilippe Mathieu-Daudé2021-10-221-2/+1Star
| | | | | | | | | | | | | | | | | | | | | | | | Since commit 12b6e9b27d4 ("disas: Clean up CPUDebug initialization") the disassemble_info->bfd_endian enum is set for all targets in target_disas(). We can directly call print_insn_nios2() and simplify. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Thomas Huth <thuth@redhat.com> Message-Id: <20210807110939.95853-3-f4bug@amsat.org> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
* | Merge remote-tracking branch ↵Richard Henderson2021-10-221-3/+3
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 'remotes/alistair23/tags/pull-riscv-to-apply-20211022-2' into staging Fourth RISC-V PR for QEMU 6.2 - Vector extension bug fixes - Bit manipulation extension bug fix - Support vhost-user and numa mem options on all boards - Rationalise XLEN and operand lengths - Bump the OpenTitan FPGA support - Remove the Ibex PLIC - General code cleanup # gpg: Signature made Fri 22 Oct 2021 06:36:10 AM PDT # gpg: using RSA key F6C4AC46D4934868D3B8CE8F21E10D29DF977054 # gpg: Good signature from "Alistair Francis <alistair@alistair23.me>" [full] * remotes/alistair23/tags/pull-riscv-to-apply-20211022-2: (33 commits) hw/riscv: spike: Use MachineState::ram and MachineClass::default_ram_id hw/riscv: sifive_u: Use MachineState::ram and MachineClass::default_ram_id hw/riscv: sifive_e: Use MachineState::ram and MachineClass::default_ram_id hw/riscv: shakti_c: Use MachineState::ram and MachineClass::default_ram_id hw/riscv: opentitan: Use MachineState::ram and MachineClass::default_ram_id hw/riscv: microchip_pfsoc: Use MachineState::ram and MachineClass::default_ram_id hw/intc: sifive_plic: Cleanup the irq_request function hw/intc: sifive_plic: Cleanup the realize function hw/intc: sifive_plic: Move the properties hw/intc: Remove the Ibex PLIC hw/riscv: opentitan: Update to the latest build target/riscv: Compute mstatus.sd on demand target/riscv: Use riscv_csrrw_debug for cpu_dump target/riscv: Use gen_shift*_per_ol for RVB, RVI target/riscv: Use gen_unary_per_ol for RVB target/riscv: Adjust trans_rev8_32 for riscv64 target/riscv: Use gen_arith_per_ol for RVM target/riscv: Replace DisasContext.w with DisasContext.ol target/riscv: Replace is_32bit with get_xl/get_xlen target/riscv: Properly check SEW in amo_op ... Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * | hw/riscv: opentitan: Update to the latest buildAlistair Francis2021-10-221-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | Update the OpenTitan machine model to match the latest OpenTitan FPGA design. Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Message-id: 18b1b681b0f8dd2461e819d1217bf0b530812680.1634524691.git.alistair.francis@wdc.com
* | | Merge remote-tracking branch 'remotes/clg/tags/pull-aspeed-20211022' into ↵Richard Henderson2021-10-221-1/+1
|\ \ \ | |_|/ |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | staging Aspeed patches : * New fp5280g2-bmc board (John) * Small cleanup in Aspeed SMC model (Cedric) # gpg: Signature made Fri 22 Oct 2021 12:55:18 AM PDT # gpg: using RSA key A0F66548F04895EBFE6B0B6051A343C7CFFBECA1 # gpg: Good signature from "Cédric Le Goater <clg@kaod.org>" [marginal] # gpg: WARNING: This key is not certified with sufficiently trusted signatures! # gpg: It is not certain that the signature belongs to the owner. # Primary key fingerprint: A0F6 6548 F048 95EB FE6B 0B60 51A3 43C7 CFFB ECA1 * remotes/clg/tags/pull-aspeed-20211022: speed/sdhci: Add trace events aspeed/smc: Use a container for the flash mmio address space aspeed: Add support for the fp5280g2-bmc board Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * | aspeed/smc: Use a container for the flash mmio address spaceCédric Le Goater2021-10-221-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Because AddressSpaces must not be sysbus-mapped, commit e9c568dbc225 ("hw/arm/aspeed: Do not sysbus-map mmio flash region directly, use alias") introduced an alias for the flash mmio region. Using a container is cleaner. Cc: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Francisco Iglesias <frasse.iglesias@gmail.com> Message-Id: <20211018132609.160008-5-clg@kaod.org> Signed-off-by: Cédric Le Goater <clg@kaod.org>
* | | Merge remote-tracking branch 'remotes/vivier-m68k/tags/q800-pull-request' ↵Richard Henderson2021-10-221-0/+1
|\ \ \ | |_|/ |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | into staging Pull request Q800 20211022 GLUE updates for A/UX mode # gpg: Signature made Fri 22 Oct 2021 12:16:29 AM PDT # gpg: using RSA key CD2F75DDC8E3A4DC2E4F5173F30C38BD3F2FBE3C # gpg: issuer "laurent@vivier.eu" # gpg: Good signature from "Laurent Vivier <lvivier@redhat.com>" [full] # gpg: aka "Laurent Vivier <laurent@vivier.eu>" [full] # gpg: aka "Laurent Vivier (Red Hat) <lvivier@redhat.com>" [full] * remotes/vivier-m68k/tags/q800-pull-request: q800: drop 8-bit graphic_depth check for Apple 21 inch display q800: add NMI handler q800: wire up remaining IRQs in classic mode q800: route SONIC on-board Ethernet IRQ via nubus IRQ 9 in classic mode q800: wire up auxmode GPIO to GLUE mac_via: add GPIO for A/UX mode q800: use GLUE IRQ numbers instead of IRQ level for GLUE IRQs q800: move VIA1 IRQ from level 1 to level 6 mac_via: update comment for VIA1B_vMystery bit Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * | mac_via: add GPIO for A/UX modeMark Cave-Ayland2021-10-201-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add a new auxmode GPIO that is updated when port B bit 6 is changed indicating whether the hardware is configured for A/UX mode. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Message-Id: <20211020134131.4392-5-mark.cave-ayland@ilande.co.uk> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
* | | Merge remote-tracking branch 'remotes/rth/tags/pull-arm-20211021' into stagingRichard Henderson2021-10-215-43/+50
|\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Introduce cpu topology support Generate DBG2 table Switch to ssize_t for elf loader return type Fixed sbsa cpu type error message typo Only initialize required submodules for edk2 Dont create device-tree node for empty NUMA node # gpg: Signature made Thu 21 Oct 2021 08:22:32 AM PDT # gpg: using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E215F # gpg: issuer "richard.henderson@linaro.org" # gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" [ultimate] * remotes/rth/tags/pull-arm-20211021: tests/data/acpi/virt: Update the empty expected file for PPTT hw/arm/virt-acpi-build: Generate PPTT table tests/data/acpi/virt: Add an empty expected file for PPTT hw/acpi/aml-build: Add PPTT table hw/acpi/aml-build: Add Processor hierarchy node structure hw/arm/virt: Add cpu-map to device tree device_tree: Add qemu_fdt_add_path hw/arm/virt: Only describe cpu topology since virt-6.2 bios-tables-test: Generate reference table for virt/DBG2 hw/arm/virt_acpi_build: Generate DBG2 table tests/acpi: Add void table for virt/DBG2 bios-tables-test hw/elf_ops.h: switch to ssize_t for elf loader return type hw/arm/sbsa-ref: Fixed cpu type error message typo. roms/edk2: Only initialize required submodules roms/edk2: Only init brotli submodule to build BaseTools hw/arm/virt: Don't create device-tree node for empty NUMA node tests/acpi: Generate reference blob for IORT rev E.b hw/arm/virt-acpi-build: IORT upgrade up to revision E.b tests/acpi: Get prepared for IORT E.b revision upgrade Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * | | hw/acpi/aml-build: Add PPTT tableAndrew Jones2021-10-211-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add the Processor Properties Topology Table (PPTT) used to describe CPU topology information to ACPI guests. Note, a DT-boot Linux guest with a non-flat CPU topology will see socket and core IDs being sequential integers starting from zero, which is different from ACPI-boot Linux guest, e.g. with -smp 4,sockets=2,cores=2,threads=1 a DT boot produces: cpu: 0 package_id: 0 core_id: 0 cpu: 1 package_id: 0 core_id: 1 cpu: 2 package_id: 1 core_id: 0 cpu: 3 package_id: 1 core_id: 1 an ACPI boot produces: cpu: 0 package_id: 36 core_id: 0 cpu: 1 package_id: 36 core_id: 1 cpu: 2 package_id: 96 core_id: 2 cpu: 3 package_id: 96 core_id: 3 This is due to several reasons: 1) DT cpu nodes do not have an equivalent field to what the PPTT ACPI Processor ID must be, i.e. something equal to the MADT CPU UID or equal to the UID of an ACPI processor container. In both ACPI cases those are platform dependant IDs assigned by the vendor. 2) While QEMU is the vendor for a guest, if the topology specifies SMT (> 1 thread), then, with ACPI, it is impossible to assign a core-id the same value as a package-id, thus it is not possible to have package-id=0 and core-id=0. This is because package and core containers must be in the same ACPI namespace and therefore must have unique UIDs. 3) ACPI processor containers are not mandatorily required for PPTT tables to be used and, due to the limitations of which IDs are selected described above in (2), they are not helpful for QEMU, so we don't build them with this patch. In the absence of them, Linux assigns its own unique IDs. The maintainers have chosen not to use counters from zero, but rather ACPI table offsets, which explains why the numbers are so much larger than with DT. 4) When there is no SMT (threads=1) the core IDs for ACPI boot guests match the logical CPU IDs, because these IDs must be equal to the MADT CPU UID (as no processor containers are present), and QEMU uses the logical CPU ID for these MADT IDs. So in summary, with QEMU as the vendor for the guests, we simply use sequential integers starting from zero for the non-leaf nodes but with ID-valid flag unset, so that guest will ignore them and use table offsets as unique container IDs. And we use logical CPU IDs for the leaf nodes with the ID-valid flag set, which will be consistent with MADT. Currently the implementation of PPTT generation complies with ACPI specification 5.2.29 (Revision 6.3). The 6.3 spec can be found at: https://uefi.org/sites/default/files/resources/ACPI_6_3_May16.pdf Reviewed-by: Eric Auger <eric.auger@redhat.com> Co-developed-by: Yanan Wang <wangyanan55@huawei.com> Signed-off-by: Andrew Jones <drjones@redhat.com> Signed-off-by: Yanan Wang <wangyanan55@huawei.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Message-Id: <20211020142125.7516-6-wangyanan55@huawei.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * | | device_tree: Add qemu_fdt_add_pathYanan Wang2021-10-211-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | qemu_fdt_add_path() works like qemu_fdt_add_subnode(), except it also adds all missing subnodes from the given path. We'll use it in a coming patch where we will add cpu-map to the device tree. And we also tweak an error message of qemu_fdt_add_subnode(). Co-developed-by: Andrew Jones <drjones@redhat.com> Signed-off-by: Yanan Wang <wangyanan55@huawei.com> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Reviewed-by: Andrew Jones <drjones@redhat.com> Cc: David Gibson <david@gibson.dropbear.id.au> Cc: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20211020142125.7516-3-wangyanan55@huawei.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * | | hw/arm/virt: Only describe cpu topology since virt-6.2Yanan Wang2021-10-211-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On existing older machine types, without cpu topology described in ACPI or DT, the guest will populate one by default. With the topology described, it will read the information and set up its topology as instructed, but that may not be the same as what was getting used by default. It's possible that an user application has a dependency on the default topology and if the default one gets changed it will probably behave differently. Based on above consideration we'd better only describe topology information to the guest on 6.2 and later machine types. Signed-off-by: Yanan Wang <wangyanan55@huawei.com> Reviewed-by: Andrew Jones <drjones@redhat.com> Message-Id: <20211020142125.7516-2-wangyanan55@huawei.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * | | hw/elf_ops.h: switch to ssize_t for elf loader return typeLuc Michel2021-10-212-42/+43
| | |/ | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Until now, int was used as the return type for all the ELF loader related functions. The returned value is the sum of all loaded program headers "MemSize" fields. Because of the overflow check in elf_ops.h, trying to load an ELF bigger than INT_MAX will fail. Switch to ssize_t to remove this limitation. Signed-off-by: Luc Michel <lmichel@kalray.eu> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Stefano Garzarella <sgarzare@redhat.com> Message-Id: <20211014194325.19917-1-lmichel@kalray.eu> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* / | spapr/xive: Add source status helpersCédric Le Goater2021-10-211-0/+24
|/ / | | | | | | | | | | | | | | and use them to set and test the ASSERTED bit of LSI sources. Signed-off-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20211004212141.432954-1-clg@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
* | virtio-net: vhost control virtqueue supportJason Wang2021-10-201-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | This patch implements the control virtqueue support for vhost. This requires virtio-net to figure out the datapath queue pairs and control virtqueue via is_datapath and pass the number of those two types of virtqueues to vhost_net_start()/vhost_net_stop(). Signed-off-by: Jason Wang <jasowang@redhat.com> Message-Id: <20211020045600.16082-10-jasowang@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
* | vhost: record the last virtqueue index for the virtio deviceJason Wang2021-10-201-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | This patch introduces a new field in the vhost_dev structure to record the last virtqueue index for the virtio device. This will be useful for the vhost backends with 1:N model to start or stop the device after all the vhost_dev structures were started or stopped. Signed-off-by: Jason Wang <jasowang@redhat.com> Message-Id: <20211020045600.16082-9-jasowang@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
* | virtio-net: use "queue_pairs" instead of "queues" when possibleJason Wang2021-10-201-2/+2
| | | | | | | | | | | | | | | | | | | | Most of the time, "queues" really means queue pairs. So this patch switch to use "queue_pairs" to avoid confusion. Signed-off-by: Jason Wang <jasowang@redhat.com> Message-Id: <20211020045600.16082-8-jasowang@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
* | vhost-net: control virtqueue supportJason Wang2021-10-201-2/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We assume there's no cvq in the past, this is not true when we need control virtqueue support for vhost-user backends. So this patch implements the control virtqueue support for vhost-net. As datapath, the control virtqueue is also required to be coupled with the NetClientState. The vhost_net_start/stop() are tweaked to accept the number of datapath queue pairs plus the the number of control virtqueue for us to start and stop the vhost device. Signed-off-by: Jason Wang <jasowang@redhat.com> Message-Id: <20211020045600.16082-7-jasowang@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
* | net: introduce control clientJason Wang2021-10-201-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | This patch introduces a boolean for the device has control queue which can accepts control command via network queue. The first user would be the control virtqueue support for vhost. Signed-off-by: Jason Wang <jasowang@redhat.com> Message-Id: <20211020045600.16082-6-jasowang@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
* | vhost-vdpa: classify one time requestJason Wang2021-10-201-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | Vhost-vdpa uses one device multiqueue queue (pairs) model. So we need to classify the one time request (e.g SET_OWNER) and make sure those request were only called once per device. This is used for multiqueue support. Signed-off-by: Jason Wang <jasowang@redhat.com> Message-Id: <20211020045600.16082-3-jasowang@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
* | vhost-user-rng: Add vhost-user-rng implementationMathieu Poirier2021-10-201-0/+33
| | | | | | | | | | | | | | | | | | | | | | | | | | Introduce a random number generator (RNG) backend that communicates with a vhost-user server to retrieve entropy. That way other VMM that comply with the vhost user protocl can use the same vhost-user daemon without having to write yet another RNG driver. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org> Message-Id: <20211012205904.4106769-2-mathieu.poirier@linaro.org> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
* | virtio-iommu: Drop base_name and change generic_nameEric Auger2021-10-201-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Drop base_name and turn generic_name into "virtio-iommu-pci". This is more in line with other modern-only devices. Signed-off-by: Eric Auger <eric.auger@redhat.com> Suggested-by: Cornelia Huck <cohuck@redhat.com> Reviewed-by: Cornelia Huck <cohuck@redhat.com> Message-Id: <20211013191755.767468-3-eric.auger@redhat.com> Reviewed-by: Jean-Philippe Brucker <jean-philippe@linaro.org> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
* | vdpa: Check for iova range at mappings changesEugenio Pérez2021-10-201-0/+2
|/ | | | | | | | | | | | Check vdpa device range before updating memory regions so we don't add any outside of it, and report the invalid change if any. Signed-off-by: Eugenio Pérez <eperezma@redhat.com> Message-Id: <20211014141236.923287-4-eperezma@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com> Acked-by: Jason Wang <jasowang@redhat.com> Reviewed-by: Stefano Garzarella <sgarzare@redhat.com>
* vt82c686: Add a method to VIA_ISA to raise ISA interruptsBALATON Zoltan2021-10-181-0/+4
| | | | | | | | | | | | Other functions in the VT82xx chips need to raise ISA interrupts. Keep a reference to them in the device state and add via_isa_set_irq() to allow setting their state. Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Message-Id: <778c04dc2c8affac060b8edf9e8d7dab3c3e04eb.1634259980.git.balaton@eik.bme.hu> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
* Revert "cpu: Move cpu_common_props to hw/core/cpu.c"Richard Henderson2021-10-161-0/+1
| | | | | | | | | | | | | | | This reverts commit 1b36e4f5a5de585210ea95f2257839c2312be28f. Despite a comment saying why cpu_common_props cannot be placed in a file that is compiled once, it was moved anyway. Revert that. Since then, Property is not defined in hw/core/cpu.h, so it is now easier to declare a function to install the properties rather than the Property array itself. Cc: Eduardo Habkost <ehabkost@redhat.com> Suggested-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* block-backend: update blk_co_pwrite() and blk_co_pread() wrappersVladimir Sementsov-Ogievskiy2021-10-151-2/+6
| | | | | | | | | | | | | | | | | | | | Make bytes argument int64_t to be consistent with modern block-layer. Callers should be OK with it as type becomes wider. What is inside functions? - Conversion from int64_t to size_t. Still, we can't have a buffer larger than SIZE_MAX, therefore bytes should not be larger than SIZE_MAX as well. Add an assertion. - Passing to blk_co_pwritev() / blk_co_preadv() which already has int64_t bytes argument. Signed-off-by: Vladimir Sementsov-Ogievskiy <vsementsov@virtuozzo.com> Message-Id: <20211007175243.642516-2-vsementsov@virtuozzo.com> Reviewed-by: Eric Blake <eblake@redhat.com> [eblake: spelling fix] Signed-off-by: Eric Blake <eblake@redhat.com>
* block-backend: fix blk_co_flush prototype to mention coroutine_fnVladimir Sementsov-Ogievskiy2021-10-151-1/+1
| | | | | | | | | | | We already have this marker for the blk_co_flush function declaration in block/block-backend.c. Add it in the header too. Signed-off-by: Vladimir Sementsov-Ogievskiy <vsementsov@virtuozzo.com> Message-Id: <20211007175243.642516-1-vsementsov@virtuozzo.com> Reviewed-by: Eric Blake <eblake@redhat.com> [eblake: wording tweak] Signed-off-by: Eric Blake <eblake@redhat.com>
* block-backend: convert blk_aio_ functions to int64_t bytes paramterVladimir Sementsov-Ogievskiy2021-10-151-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | 1. Convert bytes in BlkAioEmAIOCB: aio->bytes is only passed to already int64_t interfaces, and set in blk_aio_prwv, which is updated here. 2. For all updated functions the parameter type becomes wider so callers are safe. 3. In blk_aio_prwv we only store bytes to BlkAioEmAIOCB, which is updated here. 4. Other updated functions are wrappers on blk_aio_prwv. Note that blk_aio_preadv and blk_aio_pwritev become safer: before this commit, it's theoretically possible to pass qiov with size exceeding INT_MAX, which than converted to int argument of blk_aio_prwv. Now it's converted to int64_t which is a lot better. Still add assertions. Signed-off-by: Vladimir Sementsov-Ogievskiy <vsementsov@virtuozzo.com> Message-Id: <20211006131718.214235-11-vsementsov@virtuozzo.com> Reviewed-by: Eric Blake <eblake@redhat.com> [eblake: tweak assertion and grammar] Signed-off-by: Eric Blake <eblake@redhat.com>
* block-backend: convert blk_co_copy_range to int64_t bytesVladimir Sementsov-Ogievskiy2021-10-151-1/+1
| | | | | | | | | | | | | | | | | | Function is updated so that parameter type becomes wider, so all callers should be OK with it. Look at blk_co_copy_range() itself: bytes is passed only to blk_check_byte_request() and bdrv_co_copy_range(), which already have int64_t bytes parameter, so we are OK. Note that requests exceeding INT_MAX are still restricted by blk_check_byte_request(). Signed-off-by: Vladimir Sementsov-Ogievskiy <vsementsov@virtuozzo.com> Message-Id: <20211006131718.214235-10-vsementsov@virtuozzo.com> Reviewed-by: Eric Blake <eblake@redhat.com> [eblake: grammar tweaks] Signed-off-by: Eric Blake <eblake@redhat.com>
* block-backend: convert blk_foo wrappers to use int64_t bytes parameterVladimir Sementsov-Ogievskiy2021-10-151-3/+3
| | | | | | | | | | | | | | | | | | | | | | | Convert blk_pdiscard, blk_pwrite_compressed, blk_pwrite_zeroes. These are just wrappers for functions with int64_t argument, so allow passing int64_t as well. Parameter type becomes wider so all callers should be OK with it. Note that requests exceeding INT_MAX are still restricted by blk_check_byte_request(). Note also that we don't (and are not going to) convert blk_pwrite and blk_pread: these functions return number of bytes on success, so to update them, we should change return type to int64_t as well, which will lead to investigating and updating all callers which is too much. So, blk_pread and blk_pwrite remain unchanged. Signed-off-by: Vladimir Sementsov-Ogievskiy <vsementsov@virtuozzo.com> Message-Id: <20211006131718.214235-9-vsementsov@virtuozzo.com> Reviewed-by: Eric Blake <eblake@redhat.com> [eblake: grammar tweaks] Signed-off-by: Eric Blake <eblake@redhat.com>
* block-backend: convert blk_co_pdiscard to int64_t bytesVladimir Sementsov-Ogievskiy2021-10-151-1/+2
| | | | | | | | | | | | | | | | | | | We updated blk_do_pdiscard() and its wrapper blk_co_pdiscard(). Both functions are updated so that the parameter type becomes wider, so all callers should be OK with it. Look at blk_do_pdiscard(): bytes is passed only to blk_check_byte_request() and bdrv_co_pdiscard(), which already have int64_t bytes parameter, so we are OK. Note that requests exceeding INT_MAX are still restricted by blk_check_byte_request(). Signed-off-by: Vladimir Sementsov-Ogievskiy <vsementsov@virtuozzo.com> Message-Id: <20211006131718.214235-5-vsementsov@virtuozzo.com> Reviewed-by: Eric Blake <eblake@redhat.com> [eblake: grammar tweaks] Signed-off-by: Eric Blake <eblake@redhat.com>
* block-backend: convert blk_co_pwritev_part to int64_t bytesVladimir Sementsov-Ogievskiy2021-10-151-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | We convert blk_do_pwritev_part() and some wrappers: blk_co_pwritev_part(), blk_co_pwritev(), blk_co_pwrite_zeroes(). All functions are converted so that the parameter type becomes wider, so all callers should be OK with it. Look at blk_do_pwritev_part() body: bytes is passed to: - trace_blk_co_pwritev (we update it here) - blk_check_byte_request, throttle_group_co_io_limits_intercept, bdrv_co_pwritev_part - all already have int64_t argument. Note that requests exceeding INT_MAX are still restricted by blk_check_byte_request(). Signed-off-by: Vladimir Sementsov-Ogievskiy <vsementsov@virtuozzo.com> Message-Id: <20211006131718.214235-4-vsementsov@virtuozzo.com> Reviewed-by: Eric Blake <eblake@redhat.com> [eblake: grammar tweaks] Signed-off-by: Eric Blake <eblake@redhat.com>
* block-backend: make blk_co_preadv() 64bitVladimir Sementsov-Ogievskiy2021-10-151-1/+1
| | | | | | | | | | | | | | | | | | | | | | For both updated functions, the type of bytes becomes wider, so all callers should be OK with it. blk_co_preadv() only passes its arguments to blk_do_preadv(). blk_do_preadv() passes bytes to: - trace_blk_co_preadv, which is updated too - blk_check_byte_request, throttle_group_co_io_limits_intercept, bdrv_co_preadv, which are already int64_t. Note that requests exceeding INT_MAX are still restricted by blk_check_byte_request(). Signed-off-by: Vladimir Sementsov-Ogievskiy <vsementsov@virtuozzo.com> Message-Id: <20211006131718.214235-3-vsementsov@virtuozzo.com> Reviewed-by: Eric Blake <eblake@redhat.com> [eblake: grammar tweaks] Signed-off-by: Eric Blake <eblake@redhat.com>
* qdev: Base object creation on QDict rather than QemuOptsKevin Wolf2021-10-153-6/+11
| | | | | | | | | | | | | | | | | QDicts are both what QMP natively uses and what the keyval parser produces. Going through QemuOpts isn't useful for either one, so switch the main device creation function to QDicts. By sharing more code with the -object/object-add code path, we can even reduce the code size a bit. This commit doesn't remove the detour through QemuOpts from any code path yet, but it allows the following commits to do so. Signed-off-by: Kevin Wolf <kwolf@redhat.com> Message-Id: <20211008133442.141332-15-kwolf@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Tested-by: Peter Krempa <pkrempa@redhat.com> Signed-off-by: Kevin Wolf <kwolf@redhat.com>
* virtio-net: Store failover primary opts pointer locallyKevin Wolf2021-10-151-0/+1
| | | | | | | | | | | | | | | | | | | | Instead of accessing the global QemuOptsList, which really belong to the command line parser and shouldn't be accessed from devices, store a pointer to the QemuOpts in a new VirtIONet field. This is not the final state, but just an intermediate step to get rid of QemuOpts in devices. It will later be replaced with an options QDict. Before this patch, two "primary" devices could be hidden for the same standby device, but only one of them would actually be enabled and the other one would be kept hidden forever, so this doesn't make sense. After this patch, configuring a second primary device is an error. Signed-off-by: Kevin Wolf <kwolf@redhat.com> Message-Id: <20211008133442.141332-13-kwolf@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Tested-by: Peter Krempa <pkrempa@redhat.com> Signed-off-by: Kevin Wolf <kwolf@redhat.com>
* qdev: Add Error parameter to hide_device() callbacksKevin Wolf2021-10-151-2/+6
| | | | | | | | | | | | | | | | | hide_device() is used for virtio-net failover, where the standby virtio device delays creation of the primary device. It only makes sense to have a single primary device for each standby device. Adding a second one should result in an error instead of hiding it and never using it afterwards. Prepare for this by adding an Error parameter to the hide_device() callback where virtio-net is informed about adding a primary device. Signed-off-by: Kevin Wolf <kwolf@redhat.com> Message-Id: <20211008133442.141332-12-kwolf@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Tested-by: Peter Krempa <pkrempa@redhat.com> Signed-off-by: Kevin Wolf <kwolf@redhat.com>
* softmmu/qdev-monitor: add error handling in qdev_set_idDamien Hedde2021-10-151-1/+24
| | | | | | | | | | | | | | | | | | | | | | | | | | qdev_set_id() is mostly used when the user adds a device (using -device cli option or device_add qmp command). This commit adds an error parameter to handle the case where the given id is already taken. Also document the function and add a return value in order to be able to capture success/failure: the function now returns the id in case of success, or NULL in case of failure. The commit modifies the 2 calling places (qdev-monitor and xen-legacy-backend) to add the error object parameter. Note that the id is, right now, guaranteed to be unique because all ids came from the "device" QemuOptsList where the id is used as key. This addition is a preparation for a future commit which will relax the uniqueness. Signed-off-by: Damien Hedde <damien.hedde@greensocs.com> Signed-off-by: Kevin Wolf <kwolf@redhat.com> Message-Id: <20211008133442.141332-10-kwolf@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Tested-by: Peter Krempa <pkrempa@redhat.com> Signed-off-by: Kevin Wolf <kwolf@redhat.com>
generated by cgit v1.2.3-55-g7522 (git 2.39.0) at 2026-03-04 08:07:15 +0100