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| * | include/qemu/lockable: Use _Generic instead of QEMU_GENERICRichard Henderson2021-06-161-48/+40Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is both more and less complicated than our expansion using __builtin_choose_expr and __builtin_types_compatible_p. The expansion through QEMU_MAKE_LOCKABLE_ doesn't work because we're not emumerating all of the types within the same _Generic, which results in errors about unhandled cases. We must also handle void* explicitly, so that the NULL constant can be used. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Tested-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20210614233143.1221879-7-richard.henderson@linaro.org>
| * | util: Use unique type for QemuRecMutex in thread-posix.hRichard Henderson2021-06-161-2/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We will shortly convert lockable.h to _Generic, and we cannot have two compatible types in the same expansion. Wrap QemuMutex in a struct, and unwrap in qemu-thread-posix.c. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20210614233143.1221879-6-richard.henderson@linaro.org>
| * | util: Pass file+line to qemu_rec_mutex_unlock_implRichard Henderson2021-06-161-1/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Create macros for file+line expansion in qemu_rec_mutex_unlock like we have for qemu_mutex_unlock. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20210614233143.1221879-5-richard.henderson@linaro.org>
| * | util: Use real functions for thread-posix QemuRecMutexRichard Henderson2021-06-163-13/+6Star
| |/ | | | | | | | | | | | | | | | | | | | | Move the declarations from thread-win32.h into thread.h and remove the macro redirection from thread-posix.h. This will be required by following cleanups. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20210614233143.1221879-4-richard.henderson@linaro.org>
* | Merge remote-tracking branch ↵Peter Maydell2021-06-162-0/+39
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 'remotes/pmaydell/tags/pull-target-arm-20210616' into staging target-arm queue: * hw/intc/arm_gicv3_cpuif: Tolerate spurious EOIR writes * handle some UNALLOCATED decode cases correctly rather than asserting * hw: virt: consider hw_compat_6_0 * hw/arm: add quanta-gbs-bmc machine * hw/intc/armv7m_nvic: Remove stale comment * target/arm: Fix mte page crossing test * hw/arm: quanta-q71l add pca954x muxes * target/arm: First few parts of MVE support # gpg: Signature made Wed 16 Jun 2021 14:34:49 BST # gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE # gpg: issuer "peter.maydell@linaro.org" # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [ultimate] # gpg: aka "Peter Maydell <pmaydell@gmail.com>" [ultimate] # gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [ultimate] # Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE * remotes/pmaydell/tags/pull-target-arm-20210616: (25 commits) include/qemu/int128.h: Add function to create Int128 from int64_t bitops.h: Provide hswap32(), hswap64(), wswap64() swapping operations target/arm: Move expand_pred_b() data to vec_helper.c target/arm: Add framework for MVE decode target/arm: Implement MVE LETP insn target/arm: Implement MVE DLSTP target/arm: Implement MVE WLSTP insn target/arm: Implement MVE LCTP target/arm: Let vfp_access_check() handle late NOCP checks target/arm: Add handling for PSR.ECI/ICI target/arm: Handle VPR semantics in existing code target/arm: Enable FPSCR.QC bit for MVE target/arm: Provide and use H8 and H1_8 macros hw/arm: quanta-q71l add pca954x muxes hw/arm: gsj add pca9548 hw/arm: gsj add i2c comments target/arm: Fix mte page crossing test hw/intc/armv7m_nvic: Remove stale comment hw/arm: quanta-gbs-bmc add i2c comments hw/arm: add quanta-gbs-bmc machine ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * | include/qemu/int128.h: Add function to create Int128 from int64_tPeter Maydell2021-06-161-0/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | int128_make64() creates an Int128 from an unsigned 64 bit value; add a function int128_makes64() creating an Int128 from a signed 64 bit value. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-id: 20210614151007.4545-34-peter.maydell@linaro.org
| * | bitops.h: Provide hswap32(), hswap64(), wswap64() swapping operationsPeter Maydell2021-06-161-0/+29
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently the ARM SVE helper code defines locally some utility functions for swapping 16-bit halfwords within 32-bit or 64-bit values and for swapping 32-bit words within 64-bit values, parallel to the byte-swapping bswap16/32/64 functions. We want these also for the ARM MVE code, and they're potentially generally useful for other targets, so move them to bitops.h. (We don't put them in bswap.h with the bswap* functions because they are implemented in terms of the rotate operations also defined in bitops.h, and including bitops.h from bswap.h seems better avoided.) Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-id: 20210614151007.4545-17-peter.maydell@linaro.org
* | sysemu: Make TPM structures inaccessible if CONFIG_TPM is not definedStefan Berger2021-06-152-1/+14
| | | | | | | | | | | | | | | | | | Signed-off-by: Stefan Berger <stefanb@linux.ibm.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-Id: <20210614191335.1968807-5-stefanb@linux.ibm.com> [PMD: Remove tpm_init() / tpm_cleanup() stubs] Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
* | acpi: Eliminate all TPM related code if CONFIG_TPM is not setStefan Berger2021-06-151-0/+4
|/ | | | | | | | | | Cc: M: Michael S. Tsirkin <mst@redhat.com> Cc: Igor Mammedov <imammedo@redhat.com> Signed-off-by: Stefan Berger <stefanb@linux.ibm.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-Id: <20210614191335.1968807-4-stefanb@linux.ibm.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
* tcg: Fix documentation for tcg_constant_* vs tcg_temp_free_*Richard Henderson2021-06-141-1/+2
| | | | | | | | | | | | | At some point during the development of tcg_constant_*, I changed my mind about whether such temps should be able to be passed to tcg_temp_free_*. The final version committed allows this, but the commentary was not updated to match. Fixes: c0522136adf Reported-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Luis Pires <luis.pires@eldorado.org.br> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg: Introduce tcg_remove_ops_afterRichard Henderson2021-06-141-0/+10
| | | | | | | | Introduce a function to remove everything emitted since a given point. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg: Move tcg_init_ctx and tcg_ctx from accel/tcg/Richard Henderson2021-06-141-1/+0Star
| | | | | | | | | | | | These variables belong to the jit side, not the user side. Since tcg_init_ctx is no longer used outside of tcg/, move the declaration to tcg-internal.h. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Luis Pires <luis.pires@eldorado.org.br> Suggested-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* util/osdep: Add qemu_mprotect_rwRichard Henderson2021-06-141-0/+1
| | | | | | | | | For --enable-tcg-interpreter on Windows, we will need this. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Luis Pires <luis.pires@eldorado.org.br> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg: Move in_code_gen_buffer and tests to region.cRichard Henderson2021-06-111-10/+1Star
| | | | | | | | | | | | | | | | | Shortly, the full code_gen_buffer will only be visible to region.c, so move in_code_gen_buffer out-of-line. Move the debugging versions of tcg_splitwx_to_{rx,rw} to region.c as well, so that the compiler gets to see the implementation of in_code_gen_buffer. This leaves exactly one use of in_code_gen_buffer outside of region.c, in cpu_restore_state. Which, being on the exception path, is not performance critical. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Luis Pires <luis.pires@eldorado.org.br> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* accel/tcg: Pass down max_cpus to tcg_initRichard Henderson2021-06-111-1/+1
| | | | | | | | | | | Start removing the include of hw/boards.h from tcg/. Pass down the max_cpus value from tcg_init_machine, where we have the MachineState already. Reviewed-by: Luis Pires <luis.pires@eldorado.org.br> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* accel/tcg: Merge tcg_exec_init into tcg_init_machineRichard Henderson2021-06-111-2/+0Star
| | | | | | | | | There is only one caller, and shortly we will need access to the MachineState, which tcg_init_machine already has. Reviewed-by: Luis Pires <luis.pires@eldorado.org.br> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg: Create tcg_initRichard Henderson2021-06-111-2/+1Star
| | | | | | | | | Perform both tcg_context_init and tcg_region_init. Do not leave this split to the caller. Reviewed-by: Luis Pires <luis.pires@eldorado.org.br> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* accel/tcg: Move alloc_code_gen_buffer to tcg/region.cRichard Henderson2021-06-111-1/+1
| | | | | | | | | | Buffer management is integral to tcg. Do not leave the allocation to code outside of tcg/. This is code movement, with further cleanups to follow. Reviewed-by: Luis Pires <luis.pires@eldorado.org.br> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* vhost-vdpa: remove the unused vhost_vdpa_get_acked_features()Jason Wang2021-06-111-1/+0Star
| | | | | | No user for this helper, let's remove it. Signed-off-by: Jason Wang <jasowang@redhat.com>
* vhost-vdpa: map virtqueue notification area if possibleJason Wang2021-06-111-0/+6
| | | | | | | | | | | This patch implements the vq notification mapping support for vhost-vDPA. This is simply done by using mmap()/munmap() for the vhost-vDPA fd during device start/stop. For the device without notification mapping support, we fall back to eventfd based notification gracefully. Reviewed-by: Si-Wei Liu <si-wei.liu@oracle.com> Signed-off-by: Jason Wang <jasowang@redhat.com>
* hmp: Add "calc_dirty_rate" and "info dirty_rate" cmdsPeter Xu2021-06-081-0/+2
| | | | | | | | | | | These two commands are missing when adding the QMP sister commands. Add them, so developers can play with them easier. Signed-off-by: Peter Xu <peterx@redhat.com> Signed-off-by: Hyman Huang(黄勇) <huangy81@chinatelecom.cn> Message-Id: <4cc0039fc3ad6145136770cf3b0f056c09a2910b.1623027729.git.huangy81@chinatelecom.cn> Reviewed-by: Dr. David Alan Gilbert <dgilbert@redhat.com> Signed-off-by: Dr. David Alan Gilbert <dgilbert@redhat.com>
* Merge remote-tracking branch ↵Peter Maydell2021-06-081-0/+5
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 'remotes/alistair/tags/pull-riscv-to-apply-20210608-1' into staging Second RISC-V PR for QEMU 6.1 - Update the PLIC and CLINT DT bindings - Improve documentation for RISC-V machines - Support direct kernel boot for microchip_pfsoc - Fix WFI exception behaviour - Improve CSR printing - Initial support for the experimental Bit Manip extension # gpg: Signature made Tue 08 Jun 2021 01:28:27 BST # gpg: using RSA key F6C4AC46D4934868D3B8CE8F21E10D29DF977054 # gpg: Good signature from "Alistair Francis <alistair@alistair23.me>" [full] # Primary key fingerprint: F6C4 AC46 D493 4868 D3B8 CE8F 21E1 0D29 DF97 7054 * remotes/alistair/tags/pull-riscv-to-apply-20210608-1: (32 commits) target/riscv: rvb: add b-ext version cpu option target/riscv: rvb: support and turn on B-extension from command line target/riscv: rvb: add/shift with prefix zero-extend target/riscv: rvb: address calculation target/riscv: rvb: generalized or-combine target/riscv: rvb: generalized reverse target/riscv: rvb: rotate (left/right) target/riscv: rvb: shift ones target/riscv: rvb: single-bit instructions target/riscv: add gen_shifti() and gen_shiftiw() helper functions target/riscv: rvb: sign-extend instructions target/riscv: rvb: min/max instructions target/riscv: rvb: pack two words into one register target/riscv: rvb: logic-with-negate target/riscv: rvb: count bits set target/riscv: rvb: count leading/trailing zeros target/riscv: reformat @sh format encoding for B-extension target/riscv: Pass the same value to oprsz and maxsz. target/riscv/pmp: Add assert for ePMP operations target/riscv: Dump CSR mscratch/sscratch/satp ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * hw/riscv: Use macros for BIOS image namesBin Meng2021-06-081-0/+5
| | | | | | | | | | | | | | | | | | | | The OpenSBI BIOS image names are used by many RISC-V machines. Let's define macros for them. Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20210430071302.1489082-7-bmeng.cn@gmail.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
* | vhost-vdpa: Remove redundant declaration of address_space_memoryXie Yongji2021-06-051-1/+0Star
| | | | | | | | | | | | | | | | | | | | | | | | The symbol address_space_memory are already declared in include/exec/address-spaces.h. So let's add this header file and remove the redundant declaration in include/hw/virtio/vhost-vdpa.h. Signed-off-by: Xie Yongji <xieyongji@bytedance.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Stefano Garzarella <sgarzare@redhat.com> Message-Id: <20210517123246.999-1-xieyongji@bytedance.com> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
* | docs: fix broken referenceJohn Snow2021-06-051-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Long story short, we need a space here for the reference to work correctly. Longer story: Without the space, kerneldoc generates a line like this: one of :c:type:`MemoryListener.region_add\(\) <MemoryListener>`,:c:type:`MemoryListener.region_del\(\) Sphinx does not process the role information correctly, so we get this (my pseudo-notation) construct: <text>,:c:type:</text> <reference target="MemoryListener">MemoryListener.region_del()</reference> which does not reference the desired entity, and leaves some extra junk in the rendered output. See https://qemu-project.gitlab.io/qemu/devel/memory.html#c.MemoryListener member log_start for an example of the broken output as it looks today. Signed-off-by: John Snow <jsnow@redhat.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-Id: <20210511192950.2061326-1-jsnow@redhat.com> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
* | misc: Correct relative include pathPhilippe Mathieu-Daudé2021-06-051-1/+1
|/ | | | | | | | | | Headers should be included from the 'include/' directory, not from the root directory. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Message-Id: <20210516205034.694788-1-f4bug@amsat.org> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
* Merge remote-tracking branch 'remotes/bonzini-gitlab/tags/for-upstream' into ↵Peter Maydell2021-06-043-3/+9
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | staging * OpenBSD cleanup (Brad) * fixes for the i386 accel/cpu refactoring (Claudio) * unmap test for emulated SCSI (Kit) * fix for iscsi module (myself) * fix for -readconfig of objects (myself) * fixes for x86 16-bit task switching (myself) * fix for x86 MOV from/to CR8 (Richard) # gpg: Signature made Fri 04 Jun 2021 12:53:32 BST # gpg: using RSA key F13338574B662389866C7682BFFBD25F78C7AE83 # gpg: issuer "pbonzini@redhat.com" # gpg: Good signature from "Paolo Bonzini <bonzini@gnu.org>" [full] # gpg: aka "Paolo Bonzini <pbonzini@redhat.com>" [full] # Primary key fingerprint: 46F5 9FBD 57D6 12E7 BFD4 E2F7 7E15 100C CD36 69B1 # Subkey fingerprint: F133 3857 4B66 2389 866C 7682 BFFB D25F 78C7 AE83 * remotes/bonzini-gitlab/tags/for-upstream: vl: plug -object back into -readconfig vl: plumb keyval-based options into -readconfig qemu-config: parse configuration files to a QDict i386: run accel_cpu_instance_init as post_init i386: reorder call to cpu_exec_realizefn tests/qtest/virtio-scsi-test: add unmap large LBA with 4k blocks test target/i386: Fix decode of cr8 target/i386: tcg: fix switching from 16-bit to 32-bit tasks or vice versa target/i386: tcg: fix loading of registers from 16-bit TSS target/i386: tcg: fix segment register offsets for 16-bit TSS oslib-posix: Remove OpenBSD workaround for fcntl("/dev/null", F_SETFL, O_NONBLOCK) failure iscsi: link libm into the module meson: allow optional dependencies for block modules Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * vl: plumb keyval-based options into -readconfigPaolo Bonzini2021-06-042-2/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | Let -readconfig support parsing command line options into QDict or QemuOpts. This will be used to add back support for objects in -readconfig. Cc: Markus Armbruster <armbru@redhat.com> Cc: qemu-stable@nongnu.org Reviewed-by: Kevin Wolf <kwolf@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Message-Id: <20210524105752.3318299-3-pbonzini@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
| * qemu-config: parse configuration files to a QDictPaolo Bonzini2021-06-041-1/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Change the parser to put the values into a QDict and pass them to a callback. qemu_config_parse's QemuOpts creation is itself turned into a callback function. This is useful for -readconfig to support keyval-based options; getting a QDict from the parser removes a roundtrip from QDict to QemuOpts and then back to QDict. Unfortunately there is a disadvantage in that semantic errors will point to the last line of the group, because the entries of the QDict do not have a location attached. Cc: Kevin Wolf <kwolf@redhat.com> Cc: Markus Armbruster <armbru@redhat.com> Cc: qemu-stable@nongnu.org Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Message-Id: <20210524105752.3318299-2-pbonzini@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
* | Merge remote-tracking branch 'remotes/jasowang/tags/net-pull-request' into ↵Peter Maydell2021-06-042-0/+6
|\ \ | |/ |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | staging # gpg: Signature made Fri 04 Jun 2021 08:26:16 BST # gpg: using RSA key EF04965B398D6211 # gpg: Good signature from "Jason Wang (Jason Wang on RedHat) <jasowang@redhat.com>" [marginal] # gpg: WARNING: This key is not certified with sufficiently trusted signatures! # gpg: It is not certain that the signature belongs to the owner. # Primary key fingerprint: 215D 46F4 8246 689E C77F 3562 EF04 965B 398D 6211 * remotes/jasowang/tags/net-pull-request: MAINTAINERS: Added eBPF maintainers information. docs: Added eBPF documentation. virtio-net: Added eBPF RSS to virtio-net. ebpf: Added eBPF RSS loader. ebpf: Added eBPF RSS program. net: Added SetSteeringEBPF method for NetClientState. net/tap: Added TUNSETSTEERINGEBPF code. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * virtio-net: Added eBPF RSS to virtio-net.Andrew Melnychenko2021-06-041-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | When RSS is enabled the device tries to load the eBPF program to select RX virtqueue in the TUN. If eBPF can be loaded the RSS will function also with vhost (works with kernel 5.8 and later). Software RSS is used as a fallback with vhost=off when eBPF can't be loaded or when hash population requested by the guest. Signed-off-by: Yuri Benditovich <yuri.benditovich@daynix.com> Signed-off-by: Andrew Melnychenko <andrew@daynix.com> Signed-off-by: Jason Wang <jasowang@redhat.com>
| * net: Added SetSteeringEBPF method for NetClientState.Andrew Melnychenko2021-06-041-0/+2
| | | | | | | | | | | | | | | | For now, that method supported only by Linux TAP. Linux TAP uses TUNSETSTEERINGEBPF ioctl. Signed-off-by: Andrew Melnychenko <andrew@daynix.com> Signed-off-by: Jason Wang <jasowang@redhat.com>
* | softfloat: Convert modrem operations to FloatPartsRichard Henderson2021-06-031-0/+34
| | | | | | | | | | | | | | | | Rename to parts$N_modrem. This was the last use of a lot of the legacy infrastructure, so remove it as required. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* | softfloat: Introduce Floatx80RoundPrecRichard Henderson2021-06-033-5/+14
| | | | | | | | | | | | | | Use an enumeration instead of raw 32/64/80 values. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* | softfloat: Implement float128_(min|minnum|minnummag|max|maxnum|maxnummag)David Hildenbrand2021-06-031-0/+6
| | | | | | | | | | | | | | | | | | | | The float128 implementation is straight-forward. Unfortuantely, we don't have any tests we can simply adjust/unlock. Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20210517142739.38597-24-david@redhat.com> [rth: Update for changed parts_minmax return value] Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* | hvf: Introduce hvf vcpu structAlexander Graf2021-06-032-1/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We will need more than a single field for hvf going forward. To keep the global vcpu struct uncluttered, let's allocate a special hvf vcpu struct, similar to how hax does it. Signed-off-by: Alexander Graf <agraf@csgraf.de> Reviewed-by: Roman Bolshakov <r.bolshakov@yadro.com> Tested-by: Roman Bolshakov <r.bolshakov@yadro.com> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Sergio Lopez <slp@redhat.com> Message-id: 20210519202253.76782-12-agraf@csgraf.de Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* | hvf: Remove hvf-accel-ops.hAlexander Graf2021-06-031-0/+1
| | | | | | | | | | | | | | | | | | | | | | We can move the definition of hvf_vcpu_exec() into our internal hvf header, obsoleting the need for hvf-accel-ops.h. Signed-off-by: Alexander Graf <agraf@csgraf.de> Reviewed-by: Sergio Lopez <slp@redhat.com> Message-id: 20210519202253.76782-11-agraf@csgraf.de Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* | hvf: Split out common code on vcpu init and destroyAlexander Graf2021-06-031-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Until now, Hypervisor.framework has only been available on x86_64 systems. With Apple Silicon shipping now, it extends its reach to aarch64. To prepare for support for multiple architectures, let's start moving common code out into its own accel directory. This patch splits the vcpu init and destroy functions into a generic and an architecture specific portion. This also allows us to move the generic functions into the generic hvf code, removing exported functions. Signed-off-by: Alexander Graf <agraf@csgraf.de> Reviewed-by: Sergio Lopez <slp@redhat.com> Message-id: 20210519202253.76782-8-agraf@csgraf.de Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* | hvf: Make hvf_set_phys_mem() staticAlexander Graf2021-06-031-1/+0Star
| | | | | | | | | | | | | | | | | | | | | | The hvf_set_phys_mem() function is only called within the same file. Make it static. Signed-off-by: Alexander Graf <agraf@csgraf.de> Reviewed-by: Sergio Lopez <slp@redhat.com> Message-id: 20210519202253.76782-6-agraf@csgraf.de Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* | hvf: Move hvf internal definitions into common headerAlexander Graf2021-06-031-0/+30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Until now, Hypervisor.framework has only been available on x86_64 systems. With Apple Silicon shipping now, it extends its reach to aarch64. To prepare for support for multiple architectures, let's start moving common code out into its own accel directory. This patch moves a few internal struct and constant defines over. Signed-off-by: Alexander Graf <agraf@csgraf.de> Reviewed-by: Sergio Lopez <slp@redhat.com> Message-id: 20210519202253.76782-5-agraf@csgraf.de Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* | hvf: Move cpu functions into common directoryAlexander Graf2021-06-031-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Until now, Hypervisor.framework has only been available on x86_64 systems. With Apple Silicon shipping now, it extends its reach to aarch64. To prepare for support for multiple architectures, let's start moving common code out into its own accel directory. This patch moves CPU and memory operations over. While at it, make sure the code is consumable on non-i386 systems. Signed-off-by: Alexander Graf <agraf@csgraf.de> Reviewed-by: Sergio Lopez <slp@redhat.com> Message-id: 20210519202253.76782-4-agraf@csgraf.de Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* | hvf: Move assert_hvf_ok() into common directoryAlexander Graf2021-06-031-0/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Until now, Hypervisor.framework has only been available on x86_64 systems. With Apple Silicon shipping now, it extends its reach to aarch64. To prepare for support for multiple architectures, let's start moving common code out into its own accel directory. This patch moves assert_hvf_ok() and introduces generic build infrastructure. Signed-off-by: Alexander Graf <agraf@csgraf.de> Reviewed-by: Sergio Lopez <slp@redhat.com> Message-id: 20210519202253.76782-2-agraf@csgraf.de Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* | softfpu: Add float_round_to_odd_infRichard Henderson2021-06-031-1/+3
| | | | | | | | | | | | | | | | | | | | | | For Arm BFDOT and BFMMLA, we need a version of round-to-odd that overflows to infinity, instead of the max normal number. Cc: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210525225817.400336-6-richard.henderson@linaro.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* | arm: Consistently use "Cortex-Axx", not "Cortex Axx"Peter Maydell2021-06-031-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The official punctuation for Arm CPU names uses a hyphen, like "Cortex-A9". We mostly follow this, but in a few places usage without the hyphen has crept in. Fix those so we consistently use the same way of writing the CPU name. This commit was created with: git grep -z -l 'Cortex ' | xargs -0 sed -i 's/Cortex /Cortex-/' Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Message-id: 20210527095152.10968-1-peter.maydell@linaro.org
* | target/arm: Allow board models to specify initial NS VTORPeter Maydell2021-06-031-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | Currently we allow board models to specify the initial value of the Secure VTOR register, using an init-svtor property on the TYPE_ARMV7M object which is plumbed through to the CPU. Allow board models to also specify the initial value of the Non-secure VTOR via a similar init-nsvtor property. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210520152840.24453-10-peter.maydell@linaro.org
* | Merge remote-tracking branch 'remotes/dg-gitlab/tags/ppc-for-6.1-20210603' ↵Peter Maydell2021-06-033-24/+5Star
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | into staging ppc patch queue 2021-06-03 Next batch of ppc target patches. Highlights are: * A fix for a regression with single-step mode * Start of moving ppc to use decodetree * Implementation of some POWER10 64-bit prefixed instructions * Several cleanups to softmmu code * Continued progress towards allowing --disable-tcg * Fix for the POWER PEF implementation * Fix for LPCR handling of hotplugged CPUs * Assorted other bugfixes and cleanups This patchset does contain a couple of changes to code outside my normal scope of maintainership, related to the removal of cpu_dump and cpu_statistics hooks. ppc was the last target arch implementing these at all, and they didn't really do anything there either. The patches should have relevant acks. # gpg: Signature made Thu 03 Jun 2021 09:20:59 BST # gpg: using RSA key 75F46586AE61A66CC44E87DC6C38CACA20D9B392 # gpg: Good signature from "David Gibson <david@gibson.dropbear.id.au>" [full] # gpg: aka "David Gibson (Red Hat) <dgibson@redhat.com>" [full] # gpg: aka "David Gibson (ozlabs.org) <dgibson@ozlabs.org>" [full] # gpg: aka "David Gibson (kernel.org) <dwg@kernel.org>" [unknown] # Primary key fingerprint: 75F4 6586 AE61 A66C C44E 87DC 6C38 CACA 20D9 B392 * remotes/dg-gitlab/tags/ppc-for-6.1-20210603: (42 commits) target/ppc: fix single-step exception regression target/ppc: Move cmp/cmpi/cmpl/cmpli to decodetree target/ppc: Move addpcis to decodetree target/ppc: Implement vcfuged instruction target/ppc: Implement cfuged instruction target/ppc: Implement setbc/setbcr/stnbc/setnbcr instructions target/ppc: Implement prefixed integer store instructions target/ppc: Move D/DS/X-form integer stores to decodetree target/ppc: Implement prefixed integer load instructions target/ppc: Move D/DS/X-form integer loads to decodetree target/ppc: Implement PNOP target/ppc: Move ADDI, ADDIS to decodetree, implement PADDI target/ppc: Add infrastructure for prefixed insns target/ppc: Move page crossing check to ppc_tr_translate_insn target/ppc: Introduce macros to check isa extensions target/ppc: powerpc_excp: Consolidade TLB miss code target/ppc: powerpc_excp: Remove dump_syscall_vectored target/ppc: powerpc_excp: Move lpes code to where it is used target/ppc: overhauled and moved logic of storing fpscr target/ppc: removed all mentions to PPC_DUMP_CPU ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * | hw/core/cpu: removed cpu_dump_statistics functionBruno Larsen (billionai)2021-06-031-12/+0Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | No more architectures set the pointer to dump_statistics, so there's no point in keeping it, or the related cpu_dump_statistics function. Suggested-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Bruno Larsen (billionai) <bruno.larsen@eldorado.org.br> Message-Id: <20210526202104.127910-6-bruno.larsen@eldorado.org.br> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Luis Pires <luis.pires@eldorado.org.br> Signed-off-by: David Gibson <david@gibson.dropbear.id.au> Message-Id: <20210531145629.21300-2-bruno.larsen@eldorado.org.br> Acked-by: Eduardo Habkost <ehabkost@redhat.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
| * | spapr: nvdimm: Forward declare and move the definitionsShivaprasad G Bhat2021-06-031-12/+2Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The subsequent patches add definitions which tend to get the compilation to cyclic dependency. So, prepare with forward declarations, move the definitions and clean up. Signed-off-by: Shivaprasad G Bhat <sbhat@linux.ibm.com> Message-Id: <162133925415.610.11584121797866216417.stgit@4f1e6f2bd33e> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
| * | spapr: Don't hijack current_machine->boot_orderGreg Kurz2021-06-031-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | QEMU 6.0 moved all the -boot variables to the machine. Especially, the removal of the boot_order static changed the handling of '-boot once' from: if (boot_once) { qemu_boot_set(boot_once, &error_fatal); qemu_register_reset(restore_boot_order, g_strdup(boot_order)); } to if (current_machine->boot_once) { qemu_boot_set(current_machine->boot_once, &error_fatal); qemu_register_reset(restore_boot_order, g_strdup(current_machine->boot_order)); } This means that we now register as subsequent boot order a copy of current_machine->boot_once that was just set with the previous call to qemu_boot_set(), i.e. we never transition away from the once boot order. It is certainly fragile^Wwrong for the spapr code to hijack a field of the base machine type object like that. The boot order rework simply turned this software boundary violation into an actual bug. Have the spapr code to handle that with its own field in SpaprMachineState. Also kfree() the initial boot device string when "once" was used. Fixes: 4b7acd2ac821 ("vl: clean up -boot variables") Resolves: https://bugzilla.redhat.com/show_bug.cgi?id=1960119 Cc: pbonzini@redhat.com Signed-off-by: Greg Kurz <groug@kaod.org> Message-Id: <20210521160735.1901914-1-groug@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
* | | Merge remote-tracking branch 'remotes/kevin/tags/for-upstream' into stagingPeter Maydell2021-06-023-2/+5
|\ \ \ | |/ / |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Block layer patches - NBD server: Fix crashes related to switching between AioContexts - file-posix: Workaround for discard/write_zeroes on buggy filesystems - Follow-up fixes for the reopen vs. permission changes - quorum: Fix error handling for flush - block-copy: Refactor copy_range handling - docs: Describe how to use 'null-co' block driver # gpg: Signature made Wed 02 Jun 2021 14:44:15 BST # gpg: using RSA key DC3DEB159A9AF95D3D7456FE7F09B272C88F2FD6 # gpg: issuer "kwolf@redhat.com" # gpg: Good signature from "Kevin Wolf <kwolf@redhat.com>" [full] # Primary key fingerprint: DC3D EB15 9A9A F95D 3D74 56FE 7F09 B272 C88F 2FD6 * remotes/kevin/tags/for-upstream: docs/secure-coding-practices: Describe how to use 'null-co' block driver block-copy: refactor copy_range handling block-copy: fix block_copy_task_entry() progress update nbd/server: Use drained block ops to quiesce the server block-backend: add drained_poll block: improve permission conflict error message block: simplify bdrv_child_user_desc() block/vvfat: inherit child_vvfat_qcow from child_of_bds block: improve bdrv_child_get_parent_desc() block-backend: improve blk_root_get_parent_desc() block: document child argument of bdrv_attach_child_common() block/file-posix: Try other fallbacks after invalid FALLOC_FL_ZERO_RANGE block/file-posix: Fix problem with fallocate(PUNCH_HOLE) on GPFS block: drop BlockBackendRootState::read_only block: drop BlockDriverState::read_only block: consistently use bdrv_is_read_only() block/vvfat: fix vvfat_child_perm crash block/vvfat: child_vvfat_qcow: add .get_parent_aio_context, fix crash qemu-io-cmds: assert that we don't have .perm requested in no-blk case block/quorum: Provide .bdrv_co_flush instead of .bdrv_co_flush_to_disk Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
generated by cgit v1.2.3-55-g7522 (git 2.39.0) at 2026-03-05 17:34:02 +0100