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* linux-user: Add support for big-endian aarch64Michael Weiser2018-01-111-0/+6
| | | | | | | | | | | | Enable big-endian mode for data accesses on aarch64 for big-endian linux user mode. Activate it for all exception levels as documented by ARM: Set the SCTLR EE bit for ELs 1 through 3. Additionally set bit E0E in EL1 to enable it in EL0 as well. Signed-off-by: Michael Weiser <michael.weiser@gmx.de> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20171220212308.12614-2-michael.weiser@gmx.de Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* target/m68k: add chk and chk2Laurent Vivier2018-01-041-0/+7
| | | | | | | | | | chk and chk2 compare a value to boundaries, and trigger a CHK exception if the value is out of bounds. Signed-off-by: Laurent Vivier <laurent@vivier.eu> Suggested-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20180104012913.30763-8-laurent@vivier.eu>
* target/sh4: Use cmpxchg for movco when parallel_cpusRichard Henderson2017-12-181-4/+15
| | | | | | | | | | | As for other targets, cmpxchg isn't quite right for ll/sc, suffering from an ABA race, but is sufficient to implement portable atomic operations. Signed-off-by: Richard Henderson <rth@twiddle.net> Message-Id: <20170907185057.23421-2-richard.henderson@linaro.org> [aurel32: fix whitespace] Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* misc: remove headers implicitly includedPhilippe Mathieu-Daudé2017-12-181-1/+0Star
| | | | | | | | | | applied using ./scripts/clean-includes Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com> Reviewed-by: Ben Warren <ben@skyportsystems.com> Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
* linux-user/ppc: Report correct fault address for data faultsPeter Maydell2017-11-071-1/+1
| | | | | | | | | | | | | | | | For faults on loads and stores, ppc_cpu_handle_mmu_fault() in target/ppc/user_only_helper.c stores the offending address in env->spr[SPR_DAR]. Report this correctly to the guest in si_addr, rather than incorrectly using the address of the instruction that caused the fault. This fixes the test case in https://bugs.launchpad.net/qemu/+bug/1077116 for ppc, ppc64 and ppc64le. Reviewed-by: Laurent Vivier <laurent@vivier.eu> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Riku Voipio <riku.voipio@linaro.org>
* linux-user/s390x: Mask si_addr for SIGSEGVPeter Maydell2017-11-071-1/+5
| | | | | | | | | | | | | | | For s390x, the address passed to a signal handler in the siginfo_t si_addr field is masked (in the kernel this is done in do_sigbus() and do_sigsegv() in arch/s390/mm/fault.c). Implement this architecture-specific oddity in linux-user. This is one of the issues described in https://bugs.launchpad.net/qemu/+bug/1705118 Reviewed-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Riku Voipio <riku.voipio@linaro.org>
* sh4: simplify superh_cpu_class_by_name()Igor Mammedov2017-10-271-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | currently for sh4 cpu_model argument for '-cpu' option could be either 'cpu model' name or cpu_typename. however typically '-cpu' takes 'cpu model' name and cpu type for sh4 target isn't advertised publicly ('-cpu help' prints only 'cpu model' names) so we shouldn't care about this use case (it's more of a bug). 1. Drop '-cpu cpu_typename' to align with the rest of targets. 2. Compose searched for typename from cpu model and use it with object_class_by_name() directly instead of over-complicated object_class_get_list() g_slist_find_custom() + superh_cpu_name_compare() With #1 droped, #2 could be used for both lookups which simplifies superh_cpu_class_by_name() quite a bit. Signed-off-by: Igor Mammedov <imammedo@redhat.com> Acked-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <1507211474-188400-23-git-send-email-imammedo@redhat.com> [ehabkost: Include fixup sent by Igor] Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
* tcg: introduce regions to split code_gen_bufferEmilio G. Cota2017-10-241-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is groundwork for supporting multiple TCG contexts. The naive solution here is to split code_gen_buffer statically among the TCG threads; this however results in poor utilization if translation needs are different across TCG threads. What we do here is to add an extra layer of indirection, assigning regions that act just like pages do in virtual memory allocation. (BTW if you are wondering about the chosen naming, I did not want to use blocks or pages because those are already heavily used in QEMU). We use a global lock to serialize allocations as well as statistics reporting (we now export the size of the used code_gen_buffer with tcg_code_size()). Note that for the allocator we could just use a counter and atomic_inc; however, that would complicate the gathering of tcg_code_size()-like stats. So given that the region operations are not a fast path, a lock seems the most reasonable choice. The effectiveness of this approach is clear after seeing some numbers. I used the bootup+shutdown of debian-arm with '-tb-size 80' as a benchmark. Note that I'm evaluating this after enabling per-thread TCG (which is done by a subsequent commit). * -smp 1, 1 region (entire buffer): qemu: flush code_size=83885014 nb_tbs=154739 avg_tb_size=357 qemu: flush code_size=83884902 nb_tbs=153136 avg_tb_size=363 qemu: flush code_size=83885014 nb_tbs=152777 avg_tb_size=364 qemu: flush code_size=83884950 nb_tbs=150057 avg_tb_size=373 qemu: flush code_size=83884998 nb_tbs=150234 avg_tb_size=373 qemu: flush code_size=83885014 nb_tbs=154009 avg_tb_size=360 qemu: flush code_size=83885014 nb_tbs=151007 avg_tb_size=370 qemu: flush code_size=83885014 nb_tbs=151816 avg_tb_size=367 That is, 8 flushes. * -smp 8, 32 regions (80/32 MB per region) [i.e. this patch]: qemu: flush code_size=76328008 nb_tbs=141040 avg_tb_size=356 qemu: flush code_size=75366534 nb_tbs=138000 avg_tb_size=361 qemu: flush code_size=76864546 nb_tbs=140653 avg_tb_size=361 qemu: flush code_size=76309084 nb_tbs=135945 avg_tb_size=375 qemu: flush code_size=74581856 nb_tbs=132909 avg_tb_size=375 qemu: flush code_size=73927256 nb_tbs=135616 avg_tb_size=360 qemu: flush code_size=78629426 nb_tbs=142896 avg_tb_size=365 qemu: flush code_size=76667052 nb_tbs=138508 avg_tb_size=368 Again, 8 flushes. Note how buffer utilization is not 100%, but it is close. Smaller region sizes would yield higher utilization, but we want region allocation to be rare (it acquires a lock), so we do not want to go too small. * -smp 8, static partitioning of 8 regions (10 MB per region): qemu: flush code_size=21936504 nb_tbs=40570 avg_tb_size=354 qemu: flush code_size=11472174 nb_tbs=20633 avg_tb_size=370 qemu: flush code_size=11603976 nb_tbs=21059 avg_tb_size=365 qemu: flush code_size=23254872 nb_tbs=41243 avg_tb_size=377 qemu: flush code_size=28289496 nb_tbs=52057 avg_tb_size=358 qemu: flush code_size=43605160 nb_tbs=78896 avg_tb_size=367 qemu: flush code_size=45166552 nb_tbs=82158 avg_tb_size=364 qemu: flush code_size=63289640 nb_tbs=116494 avg_tb_size=358 qemu: flush code_size=51389960 nb_tbs=93937 avg_tb_size=362 qemu: flush code_size=59665928 nb_tbs=107063 avg_tb_size=372 qemu: flush code_size=38380824 nb_tbs=68597 avg_tb_size=374 qemu: flush code_size=44884568 nb_tbs=79901 avg_tb_size=376 qemu: flush code_size=50782632 nb_tbs=90681 avg_tb_size=374 qemu: flush code_size=39848888 nb_tbs=71433 avg_tb_size=372 qemu: flush code_size=64708840 nb_tbs=119052 avg_tb_size=359 qemu: flush code_size=49830008 nb_tbs=90992 avg_tb_size=362 qemu: flush code_size=68372408 nb_tbs=123442 avg_tb_size=368 qemu: flush code_size=33555560 nb_tbs=59514 avg_tb_size=378 qemu: flush code_size=44748344 nb_tbs=80974 avg_tb_size=367 qemu: flush code_size=37104248 nb_tbs=67609 avg_tb_size=364 That is, 20 flushes. Note how a static partitioning approach uses the code buffer poorly, leading to many unnecessary flushes. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Emilio G. Cota <cota@braap.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg: define tcg_init_ctx and make tcg_ctx a pointerEmilio G. Cota2017-10-241-1/+1
| | | | | | | | | | | | | | | | | Groundwork for supporting multiple TCG contexts. The core of this patch is this change to tcg/tcg.h: > -extern TCGContext tcg_ctx; > +extern TCGContext tcg_init_ctx; > +extern TCGContext *tcg_ctx; Note that for now we set *tcg_ctx to whatever TCGContext is passed to tcg_context_init -- in this case &tcg_init_ctx. Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Emilio G. Cota <cota@braap.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg: take tb_ctx out of TCGContextEmilio G. Cota2017-10-241-3/+3
| | | | | | | | | Groundwork for supporting multiple TCG contexts. Reviewed-by: Richard Henderson <rth@twiddle.net> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Emilio G. Cota <cota@braap.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* linux-user/main: support dfilterAlex Bennée2017-10-171-0/+7
| | | | | | | | | | | This adds the -dfilter support to linux-user. There is a minor checkpatch complaint about formatting which I've ignored for aesthetic reasons. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Riku Voipio <riku.voipio@linaro.org>
* linux-user: Tidy and enforce reserved_va initializationRichard Henderson2017-10-161-13/+25
| | | | | | | | | | | | | | | | | | | | | | We had a check using TARGET_VIRT_ADDR_SPACE_BITS to make sure that the allocation coming in from the command-line option was not too large, but that didn't include target-specific knowledge about other restrictions on user-space. Remove several target-specific hacks in linux-user/main.c. For MIPS and Nios, we can replace them with proper adjustments to the respective target's TARGET_VIRT_ADDR_SPACE_BITS definition. For ARM, we had no existing ifdef but I suspect that the current default value of 0xf7000000 was chosen with this in mind. Define a workable value in linux-user/arm/, and also document why the special case is required. Signed-off-by: Richard Henderson <rth@twiddle.net> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-Id: <20170708025030.15845-3-rth@twiddle.net> Signed-off-by: Riku Voipio <riku.voipio@linaro.org>
* cpu: make cpu_generic_init() abort QEMU on errorIgor Mammedov2017-09-191-4/+0Star
| | | | | | | | | | | | | | | | | | Almost every user of cpu_generic_init() checks for returned NULL and then reports failure in a custom way and aborts process. Some users assume that call can't fail and don't check for failure, though they should have checked for it. In either cases cpu_generic_init() failure is fatal, so instead of checking for failure and reporting it various ways, make cpu_generic_init() report errors in consistent way and terminate QEMU on failure. Signed-off-by: Igor Mammedov <imammedo@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <1505318697-77161-3-git-send-email-imammedo@redhat.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
* maint: Include bug-reporting info in --help outputEric Blake2017-08-081-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | | These days, many programs are including a bug-reporting address, or better yet, a link to the project web site, at the tail of their --help output. However, we were not very consistent at doing so: only qemu-nbd and qemu-qa mentioned anything, with the latter pointing to an individual person instead of the project. Add a new #define that sets up a uniform string, mentioning both bug reporting instructions and overall project details, and which a downstream vendor could tweak if they want bugs to go to a downstream database. Then use it in all of our binaries which have --help output. The canned text intentionally references http:// instead of https:// because our https website currently causes certificate errors in some browsers. That can be tweaked later once we have resolved the web site issued. Signed-off-by: Eric Blake <eblake@redhat.com> Reviewed-by: Daniel P. Berrange <berrange@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20170803163353.19558-5-eblake@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
* target/alpha: Merge several flag bytes into ENV->FLAGSRichard Henderson2017-07-191-11/+14
| | | | | | | | | The flags are arranged such that we can manipulate them either a whole, or as individual bytes. The computation within cpu_get_tb_cpu_state is now reduced to a single load and mask. Tested-by: Emilio G. Cota <cota@braap.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
* Merge remote-tracking branch 'mjt/tags/trivial-patches-fetch' into stagingStefan Hajnoczi2017-05-101-6/+3Star
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | trivial patches for 2017-05-10 # gpg: Signature made Wed 10 May 2017 03:19:30 AM EDT # gpg: using RSA key 0x701B4F6B1A693E59 # gpg: Good signature from "Michael Tokarev <mjt@tls.msk.ru>" # gpg: aka "Michael Tokarev <mjt@corpit.ru>" # gpg: aka "Michael Tokarev <mjt@debian.org>" # Primary key fingerprint: 6EE1 95D1 886E 8FFB 810D 4324 457C E0A0 8044 65C5 # Subkey fingerprint: 7B73 BAD6 8BE7 A2C2 8931 4B22 701B 4F6B 1A69 3E59 * mjt/tags/trivial-patches-fetch: (23 commits) tests: Remove redundant assignment MAINTAINERS: Update paths for AioContext implementation MAINTAINERS: Update paths for main loop jazz_led: fix bad snprintf tests: Ignore another built executable (test-hmp) scripts: Switch to more portable Perl shebang scripts/qemu-binfmt-conf.sh: Fix shell portability issue virtfs: allow a device id to be specified in the -virtfs option hw/core/generic-loader: Fix crash when running without CPU virtio-blk: Remove useless condition around g_free() qemu-doc: Fix broken URLs of amnhltm.zip and dosidle210.zip use _Static_assert in QEMU_BUILD_BUG_ON channel-file: fix wrong parameter comments block: Make 'replication_state' an enum util: Use g_malloc/g_free in envlist.c qga: fix compiler warnings (clang 5) device_tree: fix compiler warnings (clang 5) usb-ccid: make ccid_write_data_block() cope with null buffers tests: Ignore more test executables Add 'none' as type for drive's if option ... Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
| * util: Use g_malloc/g_free in envlist.cSaurav Sachidanand2017-05-071-6/+3Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Change malloc/strdup/free to g_malloc/g_strdup/g_free in util/envlist.c. Remove NULL checks for pointers returned from g_malloc and g_strdup as they exit in case of failure. Also, update calls to envlist_create to reflect this. Free array and array contents returned by envlist_to_environ using g_free in bsd-user/main.c and linux-user/main.c. Update comments to reflect change in semantics. Signed-off-by: Saurav Sachidanand <sauravsachidanand@gmail.com> Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
* | target/openrisc: implement shadow registersStafford Horne2017-05-041-9/+9
|/ | | | | | | | | | | | | | | | Shadow registers are part of the openrisc spec along with sr[cid], as part of the fast context switching feature. When exceptions occur, instead of having to save registers to the stack if enabled the CID will increment and a new set of registers will be available. This patch only implements shadow registers which can be used as extra scratch registers via the mfspr and mtspr if required. This is implemented in a way where it would be easy to add on the fast context switching, currently cid is hardcoded to 0. This is need for openrisc linux smp kernels to boot correctly. Signed-off-by: Stafford Horne <shorne@gmail.com>
* armv7m: Raise correct kind of UsageFault for attempts to execute ARM codePeter Maydell2017-02-281-0/+1
| | | | | | | | | | | M profile doesn't implement ARM, and the architecturally required behaviour for attempts to execute with the Thumb bit clear is to generate a UsageFault with the CFSR INVSTATE bit set. We were incorrectly implementing this as generating an UNDEFINSTR UsageFault; fix this. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
* target-ppc, tcg: fix usermode segfault with pthread_create()Sam Bobroff2017-02-221-1/+2
| | | | | | | | | | | | | | | Programs run under qemu-ppc64 on an x86_64 host currently segfault if they use pthread_create() due to the adjustment made to the NIP in commit bd6fefe71cec5a0c7d2be4ac96307f25db56abf9. This patch changes cpu_loop() to set the NIP back to the pre-incremented value before calling do_syscall(), which causes the correct address to be used for the new thread and corrects the fault. Signed-off-by: Sam Bobroff <sam.bobroff@au1.ibm.com> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
* target/openrisc: Keep SR_F in a separate variableRichard Henderson2017-02-131-2/+1Star
| | | | | | | This avoids having to keep merging and extracting the flag from SR. Reviewed-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Signed-off-by: Richard Henderson <rth@twiddle.net>
* linux-user: Fix openrisc cpu_loopRichard Henderson2017-02-131-54/+41Star
| | | | | | | We need to handle EXCP_DEBUG and EXCP_INTERRUPT. We need to send signals to the guest using queue_signal. Signed-off-by: Richard Henderson <rth@twiddle.net>
* target/s390x: use "qemu" cpu model in user modeDavid Hildenbrand2017-02-011-0/+2
| | | | | | | | | | | "any" does not exist, therefore resulting in a misleading error message. Reported-by: Stefan Weil <sw@weilnetz.de> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20170130145025.26475-1-david@redhat.com> Reviewed-by: Stefan Weil <sw@weilnetz.de> Reviewed-by: Alexander Graf <agraf@suse.de> Cc: qemu-stable@nongnu.org
* armv7m: Report no-coprocessor faults correctlyPeter Maydell2017-01-271-0/+1
| | | | | | | | | | | For v7M attempts to access a nonexistent coprocessor are reported differently from plain undefined instructions (as UsageFaults of type NOCP rather than type UNDEFINSTR). Split them out into a new EXCP_NOCP so we can report the FSR value correctly. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Message-id: 1485285380-10565-8-git-send-email-peter.maydell@linaro.org
* nios2: Add usermode binaries emulationMarek Vasut2017-01-241-2/+138
| | | | | | | | | | | | | | | Add missing bits for qemu-user required for emulating Altera Nios2 userspace binaries. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chris Wulff <crwulff@gmail.com> Cc: Jeff Da Silva <jdasilva@altera.com> Cc: Ley Foon Tan <lftan@altera.com> Cc: Sandra Loosemore <sandra@codesourcery.com> Cc: Yves Vandervennet <yvanderv@altera.com> Reviewed-by: Alexander Graf <agraf@suse.de> Message-Id: <20170118220146.489-4-marex@denx.de> Signed-off-by: Richard Henderson <rth@twiddle.net>
* linux-user: Add HPPA startup and main loopRichard Henderson2017-01-231-0/+172
| | | | | | Including support for the atomic memory op syscalls. Signed-off-by: Richard Henderson <rth@twiddle.net>
* linux-user: Support stack-grows-up in elfload.cRichard Henderson2017-01-231-6/+7
| | | | | | | | | HPPA is a (the) stack-grows-up target, and supporting that requires rearranging how we compute addresses while laying out the initial program stack. In addition, hppa32 requires 64-byte stack alignment so parameterize that as well. Signed-off-by: Richard Henderson <rth@twiddle.net>
* target-sparc: use SparcV9MMU type for sparc64 I/D-MMUsArtyom Tarasenko2017-01-181-1/+1
| | | | Signed-off-by: Artyom Tarasenko <atar4qemu@gmail.com>
* target-m68k: add 680x0 divu/divs variantsLaurent Vivier2016-12-271-0/+7
| | | | | | | | | Update helper to set the throwing location in case of div-by-0. Cleanup divX.w and add quad word variants of divX.l. Signed-off-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Richard Henderson <rth@twidle.net> [laurent: modified to clear Z on overflow, as found with risu]
* target-alpha: Emulate LL/SC using cmpxchg helpersRichard Henderson2016-10-261-49/+0Star
| | | | | | | | | Emulating LL/SC with cmpxchg is not correct, since it can suffer from the ABA problem. However, portable parallel code is written assuming only cmpxchg which means that in practice this is a viable alternative. Signed-off-by: Richard Henderson <rth@twiddle.net>
* linux-user: remove handling of aarch64's EXCP_STREXEmilio G. Cota2016-10-261-125/+0Star
| | | | | | | | | The exception is not emitted anymore. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Emilio G. Cota <cota@braap.org> Signed-off-by: Richard Henderson <rth@twiddle.net> Message-Id: <1467054136-10430-30-git-send-email-cota@braap.org>
* linux-user: remove handling of ARM's EXCP_STREXEmilio G. Cota2016-10-261-93/+0Star
| | | | | | | | | The exception is not emitted anymore. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Emilio G. Cota <cota@braap.org> Signed-off-by: Richard Henderson <rth@twidle.net> Message-Id: <1467054136-10430-29-git-send-email-cota@braap.org>
* tcg: Add EXCP_ATOMICRichard Henderson2016-10-261-0/+45
| | | | | | | | | | When we cannot emulate an atomic operation within a parallel context, this exception allows us to stop the world and try again in a serial context. Reviewed-by: Emilio G. Cota <cota@braap.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
* target-arm: Implement new HLT trap for semihostingPeter Maydell2016-10-241-0/+3
| | | | | | | | | | | | Version 2.0 of the semihosting specification introduces new trap instructions for AArch32: HLT 0xF000 for A32 and HLT 0x3C for T32. Implement these (in the same way we implement the existing HLT semihosting trap for A64). The old traps via SVC and BKPT are unaffected. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1476792973-18508-1-git-send-email-peter.maydell@linaro.org
* Put the copyright information on a separate lineThomas Huth2016-10-241-1/+1
| | | | | | | | | | | | The output string QEMU with "--version" is very long, it does not fit into a normal line of a terminal window anymore. By putting the copyright information on a separate line instead, the output looks much nicer. Signed-off-by: Thomas Huth <thuth@redhat.com> Message-Id: <1475661284-30153-1-git-send-email-thuth@redhat.com> Reviewed-by: Eric Blake <eblake@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
* linux-user: Update mips_syscall_args[] array in main.cAleksandar Markovic2016-10-211-2/+22
| | | | | | | | | Array mips_syscall_args[] determines number of arguments for each syscall on Mips32. It wasn't updated with newer syscalls. Also, preadv and pwritev have 5 arguments, not 6. Signed-off-by: Aleksandar Markovic <aleksandar.markovic@imgtec.com> Signed-off-by: Riku Voipio <riku.voipio@linaro.org>
* trace: provide mechanism for registering trace eventsDaniel P. Berrange2016-10-121-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | Remove the notion of there being a single global array of trace events, by introducing a method for registering groups of events. The module_call_init() needs to be invoked at the start of any program that wants to make use of the trace support. Currently this covers system emulators qemu-nbd, qemu-img and qemu-io. [Squashed the following fix from Daniel P. Berrange <berrange@redhat.com>: linux-user/bsd-user: initialize trace events subsystem The bsd-user/linux-user programs make use of the CPU emulation code and this now requires that the trace events subsystem is enabled, otherwise it'll crash trying to allocate an empty trace events bitmap for the CPU object. --Stefan] Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com> Reviewed-by: Lluís Vilanova <vilanova@ac.upc.edu> Signed-off-by: Daniel P. Berrange <berrange@redhat.com> Message-id: 1475588159-30598-14-git-send-email-berrange@redhat.com Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
* Merge remote-tracking branch 'remotes/stefanha/tags/tracing-pull-request' ↵Peter Maydell2016-09-291-1/+0Star
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | into staging # gpg: Signature made Wed 28 Sep 2016 22:30:45 BST # gpg: using RSA key 0x9CA4ABB381AB73C8 # gpg: Good signature from "Stefan Hajnoczi <stefanha@redhat.com>" # gpg: aka "Stefan Hajnoczi <stefanha@gmail.com>" # Primary key fingerprint: 8695 A8BF D3F9 7CDA AC35 775A 9CA4 ABB3 81AB 73C8 * remotes/stefanha/tags/tracing-pull-request: trace: Document the execution mode of guest events trace: Add event "guest_cpu_reset" trace: Add event "guest_cpu_enter" trace: Properly initialize dynamic event states in hot-plugged vCPUs trace: move hw/virtio/virtio-balloon.c trace points into correct file trace: move hw/mem/pc-dimm.c trace points into correct file trace: move util/qemu-coroutine*.c trace points into correct file trace: move util/buffer.c trace points into correct file Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * trace: Properly initialize dynamic event states in hot-plugged vCPUsLluís Vilanova2016-09-281-1/+0Star
| | | | | | | | | | | | | | | | | | | | Every time a vCPU is hot-plugged, it will "inherit" its tracing state from the global state array. That is, if *any* existing vCPU has an event enabled, new vCPUs will have too. Signed-off-by: Lluís Vilanova <vilanova@ac.upc.edu> Message-id: 147428970768.15111.7664565956870423529.stgit@fimbulvetr.bsc.es Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
* | cpus-common: move exclusive work infrastructure from linux-userPaolo Bonzini2016-09-271-87/+0Star
| | | | | | | | | | | | | | | | | | | | | | | | This will serve as the base for async_safe_run_on_cpu. Because start_exclusive uses CPU_FOREACH, merge exclusive_lock with qemu_cpu_list_lock: together with a call to exclusive_idle (via cpu_exec_start/end) in cpu_list_add, this protects exclusive work against concurrent CPU addition and removal. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
* | cpus-common: move CPU work item management to common codeSergey Fedorov2016-09-271-0/+25
| | | | | | | | | | | | | | | | | | | | | | | | | | Make CPU work core functions common between system and user-mode emulation. User-mode does not use run_on_cpu, so do not implement it. Signed-off-by: Sergey Fedorov <serge.fdrv@gmail.com> Signed-off-by: Sergey Fedorov <sergey.fedorov@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <1470158864-17651-10-git-send-email-alex.bennee@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
* | cpus-common: move CPU list management to common codePaolo Bonzini2016-09-271-13/+4Star
| | | | | | | | | | | | | | | | | | | | Add a mutex for the CPU list to system emulation, as it will be used to manage safe work. Abstract manipulation of the CPU list in new functions cpu_list_add and cpu_list_remove. Reviewed-by: Richard Henderson <rth@twiddle.net> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
* | linux-user: Add qemu_cpu_is_self() and qemu_cpu_kick()Sergey Fedorov2016-09-271-0/+10
| | | | | | | | | | | | | | | | | | | | Signed-off-by: Sergey Fedorov <serge.fdrv@gmail.com> Signed-off-by: Sergey Fedorov <sergey.fedorov@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <1470158864-17651-9-git-send-email-alex.bennee@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
* | linux-user: Use QemuMutex and QemuCondSergey Fedorov2016-09-271-23/+32
|/ | | | | | | | | | | | | | Convert pthread_mutex_t and pthread_cond_t to QemuMutex and QemuCond. This will allow to make some locks and conditional variables common between user and system mode emulation. Signed-off-by: Sergey Fedorov <serge.fdrv@gmail.com> Signed-off-by: Sergey Fedorov <sergey.fedorov@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <1470158864-17651-7-git-send-email-alex.bennee@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
* ppc: Fix signal delivery in ppc-user and ppc64-userBenjamin Herrenschmidt2016-09-231-1/+1
| | | | | | | | | | | | | | | | | | | | | There were a number of bugs in the implementation: - The structure alignment was wrong for 64-bit. - Also 64-bit only does RT signals. - On 64-bit, we need to put a pointer to the (aligned) vector registers in the frame and use it for restoring - We had endian bugs when saving/restoring vector registers - My recent fixes for exception NIP broke sigreturn in user mode causing us to resume one instruction too far. - Add VSR second halves Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
* linux-user: Pass si_type information to queue_signal() explicitlyPeter Maydell2016-09-211-62/+62
| | | | | | | | | | | | Instead of assuming in queue_signal() that all callers are passing a siginfo structure which uses the _sifields._sigfault part of the union (and thus a si_type of QEMU_SI_FAULT), make callers pass the si_type they require in as an argument. [RV adjusted to apply] Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Riku Voipio <riku.voipio@linaro.org>
* linux-user: ppc64: set MSR_CM bit for BookE 2.06 MMUMichael Walle2016-09-211-2/+3
| | | | | | | | | | | 64 bit user mode doesn't work for the e5500 core because the MSR_CM bit is not set which enables the 64 bit mode for this MMU model. Memory addresses are truncated to 32 bit, which results in "Invalid data memory access" error messages. Fix it by setting the MSR_CM bit for this MMU model. Signed-off-by: Michael Walle <michael@walle.cc> Reviewed-by: Alexander Graf <agraf@suse.de> Signed-off-by: Riku Voipio <riku.voipio@linaro.org>
* linux-user, trivial: display "0x%x" instead of "0x%d"Laurent Vivier2016-09-131-1/+1
| | | | | | | | | | Display an exception number, generally defined as an hexadecimal number (for instance, EXCP_HLT is 0x10001). Signed-off-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Eric Blake <eblake@redhat.com> Acked-by: Riku Voipio <riku.voipio@linaro.org> Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
* ppc: Stop dumping state on all exceptions in linux-userBenjamin Herrenschmidt2016-09-071-12/+0Star
| | | | | | | | | Other archs don't do it, some programs catch signals just fine and those dumps just clutter the output. Keep the dumps for cases that aren't supposed to happen such as unknown codes. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
* ppc: Fix catching some segfaults in user modeBenjamin Herrenschmidt2016-09-071-0/+1
| | | | | | | | | | The usermode "translate" code generates an error code value that has the "is_write" bit set, which causes our switch/case to miss and display "Invalid segfault errno" and a spurrious second state dump. Fix it. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
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