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* arm: translate.c: Fix smlald InstructionPeter Crosthwaite2014-04-171-11/+23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The smlald (and probably smlsld) instruction was doing incorrect sign extensions of the operands amongst 64bit result calculation. The instruction psuedo-code is: operand2 = if m_swap then ROR(R[m],16) else R[m]; product1 = SInt(R[n]<15:0>) * SInt(operand2<15:0>); product2 = SInt(R[n]<31:16>) * SInt(operand2<31:16>); result = product1 + product2 + SInt(R[dHi]:R[dLo]); R[dHi] = result<63:32>; R[dLo] = result<31:0>; The result calculation should be done in 64 bit arithmetic, and hence product1 and product2 should be sign extended to 64b before calculation. The current implementation was adding product1 and product2 together then sign-extending the intermediate result leading to false negatives. E.G. if product1 = product2 = 0x4000000, their sum = 0x80000000, which will be incorrectly interpreted as -ve on sign extension. We fix by doing the 64b extensions on both product1 and product2 before any addition/subtraction happens. We also fix where we were possibly incorrectly setting the Q saturation flag for SMLSLD, which the ARM ARM specifically says is not set. Reported-by: Christina Smith <christina.smith@xilinx.com> Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 2cddb6f5a15be4ab8d2160f3499d128ae93d304d.1397704570.git.peter.crosthwaite@xilinx.com Cc: qemu-stable@nongnu.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* target-arm: Dump 32-bit CPU state if 64 bit CPU is in AArch32Peter Maydell2014-04-171-0/+5
| | | | | | | | | | | | | For system mode, we may have a 64 bit CPU which is currently executing in AArch32 state; if we're dumping CPU state to the logs we should therefore show the correct state for the current execution state, rather than hardwiring it based on the type of the CPU. For consistency with how we handle translation, we leave the 32 bit dump function as the default, and have it hand off control to the 64 bit dump code if we're in AArch64 mode. Reported-by: Rob Herring <rob.herring@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* target-arm: Implement ARMv8 MVFR registersPeter Maydell2014-04-171-2/+8
| | | | | | | | | | | | For ARMv8 there are two changes to the MVFR media feature registers: * there is a new MVFR2 which is accessible from 32 bit code * 64 bit code accesses these via the usual sysreg instructions rather than with a floating-point specific instruction Implement this. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
* target-arm: Fix VFP enables for AArch32 EL0 under AArch64 EL1Peter Maydell2014-04-171-0/+31
| | | | | | | | | | | | | | | | | | | | | | | The current A32/T32 decoder bases its "is VFP/Neon enabled?" check on the FPSCR.EN bit. This is correct if EL1 is AArch32, but for an AArch64 EL1 the logic is different: it must act as if FPSCR.EN is always set. Instead, trapping must happen according to CPACR bits for cp10/cp11; these cover all of FP/Neon, including the FPSCR/FPSID/MVFR register accesses which FPSCR.EN does not affect. Add support for CPACR checks (which are also required for ARMv7, but were unimplemented because Linux happens not to use them) and make sure they generate exceptions with the correct syndrome. We actually return incorrect syndrome information for cases where FP is disabled but the specific instruction bit pattern is unallocated: strictly these should be the Uncategorized exception, not a "SIMD disabled" exception. This should be mostly harmless, and the structure of the A32/T32 VFP/Neon decoder makes it painful to put the 'FP disabled?' checks in the right places. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
* target-arm: Add support for generating exceptions with syndrome informationPeter Maydell2014-04-171-38/+65
| | | | | | | | | | | | | | | Add new helpers exception_with_syndrome (for generating an exception with syndrome information) and exception_uncategorized (for generating an exception with "Unknown or Uncategorized Reason", which have a syndrome register value of zero), and use them to generate the correct syndrome information for exceptions which are raised directly from generated code. This patch includes moving the A32/T32 gen_exception_insn functions further up in the source file; they will be needed for "VFP/Neon disabled" exception generation later. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
* target-arm: Provide correct syndrome information for cpreg access trapsPeter Maydell2014-04-171-1/+44
| | | | | | | | | | | | For exceptions taken to AArch64, if a coprocessor/system register access fails due to a trap or enable bit then the syndrome information must include details of the failing instruction (crn/crm/opc1/opc2 fields, etc). Make the decoder construct the syndrome information at translate time so it can be passed at runtime to the access-check helper function and used as required. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
* target-arm: Split out private-to-target functions into internals.hPeter Maydell2014-04-171-0/+1
| | | | | | | | | | Currently cpu.h defines a mixture of functions and types needed by the rest of QEMU and those needed only by files within target-arm/. Split the latter out into a new header so they aren't needlessly exposed further than required. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
* target-arm: A64: Add [UF]RSQRTE (reciprocal root estimate)Alex Bennée2014-03-171-2/+10
| | | | | | | | | | | | | This adds support for [UF]RSQRTE instructions. It utilises the existing NEON helpers with some changes. The changes include an explicit passing of fpstatus (so the correct one is used between arm32 and aarch64), denormilzation, more correct error handling and also proper scaling of the fraction going into the estimate. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net> Message-id: 1394822294-14837-25-git-send-email-peter.maydell@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* target-arm: A64: Implement AdvSIMD reciprocal estimate insns URECPE, FRECPEAlex Bennée2014-03-171-2/+10
| | | | | | | | | | | | | | | Implement URECPE and FRECPE instructions in both scalar and vector forms. The actual reciprocal estimate function is shared with the A32/T32 Neon code. However in A64 we aren't using the Neon "standard FPSCR value" so extra checks are necessary to handle non-squashed denormal inputs which can never happen for A32/T32. Calling conventions for the helpers are thus modified to pass the fpst directly; we mark the helpers as TCG_CALL_NO_RWG since we're changing the declarations anyway. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net> Message-id: 1394822294-14837-21-git-send-email-peter.maydell@linaro.org
* target-arm: A64: Implement PMULL instructionPeter Maydell2014-03-171-0/+1
| | | | | | | | | | | | | | | Implement the PMULL instruction; this is the last unimplemented insn in the three-reg-diff group. Note that PMULL with size 3 is considered part of the AES part of the crypto extensions (see the ID_AA64ISAR0_EL1 register definition in the v8 ARM ARM), so it isn't necessary to burn an extra feature bit on it, even though we're using more feature bits than a single "crypto extension present/not present" toggle. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net> Message-id: 1394822294-14837-2-git-send-email-peter.maydell@linaro.org
* exec: Change cpu_abort() argument to CPUStateAndreas Färber2014-03-131-1/+1
| | | | Signed-off-by: Andreas Färber <afaerber@suse.de>
* cpu: Move breakpoints field from CPU_COMMON to CPUStateAndreas Färber2014-03-131-2/+2
| | | | | | | | Most targets were using offsetof(CPUFooState, breakpoints) to determine how much of CPUFooState to clear on reset. Use the next field after CPU_COMMON instead, if any, or sizeof(CPUFooState) otherwise. Signed-off-by: Andreas Färber <afaerber@suse.de>
* target-arm: Implement WFE as a yield operationPeter Maydell2014-03-101-0/+6
| | | | | | | | | | | | | | | Implement WFE to yield our timeslice to the next CPU. This avoids slowdowns in multicore configurations caused by one core busy-waiting on a spinlock which can't possibly be unlocked until the other core has an opportunity to run. This speeds up my test case A15 dual-core boot by a factor of three (though it is still four or five times slower than a single-core boot). Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1393339545-22111-1-git-send-email-peter.maydell@linaro.org Reviewed-by: Richard Henderson <rth@twiddle.net> Tested-by: Rob Herring <rob.herring@linaro.org>
* target-arm: Add support for AArch32 ARMv8 CRC32 instructionsWill Newton2014-02-261-0/+56
| | | | | | | | | | | | | | Add support for AArch32 CRC32 and CRC32C instructions added in ARMv8 and add a CPU feature flag to enable these instructions. The CRC32-C implementation used is the built-in qemu implementation and The CRC-32 implementation is from zlib. This requires adding zlib to LIBS to ensure it is linked for the linux-user binary. Signed-off-by: Will Newton <will.newton@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1393411566-24104-3-git-send-email-will.newton@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* target-arm: Remove unnecessary code now read/write fns can't failPeter Maydell2014-02-201-4/+0Star
| | | | | | | | Now that cpreg read and write functions can't fail and throw an exception, we can remove the code from the translator that synchronises the guest PC in case an exception is thrown. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* target-arm: Split cpreg access checks out from read/write functionsPeter Maydell2014-02-201-0/+11
| | | | | | | | | | | | | | | | | | | | | | | | | Several of the system registers handled via the ARMCPRegInfo mechanism have access trap control bits controlling whether the registers are accessible to lower privilege levels. Replace the existing mechanism (allowing the read and write functions to return EXCP_UDEF if access is denied) with a dedicated "check access rights" function pointer in the ARMCPRegInfo. This will allow us to simplify some of the register definitions, which no longer need read/write functions purely to handle the access checks. We take the opportunity to define the return value from the access checking function in a way that allows us to set the correct exception syndrome information for exceptions taken to AArch64 (which may need to distinguish access failures due to a configurable trap or enable from other kinds of access failure). This commit defines the new mechanism but does not move any of the registers across to use it. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
* target-arm: Log bad system register accesses with LOG_UNIMPPeter Maydell2014-02-201-0/+13
| | | | | | | | | | | Log guest attempts to access unimplemented system registers via the LOG_UNIMP reporting mechanism (for both the 32 bit and 64 bit instruction sets). This is particularly useful for debugging problems where the guest is trying to use a system register that QEMU doesn't implement. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
* target-arm: Add support for AArch32 64bit VCVTB and VCVTTWill Newton2014-02-081-22/+61
| | | | | | | | | Add support for the AArch32 floating-point half-precision to double- precision conversion VCVTB and VCVTT instructions. Signed-off-by: Will Newton <will.newton@linaro.org> [PMM: fixed a minor missing-braces style issue] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* target-arm: Add AArch32 SIMD VCVTA, VCVTN, VCVTP and VCVTMWill Newton2014-01-311-1/+52
| | | | | | | | Add support for the AArch32 Advanced SIMD VCVTA, VCVTN, VCVTP and VCVTM instructions. Signed-off-by: Will Newton <will.newton@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* target-arm: Add AArch32 FP VCVTA, VCVTN, VCVTP and VCVTMWill Newton2014-01-311-0/+61
| | | | | | | | Add support for the AArch32 floating-point VCVTA, VCVTN, VCVTP and VCVTM instructions. Signed-off-by: Will Newton <will.newton@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* target-arm: Add AArch32 SIMD VRINTA, VRINTN, VRINTP, VRINTM, VRINTZWill Newton2014-01-311-1/+39
| | | | | | | | Add support for the AArch32 Advanced SIMD VRINTA, VRINTN, VRINTP VRINTM and VRINTZ instructions. Signed-off-by: Will Newton <will.newton@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* target-arm: Add support for AArch32 SIMD VRINTXWill Newton2014-01-311-1/+10
| | | | | | | | Add support for the AArch32 Advanced SIMD VRINTX instruction. Signed-off-by: Will Newton <will.newton@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* target-arm: Add support for AArch32 FP VRINTXWill Newton2014-01-311-0/+11
| | | | | | | Add support for the AArch32 floating-point VRINTX instruction. Signed-off-by: Will Newton <will.newton@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* target-arm: Add support for AArch32 FP VRINTZWill Newton2014-01-311-0/+16
| | | | | | | Add support for the AArch32 floating-point VRINTZ instruction. Signed-off-by: Will Newton <will.newton@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* target-arm: Add support for AArch32 FP VRINTRWill Newton2014-01-311-0/+11
| | | | | | | Add support for the AArch32 floating-point VRINTR instruction. Signed-off-by: Will Newton <will.newton@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* target-arm: Add AArch32 FP VRINTA, VRINTN, VRINTP and VRINTMWill Newton2014-01-311-0/+54
| | | | | | | | Add support for AArch32 ARMv8 FP VRINTA, VRINTN, VRINTP and VRINTM instructions. Signed-off-by: Will Newton <will.newton@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* target-arm: Rename A32 VFP conversion helpersWill Newton2014-01-081-11/+13
| | | | | | | | | | The VFP conversion helpers for A32 round to zero as this is the only rounding mode supported. Rename these helpers to make it clear that they round to zero and are not suitable for use in the AArch64 code. Signed-off-by: Will Newton <will.newton@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net>
* target-arm: Use VFP_BINOP macro for min, max, minnum, maxnumPeter Maydell2014-01-081-8/+8
| | | | | | | | | Use the VFP_BINOP macro to provide helpers for min, max, minnum and maxnum, rather than hand-rolling them. (The float64 max version is not used by A32 but will be needed for A64.) Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net>
* target-arm: Widen exclusive-access support struct fields to 64 bitsPeter Maydell2014-01-081-26/+39
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In preparation for adding support for A64 load/store exclusive instructions, widen the fields in the CPU state struct that deal with address and data values for exclusives from 32 to 64 bits. Although in practice AArch64 and AArch32 exclusive accesses will be generally separate there are some odd theoretical corner cases (eg you should be able to do the exclusive load in AArch32, take an exception to AArch64 and successfully do the store exclusive there), and it's also easier to reason about. The changes in semantics for the variables are: exclusive_addr -> extended to 64 bits; -1ULL for "monitor lost", otherwise always < 2^32 for AArch32 exclusive_val -> extended to 64 bits. 64 bit exclusives in AArch32 now use the high half of exclusive_val instead of a separate exclusive_high exclusive_high -> is no longer used in AArch32; extended to 64 bits as it will be needed for AArch64's pair-of-64-bit-values exclusives. exclusive_test -> extended to 64 bits, as it is an address. Since this is a linux-user-only field, in arm-linux-user it will always have the top 32 bits zero. exclusive_info -> stays 32 bits, as it is neither data nor address, but simply holds register indexes etc. AArch64 will be able to fit all its information into 32 bits as well. Note that the refactoring of gen_store_exclusive() coincidentally fixes a minor bug where ldrexd would incorrectly update the first CPU register even if the load for the second register faulted. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net>
* target-arm: Remove ARMCPU/CPUARMState from cpregs APIs used by decoderPeter Maydell2014-01-071-3/+4
| | | | | | | | | | | | | The cpregs APIs used by the decoder (get_arm_cp_reginfo() and cp_access_ok()) currently take either a CPUARMState* or an ARMCPU*. This is problematic for the A64 decoder, which doesn't pass the environment pointer around everywhere the way the 32 bit decoder does. Adjust the parameters these functions take so that we can copy only the relevant info from the CPUARMState into the DisasContext and then use that. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net>
* target-arm: A64: add support for conditional branchesAlexander Graf2013-12-171-5/+9
| | | | | | | | | | | This patch adds emulation for the conditional branch (b.cond) instruction. Signed-off-by: Alexander Graf <agraf@suse.de> [claudio: adapted to new decoder structure, reused arm infrastructure for checking the flags] Signed-off-by: Claudio Fontana <claudio.fontana@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net>
* target-arm: Split A64 from A32/T32 gen_intermediate_code_internal()Peter Maydell2013-12-171-38/+24Star
| | | | | | | | | | | | | | | | | | | | | | The A32/T32 gen_intermediate_code_internal() is complicated because it has to deal with: * conditionally executed instructions * Thumb IT blocks * kernel helper page * M profile exception-exit special casing None of these apply to A64, so putting the "this is A64 so call the A64 decoder" check in the middle of the A32/T32 loop is confusing and means the A64 decoder's handling of things like conditional jump and singlestepping has to take account of the conditional-execution jumps the main loop might emit. Refactor the code to give A64 its own gen_intermediate_code_internal function instead. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net>
* target-arm: add support for v8 AES instructionsArd Biesheuvel2013-12-171-0/+26
| | | | | | | | | This adds support for the AESE/AESD/AESMC/AESIMC instructions that are available on some v8 implementations of Aarch32. Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Message-id: 1386266078-6976-1-git-send-email-ard.biesheuvel@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* target-arm: Use new qemu_ld/st opcodesRichard Henderson2013-12-101-31/+25Star
| | | | | | | | | Retain the existing gen_aa32_* inlines, to aid compilation for A64. Cc: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net> Message-id: 1386628626-21627-1-git-send-email-rth@twiddle.net Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* target-arm: Implement ARMv8 SIMD VMAXNM and VMINNM instructions.Will Newton2013-12-101-9/+22
| | | | | | | | | This adds support for the ARMv8 Advanced SIMD VMAXNM and VMINNM instructions. Signed-off-by: Will Newton <will.newton@linaro.org> Message-id: 1386158099-9239-7-git-send-email-will.newton@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* target-arm: Implement ARMv8 FP VMAXNM and VMINNM instructions.Will Newton2013-12-101-0/+50
| | | | | | | | | | This adds support for the ARMv8 floating point VMAXNM and VMINNM instructions. Signed-off-by: Will Newton <will.newton@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1386158099-9239-6-git-send-email-will.newton@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* target-arm: Implement ARMv8 VSEL instruction.Will Newton2013-12-101-1/+134
| | | | | | | | | | This adds support for the VSEL floating point selection instruction which was added in ARMv8. Signed-off-by: Will Newton <will.newton@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1386158099-9239-3-git-send-email-will.newton@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* target-arm: Move call to disas_vfp_insn out of disas_coproc_insn.Will Newton2013-12-101-5/+27
| | | | | | | | | | | Floating point is an extension to the instruction set rather than a coprocessor, so call it directly from the ARM and Thumb decode functions. Signed-off-by: Will Newton <will.newton@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1386158099-9239-2-git-send-email-will.newton@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* tcg: Move helper registration into tcg_context_initRichard Henderson2013-10-101-3/+0Star
| | | | | | No longer needs to be done on a per-target basis. Signed-off-by: Richard Henderson <rth@twiddle.net>
* target-arm: Add AArch64 translation stubAlexander Graf2013-09-101-3/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | We should translate AArch64 mode separately from AArch32 mode. In AArch64 mode, registers look vastly different, instruction encoding is completely different, basically the system turns into a different machine. So let's do a simple if() in translate.c to decide whether we can handle the current code in the legacy AArch32 code or in the new AArch64 code. So far, the translation always complains about unallocated instructions. There is no emulator functionality in this patch! Signed-off-by: Alexander Graf <agraf@suse.de> Signed-off-by: John Rigby <john.rigby@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1378235544-22290-11-git-send-email-peter.maydell@linaro.org Message-id: 1368505980-17151-5-git-send-email-john.rigby@linaro.org [PMM: * provide no-op versions of a64 functions ifndef TARGET_AARCH64; this lets us avoid #ifdefs in translate.c * insert the missing call to disas_a64_insn() * stash the insn in the DisasContext rather than reloading it in real_unallocated_encoding() ] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* target-arm: Prepare translation for AArch64 codeAlexander Graf2013-09-101-9/+29
| | | | | | | | | | | | | | | | | | | | | | | | This patch adds all the prerequisites for AArch64 support that didn't fit into split up patches. It extends important bits in the core cpu headers to also take AArch64 mode into account. Add new ARM_TBFLAG_AARCH64_STATE translation buffer flag indicate an ARMv8 cpu running in aarch64 mode vs aarch32 mode. Signed-off-by: Alexander Graf <agraf@suse.de> Signed-off-by: John Rigby <john.rigby@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1378235544-22290-10-git-send-email-peter.maydell@linaro.org Message-id: 1368505980-17151-4-git-send-email-john.rigby@linaro.org [PMM: * rearranged tbflags so AArch64? is bit 31 and if it is set then 30..0 are freely available for whatever makes most sense for that mode * added version bump since we change VFP migration state * added a comment about how VFP/Neon register state works * physical address space is 48 bits, not 64 * added ARM_FEATURE_AARCH64 flag to identify 64-bit capable CPUs ] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* target-arm: Pass DisasContext* to gen_set_pc_im()Peter Maydell2013-09-101-13/+13
| | | | | | | | | We want gen_set_pc_im() to work for both AArch64 and AArch32, but to do this we'll need the DisasContext* so we can tell which mode we're in, so pass it in as a parameter. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1378235544-22290-7-git-send-email-peter.maydell@linaro.org
* target-arm: Fix target_ulong/uint32_t confusionsAlexander Graf2013-09-101-4/+5
| | | | | | | | | | | | | Correct a few places that were using uint32_t or a 32 bit only format string to handle something that should be a target_ulong. Signed-off-by: Alexander Graf <agraf@suse.de> Signed-off-by: John Rigby <john.rigby@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1378235544-22290-6-git-send-email-peter.maydell@linaro.org [PMM: split out to separate patch; added gen_goto_tb() and gen_set_pc_im() dest params to list of things to change.] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* target-arm: Export cpu_envAlexander Graf2013-09-101-1/+1
| | | | | | | | | | | | The cpu_env tcg variable will be used by both the AArch32 and AArch64 handling code. Unstaticify it, so that both sides can make use of it. Signed-off-by: Alexander Graf <agraf@suse.de> Signed-off-by: John Rigby <john.rigby@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1378235544-22290-5-git-send-email-peter.maydell@linaro.org Message-id: 1368505980-17151-3-git-send-email-john.rigby@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* target-arm: Extract the disas struct to a header fileAlexander Graf2013-09-101-23/+1Star
| | | | | | | | | | | | We will need to share the disassembly status struct between AArch32 and AArch64 modes. So put it into a header file that both sides can use. Signed-off-by: Alexander Graf <agraf@suse.de> Signed-off-by: John Rigby <john.rigby@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1378235544-22290-4-git-send-email-peter.maydell@linaro.org Message-id: 1368505980-17151-2-git-send-email-john.rigby@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* target-arm: Abstract out load/store from a vaddr in AArch32Peter Maydell2013-09-101-124/+210
| | | | | | | | | | | | | | | AArch32 code (ie traditional 32 bit world) expects to be able to pass a vaddr in a TCGv_i32. However when QEMU is compiled with TARGET_LONG_BITS=32 the TCG load/store functions take a TCGv_i64. Abstract out load/store with a 32 bit vaddr so we have a place to put the zero extension of the vaddr and the extension/truncation of the data value. Apart from the function definitions most of this patch is a simple s/tcg_gen_qemu_/gen_aa32_/. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1378235544-22290-3-git-send-email-peter.maydell@linaro.org
* target-arm: Use sextract32() in branch decodePeter Maydell2013-09-101-2/+3
| | | | | | | | | | | | In the decode of ARM B and BL insns, swap the order of the "append 2 implicit zeros to imm24" and the sign extend, and use the new sextract32() utility function to do the latter. This avoids a direct dependency on the undefined C behaviour of shifting into the sign bit of an integer. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net> Message-id: 1378391908-22137-2-git-send-email-peter.maydell@linaro.org
* Merge remote-tracking branch 'mjt/trivial-patches' into stagingAnthony Liguori2013-09-031-0/+4
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | # By Stefan Weil (6) and others # Via Michael Tokarev * mjt/trivial-patches: aio / timers: use g_usleep() not sleep() adlib: sort offsets in portio registration qmp: fix integer usage in examples tci: Remove function tcg_out64 (fix broken build) target-arm: Report unimplemented opcodes (LOG_UNIMP) pflash_cfi02.c: fix debug macro configure: Remove unneeded redirections of stderr (pkg-config --exists) configure: Remove unneeded redirections of stderr (pkg-config --cflags, --libs) configure: Don't write .pyc files by default (python -B) curl: qemu_bh_new() can never return NULL slirp/arp_table.c: Avoid shifting into sign bit of signed integers configure: disable clang -Wstring-plus-int warning rdma: silly ipv6 bugfix misc: Fix some typos in names and comments slirp: Port redirection option behave differently on Linux and Windows Message-id: 1378119695-14568-1-git-send-email-mjt@msgid.tls.msk.ru Signed-off-by: Anthony Liguori <anthony@codemonkey.ws>
| * target-arm: Report unimplemented opcodes (LOG_UNIMP)Stefan Weil2013-09-011-0/+4
| | | | | | | | | | | | | | | | | | | | These unimplemented opcodes are handled like illegal opcodes, but they are used in existing code. We should at least report when they are executed. Signed-off-by: Stefan Weil <sw@weilnetz.de> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
* | tcg: Change tcg_gen_exit_tb argument to uintptr_tRichard Henderson2013-09-021-1/+1
|/ | | | | | | And update all users. Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
generated by cgit v1.2.3-55-g7522 (git 2.39.0) at 2025-02-01 20:56:14 +0100