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* target-arm: Add Hyp mode checks to bad_mode_switch()Peter Maydell2016-02-261-0/+3
* target-arm: Add comment about not implementing NSACR.RFRPeter Maydell2016-02-261-0/+3
* target-arm: In cpsr_write() ignore mode switches from User modePeter Maydell2016-02-261-0/+1
* target-arm: Raw CPSR writes should skip checks and bank switchingPeter Maydell2016-02-264-6/+7
* target-arm: Add write_type argument to cpsr_write()Peter Maydell2016-02-267-10/+20
* target-arm: Give CPSR setting on 32-bit exception return its own helperPeter Maydell2016-02-263-3/+10
* all: Clean up includesPeter Maydell2016-02-232-2/+0Star
* target-arm: Add PMUSERENR_EL0 registerAlistair Francis2016-02-181-0/+6
* target-arm: Add the pmovsclr_el0 and pmintenclr_el1 registersAlistair Francis2016-02-181-0/+12
* target-arm: Add the pmceid0 and pmceid1 registersAlistair Francis2016-02-184-0/+22
* target-arm: UNDEF in the UNPREDICTABLE SRS-from-System casePeter Maydell2016-02-182-4/+13
* target-arm: Combine user-only and softmmu get/set_r13_banked()Peter Maydell2016-02-181-19/+0Star
* target-arm: Move bank_number() into internals.hPeter Maydell2016-02-182-26/+25Star
* target-arm: Move get/set_r13_banked() to op_helper.cPeter Maydell2016-02-182-33/+37
* target-arm: Clean up trap/undef handling of SRSPeter Maydell2016-02-181-5/+61
* target-arm: Report correct syndrome for FPEXC32_EL2 trapsPeter Maydell2016-02-183-2/+20
* target-arm: Implement MDCR_EL3.TDA and MDCR_EL2.TDA trapsPeter Maydell2016-02-181-9/+30
* target-arm: Implement MDCR_EL2.TDRA trapsPeter Maydell2016-02-181-3/+24
* target-arm: Implement MDCR_EL3.TDOSA and MDCR_EL2.TDOSA trapsPeter Maydell2016-02-182-1/+34
* target-arm: Fix handling of SCR.SMDPeter Maydell2016-02-181-5/+7
* target-arm: correct CNTFRQ access rightsPeter Maydell2016-02-182-3/+38
* target-arm: Implement checking of fired watchpointSergey Fedorov2016-02-113-14/+25
* target-arm: Fix IL bit reported for Thumb VFP and Neon trapsPeter Maydell2016-02-111-3/+3
* target-arm: Fix IL bit reported for Thumb coprocessor trapsPeter Maydell2016-02-111-4/+4
* target-arm: Correct misleading 'is_thumb' syn_* parameter namesPeter Maydell2016-02-111-14/+14
* target-arm: Enable EL3 for Cortex-A53 and Cortex-A57Peter Maydell2016-02-111-0/+2
* target-arm: Implement NSACR trapping behaviourPeter Maydell2016-02-111-4/+58
* target-arm: Add isread parameter to CPAccessFnsPeter Maydell2016-02-116-37/+68
* target-arm: Update arm_generate_debug_exceptions() to handle EL2/EL3Peter Maydell2016-02-111-5/+43
* target-arm: Use access_trap_aa32s_el1() for SCR and MVBARPeter Maydell2016-02-111-2/+4
* target-arm: Implement MDCR_EL3 and SDCRPeter Maydell2016-02-112-0/+27
* target-arm: Fix typo in comment in arm_is_secure_below_el3()Peter Maydell2016-02-111-1/+1
* tcg: Change tcg_global_mem_new_* to take a TCGv_ptrRichard Henderson2016-02-092-12/+12
* tcg: Remove lingering references to gen_opc_bufRichard Henderson2016-02-091-2/+1Star
* Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20160203'...Peter Maydell2016-02-042-43/+60
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| * target-arm: Don't report presence of EL2 if it doesn't existPeter Maydell2016-02-031-0/+9
| * target-arm: Implement the S2 MMU inputsize > pamax checkEdgar E. Iglesias2016-02-031-0/+8
| * target-arm: Rename check_s2_startlevel to check_s2_mmu_setupEdgar E. Iglesias2016-02-031-6/+6
| * target-arm: Apply S2 MMU startlevel table size check to AArch64Edgar E. Iglesias2016-02-031-8/+8
| * target-arm: Make various system registers visible to EL3Peter Maydell2016-02-031-29/+29
* | log: do not unnecessarily include qom/cpu.hPaolo Bonzini2016-02-032-0/+2
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* arm: Clean up includesPeter Maydell2016-01-291-0/+1
* gdb: provide the name of the architecture in the target.xmlDavid Hildenbrand2016-01-272-0/+18
* target-arm: Implement FPEXC32_EL2 system registerPeter Maydell2016-01-211-0/+16
* target-arm: ignore ELR_ELx[1] for exception return to 32-bit ARM modePeter Maydell2016-01-211-1/+5
* target-arm: Implement remaining illegal return event checksPeter Maydell2016-01-211-0/+10
* target-arm: Handle exception return from AArch64 to non-EL0 AArch32Peter Maydell2016-01-211-21/+59
* target-arm: Fix wrong AArch64 entry offset for EL2/EL3 targetPeter Maydell2016-01-211-1/+20
* target-arm: Pull semihosting handling out to arm_cpu_do_interrupt()Peter Maydell2016-01-211-39/+81
* target-arm: Use a single entry point for AArch64 and AArch32 exceptionsPeter Maydell2016-01-213-36/+44
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