summaryrefslogtreecommitdiffstats
path: root/target-arm
Commit message (Collapse)AuthorAgeFilesLines
* target-arm: Use Common Tables in AES InstructionsTom Musta2014-06-161-75/+4Star
| | | | | | | | | This patch refactors the ARM cryptographic instructions to use the (newly) added common tables from include/qemu/aes.h. Signed-off-by: Tom Musta <tommusta@gmail.com> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Alexander Graf <agraf@suse.de>
* target-arm: Delete unused iwmmxt_msadb helperPeter Maydell2014-06-093-13/+0Star
| | | | | | | | | | | The iwmmxt_msadb helper and its corresponding gen function are unused; delete them. (This function appears to have never been used right back to the initial implementation of iwMMXt; it is identical to iwmmxt_madduq, and is presumably an accidental remnant from the initial development.) Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1401822125-1822-1-git-send-email-peter.maydell@linaro.org
* target-arm: Fix errors in writes to generic timer control registersPeter Maydell2014-06-091-3/+3
| | | | | | | | | | | | | | | | | | | | The code for handling writes to the generic timer control registers had several bugs: * ISTATUS (bit 2) is read-only but we forced it to zero on any write * the check for "was IMASK (bit 1) toggled?" incorrectly used '&' where it should be '^' * the handling of IMASK was inverted: we should set the IRQ if ISTATUS is set and IMASK is clear, not if both are set The combination of these bugs meant that when running a Linux guest that uses the generic timers we would fairly quickly end up either forgetting that the timer output should be asserted, or failing to set the IRQ when the timer was unmasked. The result is that the guest never gets any more timer interrupts. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1401803208-1281-1-git-send-email-peter.maydell@linaro.org Cc: qemu-stable@nongnu.org
* target-arm: A64: Implement two-register SHA instructionsPeter Maydell2014-06-091-1/+44
| | | | | | | | Implement the two-register SHA instruction group from the optional Crypto Extensions. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1401458125-27977-10-git-send-email-peter.maydell@linaro.org
* target-arm: A64: Implement 3-register SHA instructionsPeter Maydell2014-06-091-1/+58
| | | | | | | | Implement the 3-register SHA instruction group from the optional Crypto Extensions. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1401458125-27977-9-git-send-email-peter.maydell@linaro.org
* target-arm: A64: Implement AES instructionsPeter Maydell2014-06-091-1/+50
| | | | | | | Implement the AES instructions from the optional Crypto Extensions. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1401458125-27977-8-git-send-email-peter.maydell@linaro.org
* target-arm: A32/T32: Mask CRC value in calling code, not helperPeter Maydell2014-06-092-19/+16Star
| | | | | | | | | | Bring the 32-bit CRC helper functions into line with the A64 ones, by masking the high bytes of the value in the calling code rather than the helper. This is more efficient since we can determine the mask at translation time. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1401458125-27977-7-git-send-email-peter.maydell@linaro.org
* target-arm: A64: Implement CRC instructionsPeter Maydell2014-06-093-1/+85
| | | | | | | Implement the optional A64 CRC instructions. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1401458125-27977-6-git-send-email-peter.maydell@linaro.org
* target-arm: VFPv4 implies half-precision extensionPeter Maydell2014-06-092-4/+1Star
| | | | | | | | | | VFPv4 implies the presence of the half-precision floating point extension (which is optional in VFPv3). Add this implied rule to arm_cpu_realizefn() and remove some no-longer-needed explicit setting of the bit in initfns. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1401458125-27977-5-git-send-email-peter.maydell@linaro.org
* target-arm: Clean up handling of ARMv8 optional feature bitsPeter Maydell2014-06-092-4/+14
| | | | | | | | | CRC and crypto are both optional v8 extensions, so FEATURE_V8 should not imply them. Instead we should set these bits in the initfns for the 32-bit and 64-bit "cpu any" and for the Cortex-A57. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1401458125-27977-4-git-send-email-peter.maydell@linaro.org
* target-arm: Remove unnecessary setting of feature bitsPeter Maydell2014-06-092-4/+0Star
| | | | | | | | | FEATURE_V8 implies both FEATURE_V7MP and FEATURE_ARM_DIV, so we don't need to set them explicitly in initfns which set the V8 feature bit. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1401458125-27977-3-git-send-email-peter.maydell@linaro.org
* target-arm: arm_any_initfn() should never set ARM_FEATURE_AARCH64Peter Maydell2014-06-091-3/+0Star
| | | | | | | | | The arm_any_initfn() is used only for the 32-bit linux-user "cpu any", so it only gets called in builds where TARGET_AARCH64 is not defined. Remove the unreachable line which sets ARM_FEATURE_AARCH64. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1401458125-27977-2-git-send-email-peter.maydell@linaro.org
* target-arm: A64: Use PMULL feature bit for PMULLPeter Maydell2014-06-091-1/+1
| | | | | | | Now that we have a separate ARM_FEATURE_V8_PMULL bit, use it for the A64 PMULL, not the AES feature bit. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* target-arm: add support for v8 VMULL.P64 instructionPeter Maydell2014-06-097-33/+60
| | | | | | | | | | | | | | Add support for the VMULL.P64 polynomial 64x64 to 128 bit multiplication instruction in the A32/T32 instruction sets; this is part of the v8 Crypto Extensions. To do this we have to move the neon_pmull_64_{lo,hi} helpers from helper-a64.c into neon_helper.c so they can be used by the AArch32 translator. Inspired-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1401386724-26529-4-git-send-email-peter.maydell@linaro.org
* target-arm: Allow 3reg_wide undefreq to encode more bad size optionsPeter Maydell2014-06-091-12/+12
| | | | | | | | | | | | The current undefreq field in the neon_3reg_wide handling allows us to encode "UNDEF if size != 0" and "UNDEF if size == 0". This is no longer sufficient with the advent of 64-bit polynomial VMULL, which means we want to UNDEF if size == 1. Change the undefreq encoding to use separate bits for all of "UNDEF if size == 0", "UNDEF if size == 1" and "UNDEF if size == 2". Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1401386724-26529-3-git-send-email-peter.maydell@linaro.org
* target-arm: add support for v8 SHA1 and SHA256 instructionsArd Biesheuvel2014-06-095-7/+347
| | | | | | | | | | | | | | | | | | This adds support for the SHA1 and SHA256 instructions that are available on some v8 implementations of Aarch32. Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1401386724-26529-2-git-send-email-peter.maydell@linaro.org [PMM: * rebase * fix bad indent * add a missing UNDEF check for Q!=1 in the 3-reg SHA1/SHA256 case * use g_assert_not_reached() * don't re-extract bit 6 for the 2-reg-misc encodings * set the ELF HWCAP2 bits for the new features ] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* target-arm: Correct handling of UXN bit in ARMv8 LPAE page tablesIan Campbell2014-06-091-9/+8Star
| | | | | | | | | | | | | | | | | | | | In v8 page tables bit 54 in the PTE is UXN in the EL0/EL1 translation regimes and XN elsewhere. In v7 the bit is always XN. Since we only emulate EL0/EL1 we can just treat this bit as UXN whenever we are in v8 mode. Also correctly extract the upper attributes from the PTE entry, the v8 version tried to avoid extracting the CONTIG bit and ended up with the upper bits being off-by-one. Instead behave the same as v7 and extract (but ignore) the CONTIG bit. This fixes "Bad mode in Synchronous Abort handler detected, code 0x8400000f" seen when modprobing modules under Linux. Signed-off-by: Ian Campbell <ijc@hellion.org.uk> Cc: Peter Maydell <peter.maydell@linaro.org> Cc: Claudio Fontana <claudio.fontana@huawei.com> Cc: Rob Herring <robherring2@gmail.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* target-arm: Prepare cpreg writefns/readfns for EL3/SecExtFabian Aggeler2014-06-091-14/+14
| | | | | | | | | | | | This patch changes some readfns/writefns to use raw_write and raw_read functions, which use the fieldoffset specified in ARMCPRegInfo instead of directly accessing the field. This will simplify patches for EL3 & Security Extensions. Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Signed-off-by: Fabian Aggeler <aggelerf@ethz.ch> Message-id: 1401962428-14749-1-git-send-email-aggelerf@ethz.ch Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* target-arm/cpu64.c: Actually register Cortex-A57 impdef registersPeter Maydell2014-06-091-0/+1
| | | | | | | | | | | cpu64.c contains a reginfo list for the impdef registers on the Cortex-A57; however we forgot to actually call define_arm_cp_regs(), so it was sitting there doing nothing. Remedy this omission. Message-id: 1401226259-23121-1-git-send-email-peter.maydell@linaro.org Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Tested-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* softmmu: introduce cpu_ldst.hPaolo Bonzini2014-06-053-4/+3Star
| | | | | | | | | | This will collect all load and store helpers soon. For now it is just a replacement for softmmu_exec.h, which this patch stops including directly, but we also include it where this will be necessary in order to simplify the next patch. Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
* target-arm: move arm_*_code to a separate filePaolo Bonzini2014-06-055-22/+50
| | | | | | | These will soon require cpu_ldst.h, so move them out of cpu.h. Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
* softmmu: commonize helper definitionsPaolo Bonzini2014-06-051-14/+0Star
| | | | | | | | | They do not need to be in op_helper.c. Because cputlb.c now includes softmmu_template.h twice for each size, io_readX must be elided the second time through. Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
* tcg: Invert the inclusion of helper.hRichard Henderson2014-05-289-16/+10Star
| | | | | | | | | | Rather than include helper.h with N values of GEN_HELPER, include a secondary file that sets up the macros to include helper.h. This minimizes the files that must be rebuilt when changing the macros for file N. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
* target-arm: A64: Register VBAR_EL3Edgar E. Iglesias2014-05-272-1/+6
| | | | | | | Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Message-id: 1400980132-25949-24-git-send-email-edgar.iglesias@gmail.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* target-arm: A64: Register VBAR_EL2Edgar E. Iglesias2014-05-272-1/+22
| | | | | | | Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Message-id: 1400980132-25949-23-git-send-email-edgar.iglesias@gmail.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* target-arm: Make vbar_write writeback to any CPREGEdgar E. Iglesias2014-05-271-1/+1
| | | | | | | Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Message-id: 1400980132-25949-22-git-send-email-edgar.iglesias@gmail.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* target-arm: A64: Generalize update_spsel for the various ELsEdgar E. Iglesias2014-05-271-5/+6
| | | | | | | Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Message-id: 1400980132-25949-21-git-send-email-edgar.iglesias@gmail.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* target-arm: A64: Generalize ERET to various ELsEdgar E. Iglesias2014-05-271-5/+6
| | | | | | | | Adds support for ERET to and from AArch64 EL2 and 3. Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Message-id: 1400980132-25949-20-git-send-email-edgar.iglesias@gmail.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* target-arm: A64: Trap ERET from EL0 at translation timeEdgar E. Iglesias2014-05-271-0/+4
| | | | | | | Suggested-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Message-id: 1400980132-25949-19-git-send-email-edgar.iglesias@gmail.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* target-arm: A64: Forbid ERET to higher or unimplemented ELsEdgar E. Iglesias2014-05-271-2/+6
| | | | | | | Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Message-id: 1400980132-25949-18-git-send-email-edgar.iglesias@gmail.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* target-arm: Register EL3 versions of ELR and SPSREdgar E. Iglesias2014-05-271-0/+16
| | | | | | | Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Message-id: 1400980132-25949-17-git-send-email-edgar.iglesias@gmail.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* target-arm: Register EL2 versions of ELR and SPSREdgar E. Iglesias2014-05-271-0/+16
| | | | | | | Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Message-id: 1400980132-25949-16-git-send-email-edgar.iglesias@gmail.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* target-arm: Add a feature flag for EL3Edgar E. Iglesias2014-05-271-0/+1
| | | | | | | Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Message-id: 1400980132-25949-15-git-send-email-edgar.iglesias@gmail.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* target-arm: Add a feature flag for EL2Edgar E. Iglesias2014-05-271-0/+1
| | | | | | | Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Message-id: 1400980132-25949-14-git-send-email-edgar.iglesias@gmail.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* target-arm: A64: Introduce aarch64_banked_spsr_index()Edgar E. Iglesias2014-05-273-2/+17
| | | | | | | | | | Add aarch64_banked_spsr_index(), used to map an Exception Level to an index in the banked_spsr array. Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Message-id: 1400980132-25949-13-git-send-email-edgar.iglesias@gmail.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* target-arm: Add SPSR entries for EL2/HYP and EL3/MONEdgar E. Iglesias2014-05-274-6/+12
| | | | | | | Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Message-id: 1400980132-25949-12-git-send-email-edgar.iglesias@gmail.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* target-arm: A64: Add ELR entries for EL2 and 3Edgar E. Iglesias2014-05-272-4/+4
| | | | | | | Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Message-id: 1400980132-25949-11-git-send-email-edgar.iglesias@gmail.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* target-arm: A64: Add SP entries for EL2 and 3Edgar E. Iglesias2014-05-272-4/+4
| | | | | | | Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Message-id: 1400980132-25949-10-git-send-email-edgar.iglesias@gmail.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* target-arm: c12_vbar -> vbar_el[]Edgar E. Iglesias2014-05-273-5/+5
| | | | | | | | | | No functional change. Preparation for adding EL2 and 3 versions of this reg. Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Message-id: 1400980132-25949-9-git-send-email-edgar.iglesias@gmail.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* target-arm: Make esr_el1 an arrayEdgar E. Iglesias2014-05-273-8/+8
| | | | | | | | | | No functional change. Prepares for future addtion of EL2 and 3 versions of this reg. Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Message-id: 1400980132-25949-8-git-send-email-edgar.iglesias@gmail.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* target-arm: Make elr_el1 an arrayEdgar E. Iglesias2014-05-276-10/+11
| | | | | | | | | | No functional change. Prepares for future additions of the EL2 and 3 versions of this reg. Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Message-id: 1400980132-25949-7-git-send-email-edgar.iglesias@gmail.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* target-arm: Use a 1:1 mapping between EL and MMU indexEdgar E. Iglesias2014-05-272-9/+5Star
| | | | | | | Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com> Message-id: 1400980132-25949-6-git-send-email-edgar.iglesias@gmail.com Message-id: 1400805738-11889-7-git-send-email-edgar.iglesias@gmail.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* target-arm: A32: Use get_mem_index for load/storesEdgar E. Iglesias2014-05-271-106/+106
| | | | | | | | | | | | | Avoid using IS_USER directly as the MMU-idx to simplify future changes to the MMU layout. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1400980132-25949-5-git-send-email-edgar.iglesias@gmail.com Message-id: 1400805738-11889-6-git-send-email-edgar.iglesias@gmail.com [PMM: parts relating to LDRT/STRT moved into earlier patches] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* target-arm/translate.c: Use get_mem_index() for SRS memory accessesPeter Maydell2014-05-271-2/+2
| | | | | | | | | | | | The SRS instruction was using a hardcoded 0 for the memory accesses. This happens to be OK since the SRS instruction is UNPREDICTABLE in User and System modes, but is awkward if we want to rearrange the MMU index uses. Switch to using get_mem_index() like all the other accesses. Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1400980132-25949-4-git-send-email-edgar.iglesias@gmail.com
* target-arm/translate.c: Clean up mmu index handling for ldrt/strtPeter Maydell2014-05-271-12/+17
| | | | | | | | | | Clean up the mmu index handling for ldrt/strt insns: instead of a flag 'user' indicating whether to treat the store as user mode or not, use 'memidx' to indicate the correct memory index to use. Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1400980132-25949-3-git-send-email-edgar.iglesias@gmail.com
* target-arm: Move get_mem_index to translate.hEdgar E. Iglesias2014-05-272-9/+9
| | | | | | | | | So that it can be shared with the AArch32 code. Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Message-id: 1400980132-25949-2-git-send-email-edgar.iglesias@gmail.com Message-id: 1400805738-11889-5-git-send-email-edgar.iglesias@gmail.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* target-arm: implement CPACR register logic for ARMv7Fabian Aggeler2014-05-271-4/+28
| | | | | | | | | | | | | | | | In ARMv7 the CPACR register allows to control access rights to coprocessor 0-13 interfaces. Bits corresponding to unimplemented coprocessors should be RAZ/WI. Bits ASEDIS, D32DIS, TRCDIS are UNK/SBZP if VFP is not implemented and RAO/WI in some cases. Treating TRCDIS as RAZ/WI since we neither implement a trace macrocell nor a CP14 interface to the trace macrocell registers. Since CPACR bits for VFP/Neon access are honoured with the CPACR_FPEN bit in the TB flags, flushing the TLB is not necessary anymore. Signed-off-by: Fabian Aggeler <aggelerf@ethz.ch> Message-id: 1400532968-30668-1-git-send-email-aggelerf@ethz.ch Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* target-arm: Fix segfault on startup when KVM enabledChristoffer Dall2014-05-271-1/+1
| | | | | | | | | | | | | | | Commit 50a2c6e55fa introduced a bug where QEMU would segfault on startup when using KVM on ARM hosts, because kvm_arm_reset_cpu() accesses cpu->cpreg_reset_values, which is not allocated before kvm_arch_init_vcpu(). Fix this by not calling cpu_reset() until after qemu_init_vcpu(). Acked-by: Paolo Bonzini <pbonzini@redhat.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Andreas Faerber <afaerber@suse.de> Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org> Message-id: 1401194263-13010-1-git-send-email-christoffer.dall@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* Merge remote-tracking branch ↵Peter Maydell2014-05-152-5/+7
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 'remotes/pmaydell/tags/pull-target-arm-20140513' into staging target-arm queue: * update libvixl to 1.4 * remove version_minimum_id_old from ARM devices * stellaris_enet tx/rx/migration overhaul * various minor fixes for coverity issues # gpg: Signature made Tue 13 May 2014 16:25:12 BST using RSA key ID 14360CDE # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" * remotes/pmaydell/tags/pull-target-arm-20140513: hw/arm/omap_gpmc: Avoid buffer overrun filling prefetch FIFO hw/arm/stellaris: Correct handling of GPTM TAR register hw/timer/exynos4210_mct: Avoid overflow in exynos4210_ltick_recalc_count hw/dma/omap_dma: Add (uint32_t) casts when shifting uint16_t by 16 hw/arm/omap1: Avoid unintended sign extension writing omap_rtc YEARS_REG hw/net/cadence_gem: Remove dead code hw/intc/allwinner-a10-pic: Add missing 'break' target-arm/helper.c: Don't flush the TLB if SCTLR is rewritten unchanged hw/net/stellaris_enet: Convert to vmstate hw/net/stellaris_enet: Get rid of rx_fifo pointer hw/net/stellaris_enet: Fix debug format strings hw/net/stellaris_enet: Correctly implement the TR and THR registers hw/net/stellaris_enet: Rewrite tx fifo handling code hw/net/stellaris_enet: Correct handling of packet padding hw/net/stellaris_enet: Restructure tx_fifo code to avoid buffer overrun savevm: Remove all the unneeded version_minimum_id_old (arm) disas/libvixl: Update to libvixl 1.4 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * target-arm/helper.c: Don't flush the TLB if SCTLR is rewritten unchangedPeter Maydell2014-05-131-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Linux makes a habit of writing the same value to the SCTLR that it already holds. In a sample boot of the kernel to a shell prompt it wrote the SCTLR with the value it already held 325465 times, and wrote different values just 3 times. Skip flushing the TLB if the SCTLR value isn't actually being changed; this speeds up my sample boot by 3-5%. Reported-by: Laurent Desnogues <laurent.desnogues@gmail.com> Reviewed-by: Laurent Desnogues <laurent.desnogues@gmail.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1399560029-19007-1-git-send-email-peter.maydell@linaro.org
generated by cgit v1.2.3-55-g7522 (git 2.39.0) at 2024-12-12 00:53:33 +0100