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* target-arm: Drop unused DECODE_CPREG_CRN macroPeter Maydell2012-10-051-2/+0Star
| | | | | | This macro snuck through code review despite being unused; drop it. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* target-arm: use deposit instead of hardcoded versionAurelien Jarno2012-10-051-14/+6Star
| | | | | | | | Use the deposit op instead of and hardcoded bit field insertion. It allows the host to emit the corresponding instruction if available. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* target-arm: mark a few integer helpers const and pureAurelien Jarno2012-10-051-9/+10
| | | | | Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* target-arm: convert sar, shl and shr helpers to TCGAurelien Jarno2012-10-053-33/+43
| | | | | | | | | | | Now that the movcond TCG op is available, it's possible to replace shl and shr helpers by TCG code. The code generated by TCG is slightly longer than the code generated by GCC for the helper but is still worth it as this avoid all the consequences of using an helper: globals saved back to memory, no possible optimization, call overhead, etc. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* target-arm: convert add_cc and sub_cc helpers to TCGAurelien Jarno2012-10-053-40/+48
| | | | | | | | | | | Now that the setcond TCG op is available, it's possible to replace add_cc and sub_cc helpers by TCG code. The code generated by TCG is actually very close to the one generated by GCC for the helper, and this avoid all the consequences of using an helper: globals saved back to memory, no possible optimization, call overhead, etc. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* target-arm: use globals for CC flagsAurelien Jarno2012-10-051-81/+46Star
| | | | | | | | | Use globals for CC flags instead of loading/storing them each they are accessed. This allows some optimizations to be performed by the TCG optimization passes. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* target-arm: Reinstate display of VFP registers in cpu_dump_statePeter Maydell2012-10-051-26/+16Star
| | | | | | | | | | | Reinstate the display of VFP registers in cpu_dump_state(), if the CPU has them (this code had been #if 0'd out a for a long time). We drop the attempt ot display the values as floating point, since this makes assumptions about the host 'float' and 'double' formats and is not done by eg the i386 cpu_dump_state(). This display is gated on the CPU_DUMP_FPU flag, as for x86. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* Emit debug_insn for CPU_LOG_TB_OP_OPT as well.Richard Henderson2012-09-271-1/+1
| | | | | | | | | | | For all targets that currently call tcg_gen_debug_insn_start, add CPU_LOG_TB_OP_OPT to the condition that gates it. This is useful for comparing optimization dumps, when the pre-optimization dump is merely noise. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* target-arm: final conversion to AREG0 free modeBlue Swirl2012-09-155-20/+15Star
| | | | | | | Convert code load functions and switch to AREG0 free mode. Signed-off-by: Blue Swirl <blauwirbel@gmail.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
* target-arm: convert remaining helpersBlue Swirl2012-09-153-125/+125
| | | | | | | | Convert remaining helpers to AREG0 free mode: add an explicit CPUState parameter instead of relying on AREG0. Signed-off-by: Blue Swirl <blauwirbel@gmail.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
* target-arm: convert void helpersBlue Swirl2012-09-153-18/+18
| | | | | | | | | Add an explicit CPUState parameter instead of relying on AREG0. For easier review, convert only op helpers which don't return any value. Signed-off-by: Blue Swirl <blauwirbel@gmail.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
* target-arm: Fix potential buffer overflowStefan Weil2012-09-101-2/+2
| | | | | | | | | | | | | | | Report from smatch: target-arm/helper.c:651 arm946_prbs_read(6) error: buffer overflow 'env->cp15.c6_region' 8 <= 8 target-arm/helper.c:661 arm946_prbs_write(6) error: buffer overflow 'env->cp15.c6_region' 8 <= 8 c7_region is an array with 8 elements, so the index must be less than 8. Signed-off-by: Stefan Weil <sw@weilnetz.de> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* arm-semi: don't leak 1KB user string lock buffer upon TARGET_SYS_OPENJim Meyering2012-08-221-6/+7
| | | | | | | Always call unlock_user before returning. Signed-off-by: Jim Meyering <meyering@redhat.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
* target-arm: Fix typos in commentsPeter Maydell2012-08-106-24/+24
| | | | | | | | Fix a variety of typos in comments in target-arm files. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Peter Crosthwaite <peter.crosthwaite@petalogix.com> Signed-off-by: Stefan Hajnoczi <stefanha@linux.vnet.ibm.com>
* arm: translate: comment typo - s/middel/middle/Peter A. G. Crosthwaite2012-08-101-1/+1
| | | | | | | Signed-off-by: Peter A. G. Crosthwaite <peter.crosthwaite@petalogix.com> Reviewed-by: Andreas Färber <afaerber@suse.de> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Stefan Hajnoczi <stefanha@linux.vnet.ibm.com>
* target-arm: Add support for long format translation table walksPeter Maydell2012-07-121-0/+182
| | | | | | | Implement the actual table walk code for LPAE's long format translation tables. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* target-arm: Implement TTBCR changes for LPAEPeter Maydell2012-07-121-1/+14
| | | | | | | | | Implement the changes to the TTBCR register required for LPAE: * many fewer bits should be RAZ/WI * since TTBCR changes can result in a change of ASID, we must flush the TLB on writes to it Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* target-arm: Implement long-descriptor PAR formatPeter Maydell2012-07-121-10/+69
| | | | | | | | | | | Implement the different format of the PAR when long descriptor translation tables are in use. Note that we assume that get_phys_addr() returns a long-descriptor format DFSR value on failure if long descriptors are in use; this added subtlety tips the balance and makes it worth adding a comment documenting the API to get_phys_addr(). Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* target-arm: Use target_phys_addr_t in get_phys_addr()Peter Maydell2012-07-121-14/+15
| | | | | | | | In the implementation of get_phys_addr(), consistently use target_phys_addr_t to hold the physical address rather than uint32_t. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* target-arm: Add 64 bit PAR, TTBR0, TTBR1 for LPAEPeter Maydell2012-07-123-3/+87
| | | | | | | | | | | | | | | | Under LPAE, the cp15 registers PAR, TTBR0 and TTBR1 are extended to 64 bits, with a 64 bit (MRRC/MCRR) access path to read the full width of the register. Add the state fields for the top half and the 64 bit access path. Actual use of the top half of the register will come with the addition of the long-descriptor translation table format support. For the PAR we also need to correct the masking applied for 32 bit writes (there are no bits reserved if LPAE is implemented) and clear the high half when doing a 32 bit result VA-to-PA lookup. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* target-arm: Add 64 bit variants of DBGDRAR and DBGDSAR for LPAEPeter Maydell2012-07-121-0/+5
| | | | | | | | LPAE extends the DBGDRAR and DBGDSAR debug registers to 64 bits; we only implement these as dummy RAZ versions; provide dummies for the 64 bit accesses as well. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* target-arm: Add AMAIR0, AMAIR1 LPAE cp15 registersPeter Maydell2012-07-121-0/+16
| | | | | | | | | | Add implementations of the AMAIR0 and AMAIR1 LPAE Auxiliary Memory Attribute Indirection Registers. These are implementation defined and we choose to implement them as RAZ/WI, matching the Cortex-A7 and Cortex-A15. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* target-arm: Extend feature flags to 64 bitsPeter Maydell2012-07-123-6/+6
| | | | | | | Extend feature flags to 64 bits, as we've just run out of space in the 32 bit integer we were using for them. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* target-arm: Implement privileged-execute-never (PXN)Peter Maydell2012-07-123-12/+26
| | | | | | | | | | Implement the privileged-execute-never (PXN) translation table bit. It is implementation-defined whether this is implemented, so we give it its own ARM_FEATURE_ flag. LPAE requires PXN, so add also an LPAE feature flag and the implication logic, as a placeholder for actually implementing LPAE at a later date. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* ARM: Make target_phys_addr_t 64 bits and physaddrs 40 bitsPeter Maydell2012-07-121-1/+1
| | | | | | | | | | | Make target_phys_addr_t 64 bits for ARM targets, and set TARGET_PHYS_ADDR_SPACE_BITS to 40. This should have no effect for ARM boards where physical addresses really are 32 bits (except perhaps a slight performance hit on 32 bit hosts for system emulation) but allows us to implement the Large Physical Address Extensions for Cortex-A15, which mean 40 bit physical addresses. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* target-arm: Fix TCG temp handling in 64 bit cp writesPeter Maydell2012-07-121-0/+2
| | | | | | | | | | | | Fix errors in the TCG temp handling in the 64 bit coprocessor write path: we were reusing a 32 bit temp after it had been freed by store_reg(), and failing to free a 64 bit temp. This bug has no visible effect at this point because there aren't any non-NOP 64 bit registers yet; it needs to be fixed as a prerequisite for the 64 bit registers in LPAE support. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* target-arm: Fix some copy-and-paste errors in cp register namesPeter Maydell2012-07-121-3/+3
| | | | | | | | | Fix a couple of cases where cp register names were copy-and-pasted. These are harmless since we don't use the name for anything (except debugging convenience) but could be confusing. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Igor Mitsyanko <i.mitsyanko@samsung.com>
* target-arm: Fix typo that meant TTBR1 accesses went to TTBR0Peter Maydell2012-07-121-1/+1
| | | | | | | | Fix a copy-and-paste error in the register description for TTBR1 that meant it was a duplicate of TTBR0 rather than affecting the correct bit of CPU state. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* target-arm: Fix CP15 based WFIPaul Brook2012-07-121-1/+1
| | | | | | | | | | | The coprocessor register rework broke cp15 based WFI instructions. We incorrectly fall through the normal register write case, which incorrectly adds a forced block termination. We've already done a special version of this (DISAS_WFI), so return immediately. Signed-off-by: Paul Brook <paul@codesourcery.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* target-arm: Remove ARM_CPUID_* macrosPeter Maydell2012-06-202-52/+25Star
| | | | | | | | | | All the uses of ARM_CPUID() to vary behaviour have now been removed, so we can delete the ARM_CPUID_* macros now. The one exception is the TI915T/925T, because of its odd behaviour where the MIDR value can be changed at runtime. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Andreas Färber <afaerber@suse.de>
* target-arm: Remove remaining old cp15 infrastructurePeter Maydell2012-06-203-100/+1Star
| | | | | | | There are now no uses of the old cp15 infrastructure, so it can be deleted. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* target-arm: Move block cache ops to new cp15 frameworkPeter Maydell2012-06-202-6/+14
| | | | | | | | | Move the v6 optional block cache ops to the new cp15 framework. This includes only providing them on the CPUs which implemented them, rather than the previous blunderbuss approach of making all MCRR instructions on all CPUs act as NOPs. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* target-arm: Remove c0_cachetype CPUARMState fieldPeter Maydell2012-06-202-4/+1Star
| | | | | | | | | | Remove the no-longer-used CPUARMState c0_cachetype field. Although this was a constant register we had it in our migration state. Drop this (with resulting version bump) because for ARM currently we prefer cleaner migration code and have not stabilised migration format yet. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* target-arm: Convert final ID registersPeter Maydell2012-06-202-50/+68
| | | | | | Convert the final ID registers to the new cp15 scheme. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* target-arm: Convert MPIDRPeter Maydell2012-06-203-22/+31
| | | | | | | | Convert the MPIDR to the new cp15 register scheme. This includes giving it its own feature bit rather than doing a CPUID value check. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* target-arm: Convert cp15 cache ID registersPeter Maydell2012-06-203-32/+33
| | | | | | Convert the cp15 cache ID registers to the new scheme. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* target-arm: Convert cp15 crn=0 crm={1,2} feature registersPeter Maydell2012-06-203-24/+54
| | | | | | | Convert the cp15 crn=0 crm={1,2} features registers to the new cp reg framework. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* target-arm: Convert cp15 crn=1 registersPeter Maydell2012-06-203-76/+61Star
| | | | | | Convert the cp15 crn=1 registers to the new scheme. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* target-arm: Convert cp15 crn=9 registersPeter Maydell2012-06-202-79/+59Star
| | | | | | | | | | | | Convert cp15 crn=9 registers (mostly cache lockdown) to the new scheme. Note that this change makes OMAPCP cores RAZ/WI the whole c9 space. This is a change from previous behaviour, but a return to the behaviour of commit c3d2689d when OMAP1 support was first added -- subsequent commits have clearly accidentally relegated the OMAPCP RAZ condition to only a subset of the crn=9 space when adding support for other cores. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* target-arm: Convert cp15 crn=6 registersPeter Maydell2012-06-202-53/+45Star
| | | | | | | | | | Convert the cp15 crn=6 registers to the new scheme. Note that this includes some minor tidyup: drop an unnecessary underdecoding of op2 on OMAPCP cores, and only implement the pre-v6 c6,c0,0,1 IFAR on the 1026 and not on the other ARMv5 cores, which didn't have it. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* target-arm: convert cp15 crn=7 registersPeter Maydell2012-06-203-11/+74
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Convert the cp15 crn=7 registers to the new scheme. Note that to do this we have to distinguish some registers used on the ARM9 and ARM10 from some which are ARM1176 only. This is because the old code returned a value of 0 but always set the Z flag (by clearing env->ZF, since we store the Z flag in CPUState inverted). This is inconsistent with actual ARM CPU behaviour, which only sets flags for reads to r15 and sets them based on the top bits of the result. However it happened to work for the two common use cases for cp15 crn=7 reads: * On ARM9 and ARM10 the cache clean-and-test operations are typically done with a destination of r15 so that you can do a "loop: mrc ... ; bne loop" to keep cleaning until the cache is finally clean; always setting the Z flag means this loop terminates immediately * on ARM1176 the Cache Dirty Status Register reads as zero if the cache is dirty; returning 0 means this is correctly implemented for QEMU Since the new coprocessor register framework does the right thing of always setting flags based on the returned result for reads to r15, we need to split these up so that we can return (1<<30) for the ARM9/ARM10 registers but 0 for the ARM1176 one. This allows us to remove the nasty hack which always sets Z. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* target-arm: Convert cp15 VA-PA translation registersPeter Maydell2012-06-201-43/+65
| | | | | | | Convert the cp15 VA-PA translation registers (a subset of the crn=7 regs) to the new scheme. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* target-arm: Convert cp15 MMU TLB controlPeter Maydell2012-06-201-20/+43
| | | | | | Convert cp15 MMU TLB control (crn=8) to new scheme. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* target-arm: Convert cp15 crn=15 registersPeter Maydell2012-06-203-117/+126
| | | | | | | Convert the cp15 crn=15 (implementation specific) registers to the new scheme. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* target-arm: Convert cp15 crn=10 registersPeter Maydell2012-06-201-6/+5Star
| | | | | | | | | | | We RAZ/WI the entire block of crn=10 registers. Note that this actually covers not just the implementation-defined TLB lockdown registers but also a number of v7 VMSA memory attribute registers which we would need to implement to support TEX remap. We retain the previous QEMU behaviour in this conversion, though. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* target-arm: Convert cp15 crn=13 registersPeter Maydell2012-06-201-30/+31
| | | | | | | Convert the cp15 crn=13 registers (FCSEIDR, CONTEXTIDR, and the ARM946 Trace Process Identifier Register). Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* target-arm: Convert cp15 crn=2 registersPeter Maydell2012-06-202-56/+33Star
| | | | | | | Convert the cp15 crn=2 registers (MMU page table control, MPU cache control) to the new scheme. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* target-arm: Convert MMU fault status cp15 registersPeter Maydell2012-06-201-81/+107
| | | | | | | Convert the MMU fault status and MPU access permission cp15 registers to the new scheme. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* target-arm: Convert cp15 c3 registerPeter Maydell2012-06-201-6/+12
| | | | | | | | | | Convert the cp15 c3 register (MMU domain access control or MPU write buffer control). NB that this is horribly underdecoded for modern cores (should be crn=3,crm=0, opc1=0,opc2=0) but this change preserves the existing QEMU behaviour. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* target-arm: Convert generic timer cp15 regsPeter Maydell2012-06-201-12/+11Star
| | | | | | Convert the (dummy) generic timer cp15 implementation. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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