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* target-i386: Dump unknown opcodes with -d unimpRichard Henderson2016-03-141-44/+83
| | | | | | | | We discriminate here between opcodes that are illegal in the current cpu mode or with illegal arguments (such as modrm.mod == 3) and encodings that are unknown (such as an unimplemented isa extension). Signed-off-by: Richard Henderson <rth@twiddle.net>
* target-i386: Fix inhibit irq mask handlingRichard Henderson2016-03-141-39/+37Star
| | | | | | | | | | | The patch in 7f0b714 was too simplistic, in that we wound up setting the flag and then resetting it immediately in gen_eob. Fixes the reported boot problem with Windows XP. Reported-by: Hervé Poussineau <hpoussin@reactos.org> Tested-by: Hervé Poussineau <hpoussin@reactos.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
* target-i386: Use gen_nop_modrm for prefetch instructionsRichard Henderson2016-03-141-3/+2Star
| | | | | Tested-by: Hervé Poussineau <hpoussin@reactos.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
* target-i386: Fix addr16 prefixPaolo Bonzini2016-03-141-7/+7
| | | | | | | | | | | | | | | | | | | | While ADDSEG will only be false in 16-bit mode for LEA, it can be false even in other cases when 16-bit addresses are obtained via the 67h prefix in 32-bit mode. In this case, gen_lea_v_seg forgets to add a nonzero FS or GS base if CS/DS/ES/SS are all zero. This case is pretty rare but happens when booting Windows 95/98, and this patch fixes it. The bug is visible since commit d6a291498, but it was introduced together with gen_lea_v_seg and it probably could be reproduced with a "addr16 gs movsb" instruction as early as in commit ca2f29f555805d07fb0b9ebfbbfc4e3656530977. Reported-by: Hervé Poussineau <hpoussin@reactos.org> Tested-by: Hervé Poussineau <hpoussin@reactos.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Message-Id: <1456931078-21635-1-git-send-email-pbonzini@redhat.com> Signed-off-by: Richard Henderson <rth@twiddle.net>
* target-i386: Fix SMSW for 64-bit modeRichard Henderson2016-03-141-6/+8
| | | | | | | | | In non-64-bit modes, the instruction always stores 16 bits. But in 64-bit mode, when the destination is a register, the instruction can write 32 or 64 bits. Tested-by: Hervé Poussineau <hpoussin@reactos.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
* target-i386: Fix SMSW and LMSW from/to registerPaolo Bonzini2016-03-141-16/+22
| | | | | | | | | | | | SMSW and LMSW accept register operands, but commit 1906b2a ("target-i386: Rearrange processing of 0F 01", 2016-02-13) did not account for that. Fixes: 1906b2af7c2345037d9b2fdf484b457b5acd09d1 Reported-by: Hervé Poussineau <hpoussin@reactos.org> Tested-by: Hervé Poussineau <hpoussin@reactos.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Message-Id: <1456845134-18812-1-git-send-email-pbonzini@redhat.com> Signed-off-by: Richard Henderson <rth@twiddle.net>
* target-i386: Avoid repeated calls to the bnd_jmp helperPaolo Bonzini2016-03-141-5/+5
| | | | | | | | | | Two flags were tested the wrong way. Tested-by: Hervé Poussineau <hpoussin@reactos.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Message-Id: <1456845145-18891-1-git-send-email-pbonzini@redhat.com> Signed-off-by: Richard Henderson <rth@twiddle.net> [rth: Fixed enable test as well.]
* tcg: Add type for vCPU pointersLluís Vilanova2016-03-011-1/+1
| | | | | | | | | | | | | | | | | | | | Adds the 'TCGv_env' type for pointers to 'CPUArchState' objects. The tracing infrastructure later needs to differentiate between regular pointers and pointers to vCPUs. Also changes all targets to use the new 'TCGv_env' type instead of the generic 'TCGv_ptr'. As of now, the change is merely cosmetic ('TCGv_env' translates into 'TCGv_ptr'), but that could change in the future to enforce the difference. Note that a 'TCGv_env' type (for 'CPUState') is not added, since all helpers currently receive the architecture-specific pointer ('CPUArchState'). Signed-off-by: Lluís Vilanova <vilanova@ac.upc.edu> Acked-by: Richard Henderson <rth@twiddle.net> Message-id: 145641859552.30295.7821536833590725201.stgit@localhost Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
* target-i386: Implement FSGSBASERichard Henderson2016-02-151-0/+34
| | | | Signed-off-by: Richard Henderson <rth@twiddle.net>
* target-i386: Clear bndregs during legacy near jumpsRichard Henderson2016-02-151-0/+20
| | | | Signed-off-by: Richard Henderson <rth@twiddle.net>
* target-i386: Implement BNDLDX, BNDSTXRichard Henderson2016-02-151-0/+57
| | | | Signed-off-by: Richard Henderson <rth@twiddle.net>
* target-i386: Implement BNDCL, BNDCU, BNDCNRichard Henderson2016-02-151-1/+43
| | | | Signed-off-by: Richard Henderson <rth@twiddle.net>
* target-i386: Implement BNDMOVRichard Henderson2016-02-151-1/+72
| | | | Signed-off-by: Richard Henderson <rth@twiddle.net>
* target-i386: Implement BNDMKRichard Henderson2016-02-151-1/+57
| | | | Signed-off-by: Richard Henderson <rth@twiddle.net>
* target-i386: Split up gen_lea_modrmRichard Henderson2016-02-121-114/+85Star
| | | | | | | This is immediately usable by lea and multi-byte nop, and will be required to implement parts of the mpx spec. Signed-off-by: Richard Henderson <rth@twiddle.net>
* target-i386: Perform set/reset_inhibit_irq inlineRichard Henderson2016-02-121-9/+28
| | | | | | With helpers that can be reused for other things. Signed-off-by: Richard Henderson <rth@twiddle.net>
* target-i386: Enable control registers for MPXRichard Henderson2016-02-121-0/+5
| | | | | | Enable and disable at CPL changes, MSR changes, and XRSTOR changes. Signed-off-by: Richard Henderson <rth@twiddle.net>
* target-i386: Implement XSAVEOPTRichard Henderson2016-02-121-3/+15
| | | | Signed-off-by: Richard Henderson <rth@twiddle.net>
* target-i386: Add XSAVE extensionRichard Henderson2016-02-121-0/+54
| | | | | | | This includes XSAVE, XRSTOR, XGETBV, XSETBV, which are all related, as well as the associate cpuid bits. Signed-off-by: Richard Henderson <rth@twiddle.net>
* target-i386: Rearrange processing of 0F AERichard Henderson2016-02-121-52/+72
| | | | | | | | Rather than nesting tests of OP, MOD, and RM, decode them all at once with a switch. Also, add some missing #UD checks for e.g. incorrect LOCK prefix. Signed-off-by: Richard Henderson <rth@twiddle.net>
* target-i386: Rearrange processing of 0F 01Richard Henderson2016-02-121-223/+247
| | | | | | | | Rather than nesting tests of OP, MOD, and RM, decode them all at once with a switch. Fixes incorrect decoding of AMD Pacifica extensions (aka vmrun et al) via op==2 path. Signed-off-by: Richard Henderson <rth@twiddle.net>
* target-i386: Split fxsave/fxrstor implementationRichard Henderson2016-02-121-2/+2
| | | | | | We will be able to reuse these pieces for XSAVE/XRSTOR. Signed-off-by: Richard Henderson <rth@twiddle.net>
* target-i386: Deconstruct the cpu_T arrayRichard Henderson2016-02-091-607/+617
| | | | | | | | | | All references to cpu_T are done with a constant index. It aids readability to decompose the array into two scalar variables. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net> Message-Id: <1436426122-12276-11-git-send-email-rth@twiddle.net> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
* target-i386: Tidy gen_add_A0_imRichard Henderson2016-02-091-22/+5Star
| | | | | | | | | | | | Merge gen_op_addl_A0_im and gen_op_addq_A0_im into gen_add_A0_im and clean up the ifdef. Replace the one remaining user of gen_op_addl_A0_im with gen_add_A0_im. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net> Message-Id: <1450379966-28198-10-git-send-email-rth@twiddle.net> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
* target-i386: Rewrite leaveRichard Henderson2016-02-091-14/+15
| | | | | | | | | Unify the code across stack pointer widths. Fix the note about not updating ESP before the potential exception. Signed-off-by: Richard Henderson <rth@twiddle.net> Message-Id: <1450379966-28198-9-git-send-email-rth@twiddle.net> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
* target-i386: Rewrite gen_enter inlineRichard Henderson2016-02-091-59/+34Star
| | | | | | | | | | Use gen_lea_v_seg for centralized segment base knowledge. Unify code across 32- and 64-bit. Fix note about "must save state" before using the out-of-line helpers. Signed-off-by: Richard Henderson <rth@twiddle.net> Message-Id: <1450379966-28198-8-git-send-email-rth@twiddle.net> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
* target-i386: Use gen_lea_v_seg in pusha/popaRichard Henderson2016-02-091-27/+23Star
| | | | | | | | | More centralization of handling of segment bases. Also fixes the note about 16-bit wrap around not fully handled. Signed-off-by: Richard Henderson <rth@twiddle.net> Message-Id: <1450379966-28198-7-git-send-email-rth@twiddle.net> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
* target-i386: Access segs via TCG registersRichard Henderson2016-02-091-24/+28
| | | | | | | | | | | | Having segs[].base as a register significantly improves code generation for real and protected modes, particularly for TBs that have multiple memory references where the segment base can be held in a hard register through the TB. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net> Message-Id: <1450379966-28198-6-git-send-email-rth@twiddle.net> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
* target-i386: Use gen_lea_v_seg in stack subroutinesRichard Henderson2016-02-091-39/+13Star
| | | | | | | | | I.e. gen_push_v, gen_pop_T0, gen_stack_A0. More centralization of handling of segment bases. Signed-off-by: Richard Henderson <rth@twiddle.net> Message-Id: <1450379966-28198-5-git-send-email-rth@twiddle.net> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
* target-i386: Use gen_lea_v_seg in gen_lea_modrmRichard Henderson2016-02-091-59/+23Star
| | | | | | | | Centralize handling of segment bases. Signed-off-by: Richard Henderson <rth@twiddle.net> Message-Id: <1450379966-28198-4-git-send-email-rth@twiddle.net> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
* target-i386: Introduce mo_stacksizeRichard Henderson2016-02-091-14/+10Star
| | | | | | | | Centralize computation of a MO_SIZE for the stack pointer. Signed-off-by: Richard Henderson <rth@twiddle.net> Message-Id: <1450379966-28198-3-git-send-email-rth@twiddle.net> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
* target-i386: Create gen_lea_v_segRichard Henderson2016-02-091-107/+53Star
| | | | | | | | | | Add forgotten zero-extension in the TARGET_X86_64, !CODE64, ss32 case; use this new function to implement gen_string_movl_A0_EDI, gen_string_movl_A0_ESI, gen_add_A0_ds_seg. Signed-off-by: Richard Henderson <rth@twiddle.net> Message-Id: <1450379966-28198-2-git-send-email-rth@twiddle.net> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
* tcg: Change tcg_global_mem_new_* to take a TCGv_ptrRichard Henderson2016-02-091-5/+5
| | | | | | | | Thus, use cpu_env as the parameter, not TCG_AREG0 directly. Update all uses in the translators. Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg: Remove lingering references to gen_opc_bufRichard Henderson2016-02-091-2/+1Star
| | | | | | Three in comments and one in code in the stub tcg_liveness_analysis. Signed-off-by: Richard Henderson <rth@twiddle.net>
* log: do not unnecessarily include qom/cpu.hPaolo Bonzini2016-02-031-0/+1
| | | | | | | | | | Split the bits that require it to exec/log.h. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Denis V. Lunev <den@openvz.org> Acked-by: Christian Borntraeger <borntraeger@de.ibm.com> Message-id: 1452174932-28657-8-git-send-email-den@openvz.org Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
* x86: Clean up includesPeter Maydell2016-01-291-5/+1Star
| | | | | | | | | | Clean up includes so that osdep.h is included first and headers which it implies are not included manually. This commit was created with scripts/clean-includes. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1453832250-766-11-git-send-email-peter.maydell@linaro.org
* target-i386: Rename XMM_[BWLSDQ] helpers to ZMM_*Eduardo Habkost2016-01-211-94/+94
| | | | | | | | | They are helpers for the ZMMReg fields, so name them accordingly. This is just a global search+replace, no other changes are being introduced. Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
* target-i386: Rename struct XMMReg to ZMMRegEduardo Habkost2016-01-211-11/+11
| | | | | | | | | The struct represents a 512-bit register, so name it accordingly. This is just a global search+replace, no other changes are being introduced. Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
* target-i386: Rename optimize_flags_init()Eduardo Habkost2016-01-211-1/+1
| | | | | | | | Rename the function so that the reason for its existence is clearer: it does x86-specific initialization of TCG structures. Reviewed-by: Igor Mammedov <imammedo@redhat.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
* target-i386: Fix mulx for identical target regsRichard Henderson2015-11-171-1/+3
| | | | | | | | | | | | | | | The Intel specification clearly indicates that the low part of the result is written first and the high part of the result is written second; thus if ModRM:reg and VEX.vvvv are identical, the final result should be the high part of the result. At present, TCG may either produce incorrect results or crash with --enable-checking. Reported-by: Toni Nedialkov <farmdve@gmail.com> Reported-by: Max Reitz <mreitz@redhat.com> Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
* target-i386: tcg: Check right CPUID bits for clflushopt/pcommitEduardo Habkost2015-11-061-8/+20
| | | | | | | | | Detect the clflushopt and pcommit instructions and check their corresponding feature flags, instead of checking CPUID_SSE and CPUID_CLFLUSH. Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
* target-i386: tcg: Accept clwb instructionEduardo Habkost2015-11-061-1/+12
| | | | | | | | Accept the clwb instruction (66 0F AE /6) if its corresponding feature flag is enabled on CPUID[7]. Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
* target-*: Advance pc after recognizing a breakpointRichard Henderson2015-10-281-0/+5
| | | | | | | | Some targets already had this within their logic, but make sure it's present for all targets. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
* target-i386: Don't left shift negative constantEduardo Habkost2015-10-271-1/+1
| | | | | | | | | | Left shift of negative values is undefined behavior. Detected by clang: qemu/target-i386/translate.c:2423:26: runtime error: left shift of negative value -8 This changes the code to reverse the sign after the left shift. Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
* target-i386: Check CR4[DE] for processing DR4/DR5Richard Henderson2015-10-231-4/+6
| | | | | | | | | Introduce helper_get_dr so that we don't have to put CR4[DE] into the scarce HFLAGS resource. At the same time, rename helper_movl_drN_T0 to helper_set_dr and set the helper flags. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
* target-i386: Handle I/O breakpointsEduardo Habkost2015-10-231-1/+19
| | | | | Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
* tcg: Remove gen_intermediate_code_pcRichard Henderson2015-10-071-44/+5Star
| | | | | | | | | | It is no longer used, so tidy up everything reached by it. This includes the gen_opc_* arrays, the search_pc parameter and the inline gen_intermediate_code_internal functions. Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg: Pass data argument to restore_state_to_opcRichard Henderson2015-10-071-20/+6Star
| | | | | | | | | | The gen_opc_* arrays are already redundant with the data stored in the insn_start arguments. Transition restore_state_to_opc to use data from the latter. Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg: Add TCG_MAX_INSNSRichard Henderson2015-10-071-1/+5
| | | | | | | | Adjust all translators to respect it. Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
* target-i386: Add cc_op state to insn_startRichard Henderson2015-10-071-1/+1
| | | | | | Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
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