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* target-i386: Move KVM default-vendor hack to instance_initEduardo Habkost2014-02-031-13/+19
| | | | | | | | | | | As we will not have a cpu_x86_find_by_name() function anymore, move the KVM default-vendor hack to instance_init. Unfortunately we can't move that code to class_init because it depends on KVM being initialized. Signed-off-by: Eduardo Habkost <ehabkost@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
* target-i386: Don't change x86_def_t struct on cpu_x86_register()Eduardo Habkost2014-02-031-5/+6
| | | | | | | | | | | As eventually the x86_def_t data is going to be provided by the CPU class, it's better to not touch it, and handle the special cases on the X86CPU object itself. Current behavior of the code should stay exactly the same. Signed-off-by: Eduardo Habkost <ehabkost@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
* target-i386: Eliminate CONFIG_KVM #ifdefsEduardo Habkost2014-02-031-12/+3Star
| | | | | | | | | | | | | | | | The compiler is already able to eliminate the kvm_arch_get_supported_cpuid() calls in kvm_cpu_fill_host() and filter_features_for_kvm(), so we can eliminate the CONFIG_KVM #ifdefs there. Also, kvm_cpu_fill_host() and host_cpuid() don't need to check CONFIG_KVM, as they don't have any KVM-specific function calls. Tested to build successfully with CONFIG_KVM disabled, using the following CFLAGS combinations: "-DNDEBUG", "-DNDEBUG -O', "-DNDEBUG -O0", "-DNDEBUG -O1", "-DNDEBUG -O2". Signed-off-by: Eduardo Habkost <ehabkost@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
* kvm: add support for hyper-v timersVadim Rozenfeld2014-02-035-1/+44
| | | | | | | | | | http://msdn.microsoft.com/en-us/library/windows/hardware/ff541625%28v=vs.85%29.aspx This code is generic for activating reference time counter or virtual reference time stamp counter Signed-off-by: Vadim Rozenfeld <vrozenfe@redhat.com> Reviewed-by: Marcelo Tosatti <mtosatti@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
* kvm: make hyperv vapic assist page migratableVadim Rozenfeld2014-02-033-1/+32
| | | | | Signed-off-by: Vadim Rozenfeld <vrozenfe@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
* kvm: make hyperv hypercall and guest os id MSRs migratable.Vadim Rozenfeld2014-02-033-2/+39
| | | | | Signed-off-by: Vadim Rozenfeld <vrozenfe@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
* kvm: make availability of Hyper-V enlightenments dependent on KVM_CAP_HYPERVPaolo Bonzini2014-02-031-5/+11
| | | | | | | | | The MS docs specify HV_X64_MSR_HYPERCALL as a mandatory interface, thus we must provide the MSRs even if the user only specified features that, like relaxed timing, in principle don't require them. And the MSRs are only there if the hypervisor has KVM_CAP_HYPERV. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
* KVM: fix coexistence of KVM and Hyper-V leavesPaolo Bonzini2014-02-031-22/+25
| | | | | | | | kvm_arch_init_vcpu's initialization of the KVM leaves at 0x40000100 is broken, because KVM_CPUID_FEATURES is left at 0x40000001. Move it to 0x40000101 if Hyper-V is enabled. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
* target-i386: kvm_check_features_against_host(): Kill feature word arrayEduardo Habkost2014-02-031-36/+12Star
| | | | | | | | | We don't need the ft[] array on kvm_check_features_against_host() anymore, as we can simply use the feature_word_info[] array, that has everything we need. Signed-off-by: Eduardo Habkost <ehabkost@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
* target-i386: kvm_cpu_fill_host(): Fill feature words in a loopEduardo Habkost2014-02-031-16/+7Star
| | | | | | | | Now that the kvm_cpu_fill_host() code is simplified, we can simply set the feature word array using a simple loop. Signed-off-by: Eduardo Habkost <ehabkost@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
* target-i386: kvm_cpu_fill_host(): Set all feature words at end of functionEduardo Habkost2014-02-031-14/+9Star
| | | | | | | | Reorder the code so all the code that sets x86_cpu_def->features is at the end of the function. Signed-off-by: Eduardo Habkost <ehabkost@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
* target-i386: kvm_cpu_fill_host(): No need to check xlevel2Eduardo Habkost2014-02-031-7/+4Star
| | | | | | | | | | | | | | | | | | | | | | | There's no need to check CPU xlevel2 before calling kvm_arch_get_supported_cpuid(s, 0xC0000001, 0, R_EDX), because: * The kernel won't return any entry for 0xC0000000 if host CPU vendor is not Centaur (See kvm_dev_ioctl_get_supported_cpuid() on the kernel code) * Similarly, the kernel won't return any entry for 0xC0000001 if CPUID[0xC0000000].EAX is < 0xC0000001 * kvm_arch_get_supported_cpuid() will return 0 if no entry is returned by the kernel for the requested leaf For similar reasons, we can simply set x86_cpu_def->xlevel2 directly instead of making it conditional, because it will be set to 0 CPU vendor is not Centaur. This will simplify the kvm_cpu_fill_host() code a little. Signed-off-by: Eduardo Habkost <ehabkost@redhat.com> [Remove unparseable comment. - Paolo] Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
* target-i386: kvm_cpu_fill_host(): No need to check CPU vendorEduardo Habkost2014-02-031-8/+6Star
| | | | | | | | | | | | | | | There's no need to check CPU vendor before calling kvm_arch_get_supported_cpuid(s, 0xC0000000, 0, R_EAX), because: * The kernel won't return any entry for 0xC0000000 if host CPU vendor is not Centaur (See kvm_dev_ioctl_get_cpuid() on the kernel code); * kvm_arch_get_supported_cpuid() will return 0 if no entry is returned by the kernel for the requested leaf. This will simplify the kvm_cpu_fill_host() code a little. Signed-off-by: Eduardo Habkost <ehabkost@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
* target-i386: kvm_cpu_fill_host(): No need to check levelEduardo Habkost2014-02-031-6/+2Star
| | | | | | | | | | | | | | | There's no need to check level (CPUID[0].EAX) before calling kvm_arch_get_supported_cpuid(s, 0x7, 0, R_EBX), because: * The kernel won't return any entry for CPUID 7 if CPUID[0].EAX is < 7 on the host (See kvm_dev_ioctl_get_cpuid() on the kernel code); * kvm_arch_get_supported_cpuid() will return 0 if no entry is returned by the kernel for the requested leaf. This will simplify the kvm_cpu_fill_host() code a little. Signed-off-by: Eduardo Habkost <ehabkost@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
* target-i386: kvm_cpu_fill_host(): Kill unused codeEduardo Habkost2014-02-031-2/+0Star
| | | | | | | | Those host_cpuid() calls are useless. They are leftovers from when the old code using host_cpuid() was removed. Signed-off-by: Eduardo Habkost <ehabkost@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
* Merge remote-tracking branch 'qemu-kvm/uq/master' into stagingAnthony Liguori2014-01-254-18/+134
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * qemu-kvm/uq/master: kvm: always update the MPX model specific register KVM: fix addr type for KVM_IOEVENTFD KVM: Retry KVM_CREATE_VM on EINTR mempath prefault: fix off-by-one error kvm: x86: Separately write feature control MSR on reset roms: Flush icache when writing roms to guest memory target-i386: clear guest TSC on reset target-i386: do not special case TSC writeback target-i386: Intel MPX Conflicts: exec.c aliguori: fix trivial merge conflict in exec.c Signed-off-by: Anthony Liguori <aliguori@amazon.com>
| * kvm: always update the MPX model specific registerPaolo Bonzini2014-01-201-3/+3
| | | | | | | | | | | | | | | | | | The original patch from Liu Jinsong restricted them to reset or full state updates, but that's unnecessary (and wrong) since the BNDCFGS MSR has no side effects. Cc: Liu Jinsong <jinsong.liu@intel.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
| * kvm: x86: Separately write feature control MSR on resetJan Kiszka2013-12-181-4/+29
| | | | | | | | | | | | | | | | | | | | | | | | | | If the guest is running in nested mode on system reset, clearing the feature MSR signals the kernel to leave this mode. Recent kernels processes this properly, but leave the VCPU state undefined behind. It is the job of userspace to bring it to a proper shape. Therefore, write this specific MSR first so that no state transfer gets lost. This allows to cleanly reset a guest with VMX in use. Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
| * target-i386: clear guest TSC on resetFernando Luis Vázquez Cao2013-12-122-3/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | VCPU TSC is not cleared by a warm reset (*), which leaves some types of Linux guests (non-pvops guests and those with the kernel parameter no-kvmclock set) vulnerable to the overflow in cyc2ns_offset fixed by upstream commit 9993bc635d01a6ee7f6b833b4ee65ce7c06350b1 ("sched/x86: Fix overflow in cyc2ns_offset"). To put it in a nutshell, if such a Linux guest without the patch above applied has been up more than 208 days and attempts a warm reset chances are that the newly booted kernel will panic or hang. (*) Intel Xeon E5 processors show the same broken behavior due to the errata "TSC is Not Affected by Warm Reset" (Intel® Xeon® Processor E5 Family Specification Update - August 2013): "The TSC (Time Stamp Counter MSR 10H) should be cleared on reset. Due to this erratum the TSC is not affected by warm reset." Cc: Will Auld <will.auld@intel.com> Cc: Marcelo Tosatti <mtosatti@redhat.com> Signed-off-by: Fernando Luis Vazquez Cao <fernando@oss.ntt.co.jp> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Fernando Luis Vázquez Cao <fernando_b1@lab.ntt.co.jp>
| * target-i386: do not special case TSC writebackFernando Luis Vázquez Cao2013-12-121-9/+1Star
| | | | | | | | | | | | | | | | | | | | | | Newer kernels are capable of synchronizing TSC values of multiple VCPUs on writeback, but we were excluding the power up case, which is not needed anymore. Signed-off-by: Fernando Luis Vazquez Cao <fernando@oss.ntt.co.jp> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Fernando Luis Vázquez Cao <fernando_b1@lab.ntt.co.jp>
| * target-i386: Intel MPXLiu Jinsong2013-12-124-3/+101
| | | | | | | | | | | | | | | | | | Add some MPX related definiation, and hardcode sizes and offsets of xsave features 3 and 4. It also add corresponding part to kvm_get/put_xsave, and vmstate. Signed-off-by: Liu Jinsong <jinsong.liu@intel.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
* | Merge remote branch 'luiz/queue/qmp' into qmpqEdgar E. Iglesias2014-01-141-3/+1Star
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * luiz/queue/qmp: migration: qmp_migrate(): keep working after syntax error qerror: Remove assert_no_error() qemu-option: Remove qemu_opts_create_nofail target-i386: Remove assert_no_error usage hw: Remove assert_no_error usages qdev: Delete dead code error: Add error_abort monitor: add object-add (QMP) and object_add (HMP) command monitor: add object-del (QMP) and object_del (HMP) command qom: catch errors in object_property_add_child qom: fix leak for objects created with -object rng: initialize file descriptor to -1 qemu-monitor: HMP cpu-add wrapper vl: add missing transition debug->finish_migrate Message-Id: 1389045795-18706-1-git-send-email-lcapitulino@redhat.com Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
| * | target-i386: Remove assert_no_error usagePeter Crosthwaite2014-01-061-3/+1Star
| |/ | | | | | | | | | | | | | | Replace an assert_no_error() usage with the error_abort system. Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Reviewed-by: Markus Armbruster <armbru@redhat.com> Signed-off-by: Luiz Capitulino <lcapitulino@redhat.com>
* | Merge remote-tracking branch 'afaerber/tags/qom-cpu-for-anthony' into stagingAnthony Liguori2014-01-106-71/+90
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | QOM CPUState refactorings / X86CPU * TLB invalidation optimizations * X86CPU initialization cleanups * Preparations for X86CPU hot-unplug # gpg: Signature made Tue 24 Dec 2013 04:51:52 AM PST using RSA key ID 3E7E013F # gpg: Good signature from "Andreas Färber <afaerber@suse.de>" # gpg: aka "Andreas Färber <afaerber@suse.com>" # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 174F 0347 1BCC 221A 6175 6F96 FA2E D12D 3E7E 013F * afaerber/tags/qom-cpu-for-anthony: target-i386: Cleanup 'foo=val' feature handling target-i386: Cleanup 'foo' feature handling target-i386: Convert 'check' and 'enforce' to static properties target-i386: Convert 'hv_spinlocks' to static property target-i386: Convert 'hv_vapic' to static property target-i386: Convert 'hv_relaxed' to static property cpu-exec: Optimize X86CPU usage in cpu_exec() target-i386: Move apic_state field from CPUX86State to X86CPU cputlb: Tidy memset() of arrays cputlb: Use memset() when flushing entries
| * | target-i386: Cleanup 'foo=val' feature handlingIgor Mammedov2013-12-241-15/+2Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Features family, model, stepping, level, hv_spinlocks are treated similarly when passed from command line, so it's not necessary to handle each of them individually. Collapse them to one catch-all branch which will treat any not explicitly handled feature in format 'foo=val'. Any unknown feature will be rejected by property setter so there is no need to check for unknown feature in cpu_x86_parse_featurestr(), therefore it's replaced by above mentioned catch-all handler. Signed-off-by: Igor Mammedov <imammedo@redhat.com> Signed-off-by: Andreas Färber <afaerber@suse.de>
| * | target-i386: Cleanup 'foo' feature handlingIgor Mammedov2013-12-241-11/+2Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Features check, enforce, hv_relaxed and hv_vapic are treated as boolean set to 'on' when passed from command line, so it's not necessary to handle each of them separately. Collapse them to one catch-all branch which will treat any feature in format 'foo' as boolean set to 'on'. Any unknown feature will be rejected by CPU property setter so there is no need to check for unknown feature in cpu_x86_parse_featurestr(), therefore it's replaced by above mentioned catch-all handler. Signed-off-by: Igor Mammedov <imammedo@redhat.com> Reviewed-by: Eduardo Habkost <ehabkost@redhat.com> Signed-off-by: Andreas Färber <afaerber@suse.de>
| * | target-i386: Convert 'check' and 'enforce' to static propertiesIgor Mammedov2013-12-242-7/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | * Additionally convert check_cpuid & enforce_cpuid to bool and make them members of X86CPU * Make 'enforce' feature independent from 'check' Signed-off-by: Igor Mammedov <imammedo@redhat.com> Signed-off-by: Andreas Färber <afaerber@suse.de>
| * | target-i386: Convert 'hv_spinlocks' to static propertyIgor Mammedov2013-12-241-1/+44
| | | | | | | | | | | | | | | Signed-off-by: Igor Mammedov <imammedo@redhat.com> Signed-off-by: Andreas Färber <afaerber@suse.de>
| * | target-i386: Convert 'hv_vapic' to static propertyIgor Mammedov2013-12-241-1/+2
| | | | | | | | | | | | | | | Signed-off-by: Igor Mammedov <imammedo@redhat.com> Signed-off-by: Andreas Färber <afaerber@suse.de>
| * | target-i386: Convert 'hv_relaxed' to static propertyIgor Mammedov2013-12-241-1/+2
| | | | | | | | | | | | | | | Signed-off-by: Igor Mammedov <imammedo@redhat.com> Signed-off-by: Andreas Färber <afaerber@suse.de>
| * | target-i386: Move apic_state field from CPUX86State to X86CPUChen Fan2013-12-236-39/+34Star
| |/ | | | | | | | | | | | | This motion is preparing for refactoring vCPU APIC subsequently. Signed-off-by: Chen Fan <chen.fan.fnst@cn.fujitsu.com> Signed-off-by: Andreas Färber <afaerber@suse.de>
* | Merge remote-tracking branch 'rth/ldst-i386-2' into stagingAnthony Liguori2014-01-091-1534/+1111Star
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * rth/ldst-i386-2: (49 commits) target-i386: Tidy ljmp target-i386: Rename gen_op_jmp_T0 to gen_op_jmp_v target-i386: Tidy some size computation target-i386: Remove gen_op_mov_reg_A0 target-i386: Remove gen_op_mov_TN_reg target-i386: Remove gen_op_addl_T0_T1 target-i386: Remove gen_op_mov_reg_T1 target-i386: Remove gen_op_mov_reg_T0 target-i386: Tidy cpu_regs initialization target_i386: Clean up gen_pop_T0 target-i386: Combine gen_push_T* into gen_push_v target-i386: Tidy addr16 code in gen_lea_modrm target-i386: Change dflag to TCGMemOp target-i386: Change gen_op_mov_reg_A0 size parameter to TCGMemOp target-i386: Change aflag to TCGMemOp target-i386: Change gen_op_j*z_ecx size parameter to TCGMemOp target-i386: Change gen_op_add_reg_* size parameter to TCGMemOp target-i386: Use TCGMemOp for 'ot' variables target-i386: Remove gen_op_andl_A0_ffff target-i386: Remove gen_op_movl_T0_T1 ... Message-id: 1389128439-10067-1-git-send-email-rth@twiddle.net Signed-off-by: Anthony Liguori <aliguori@amazon.com>
| * | target-i386: Tidy ljmpRichard Henderson2014-01-071-2/+1Star
| | | | | | | | | | | | | | | | | | | | | Remove an unnecessary move opcode. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
| * | target-i386: Rename gen_op_jmp_T0 to gen_op_jmp_vRichard Henderson2014-01-071-9/+9
| | | | | | | | | | | | | | | | | | | | | And make the destination argument explicit. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
| * | target-i386: Tidy some size computationRichard Henderson2014-01-071-3/+3
| | | | | | | | | | | | | | | | | | | | | Clean up relics of multiple size domains: - MO_16 + 1 => - 1 + 1 => 0. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
| * | target-i386: Remove gen_op_mov_reg_A0Richard Henderson2014-01-071-6/+1Star
| | | | | | | | | | | | | | | | | | | | | Replace with its definition. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
| * | target-i386: Remove gen_op_mov_TN_regRichard Henderson2014-01-071-64/+59Star
| | | | | | | | | | | | | | | | | | | | | Replace with its definition. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
| * | target-i386: Remove gen_op_addl_T0_T1Richard Henderson2014-01-071-8/+3Star
| | | | | | | | | | | | | | | | | | | | | Replace with its definition. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
| * | target-i386: Remove gen_op_mov_reg_T1Richard Henderson2014-01-071-18/+13Star
| | | | | | | | | | | | | | | | | | | | | Replace with its definition. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
| * | target-i386: Remove gen_op_mov_reg_T0Richard Henderson2014-01-071-70/+65Star
| | | | | | | | | | | | | | | | | | | | | Replace with its definition. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
| * | target-i386: Tidy cpu_regs initializationRichard Henderson2014-01-071-51/+36Star
| | | | | | | | | | | | | | | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
| * | target_i386: Clean up gen_pop_T0Richard Henderson2014-01-071-47/+37Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Reduce ifdefs, share more code between paths, reduce the number of TCG ops generated. Avoid re-computing the size of the operation across gen_pop_T0 and gen_pop_update. Add forgotten zero-extension in the TARGET_X86_64, !CODE64, ss32 case. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
| * | target-i386: Combine gen_push_T* into gen_push_vRichard Henderson2014-01-071-74/+32Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Reduce ifdefs, share more code between paths, reduce the number of TCG ops generated. Add forgotten zero-extension in the TARGET_X86_64, !CODE64, ss32 case. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
| * | target-i386: Tidy addr16 code in gen_lea_modrmRichard Henderson2014-01-071-18/+16Star
| | | | | | | | | | | | | | | | | | | | | | | | Unlike the addr32, there was no bug. But we can use the same technique to reduce the number of TCG ops. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
| * | target-i386: Change dflag to TCGMemOpRichard Henderson2014-01-071-284/+216Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Changing the domain to TCGMemOp makes it easier to interoperate with other portions of the rest of the translator. We now only have one domain for size operands inside the translator, which makes things less confusing all the way around. There are still a number of helpers that continue to use the log2-1 domain. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
| * | target-i386: Change gen_op_mov_reg_A0 size parameter to TCGMemOpRichard Henderson2014-01-071-24/+8Star
| | | | | | | | | | | | | | | | | | | | | | | | Change the domain of the parameter and update all callers. Which lets us defer completely to gen_op_mov_reg_v. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
| * | target-i386: Change aflag to TCGMemOpRichard Henderson2014-01-071-91/+87Star
| | | | | | | | | | | | | | | | | | | | | | | | Changing the domain to TCGMemOp makes it easier to interoperate with other portions of the rest of the translator. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
| * | target-i386: Change gen_op_j*z_ecx size parameter to TCGMemOpRichard Henderson2014-01-071-10/+10
| | | | | | | | | | | | | | | | | | | | | Change the domain of the parameter and update all callers. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
| * | target-i386: Change gen_op_add_reg_* size parameter to TCGMemOpRichard Henderson2014-01-071-54/+22Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | These functions used the aflags/dflags domain, which is log2-1 of the byte size. Confusingly, they used enumeration values from the log2 domain. Change the domain of the parameter and update all callers. Since we're now in a common domain, defer the deposit/extend/mov decision to gen_op_mov_reg_v. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
| * | target-i386: Use TCGMemOp for 'ot' variablesRichard Henderson2014-01-071-50/+70
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The 'ot' variables (operand type?) hold the log2(byte size) of the operand being manipulated. This is the same as the MO_SIZE subset of the TCGMemOp. Indeed, we often pass 'ot' to the tcg_gen_qemu_ld/st functions. Changing the type from 'int' makes it easier to see what domain the variable should be. This does require adding some default cases to some switch statements, to avoid the 'unhandled enumeration value' warning that would result from the change of type. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
generated by cgit v1.2.3-55-g7522 (git 2.39.0) at 2024-12-05 02:52:38 +0100