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* target-i386: implement lzcnt emulationAndre Przywara2009-10-233-14/+38
| | | | | | | | | | | | | lzcnt is a AMD Phenom/Barcelona added instruction returning the number of leading zero bits in a word. As this is similar to the "bsr" instruction, reuse the existing code. There need to be some more changes, though, as lzcnt always returns a valid value (in opposite to bsr, which has a special case when the operand is 0). lzcnt is guarded by the ABM CPUID bit (Fn8000_0001:ECX_5). Signed-off-by: Andre Przywara <andre.przywara@amd.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* x86: add 'static' to please SparseBlue Swirl2009-10-181-5/+5
| | | | Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* target-i386: fix ARPLLaurent Desnogues2009-10-061-3/+7
| | | | | | | | The arpl implementation in target-i386/translate.c uses cpu_A0 temporary across a brcond op. This patch fixes that issue. Signed-off-by: Laurent Desnogues <laurent.desnogues@gmail.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* target-i386: move recently added vmstate fields at the end of the structureAurelien Jarno2009-10-051-4/+6
| | | | | | | This reduce the impact on hosts that have addressing modes with limited offsets. Suggested by Laurent Desnogues. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* x86: fix miss mergeJuan Quintela2009-10-051-1/+2
| | | | | | | | There was a missmerge, and then we got a tail recursive call to cpu_post_load without case base :) Signed-off-by: Juan Quintela <quintela@redhat.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
* gdbstub: x86: Switch 64/32 bit registers dynamicallyJan Kiszka2009-10-051-2/+5
| | | | | | | | | | | | | | | | | Commit 56aebc891674cd2d07b3f64183415697be200084 changed gdbstub in way that debugging 32 or 16-bit guest code is no longer possible with qemu for x86_64 guest CPUs. Since that commit, qemu only provides registers sets for 64-bit, forcing current and foreseeable gdb to also switch its architecture to 64-bit. And this breaks if the inferior is 32 or 16 bit. No question, this is a gdb issue. But, as it was confirmed in several discusssions with gdb people, it is a non-trivial thing to fix. So until qemu finds a gdb version attach with a rework x86 support, we have to work around it by switching the register layout as the guest switches its execution mode between 16/32 and 64 bit. Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
* x86: port cpu to vmstateJuan Quintela2009-10-051-259/+240Star
| | | | | Signed-off-by: Juan Quintela <quintela@redhat.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
* x86: factor out cpu_get/put_fpreg()Juan Quintela2009-10-051-72/+137
| | | | | Signed-off-by: Juan Quintela <quintela@redhat.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
* x86: factor out cpu_get/put_mttr_var()Juan Quintela2009-10-051-4/+24
| | | | | Signed-off-by: Juan Quintela <quintela@redhat.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
* x86: factor out cpu_get/put_xmm_reg()Juan Quintela2009-10-051-4/+24
| | | | | Signed-off-by: Juan Quintela <quintela@redhat.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
* x86: factor out cpu_pre/post_load()Juan Quintela2009-10-051-18/+39
| | | | | Signed-off-by: Juan Quintela <quintela@redhat.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
* x86: factor out cpu_pre_save()Juan Quintela2009-10-051-21/+32
| | | | | Signed-off-by: Juan Quintela <quintela@redhat.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
* x86: port segments to vmstateJuan Quintela2009-10-051-8/+16
| | | | | Signed-off-by: Juan Quintela <quintela@redhat.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
* x86: split MTRRVar unionJuan Quintela2009-10-051-4/+6
| | | | | Signed-off-by: Juan Quintela <quintela@redhat.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
* x86: split FPReg unionJuan Quintela2009-10-051-8/+10
| | | | | Signed-off-by: Juan Quintela <quintela@redhat.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
* x86: mcg_cap is never 0Juan Quintela2009-10-051-12/+8Star
| | | | | Signed-off-by: Juan Quintela <quintela@redhat.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
* x86: send mce_banks as an arrayJuan Quintela2009-10-051-10/+4Star
| | | | | Signed-off-by: Juan Quintela <quintela@redhat.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
* x86: mce_banks always have the same sizeJuan Quintela2009-10-053-5/+4Star
| | | | | | | | mce_banks is always MCE_BANKS_DEF * 4 in size, value never change CC: Huang Ying <ying.huang@intel.com> Signed-off-by: Juan Quintela <quintela@redhat.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
* x86: add fpregs_format_vmstateJuan Quintela2009-10-052-7/+6Star
| | | | | | | Don't even ask, being able to load/save between 64<->80bit floats should be forbidden Signed-off-by: Juan Quintela <quintela@redhat.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
* x86: add pending_irq_vmstate to the stateJuan Quintela2009-10-052-9/+8Star
| | | | | | | It is needed to save the interrupt_bitmap Signed-off-by: Juan Quintela <quintela@redhat.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
* x86: add fptag_vmstate to the stateJuan Quintela2009-10-052-9/+10
| | | | | | | It is needed to store fptags Signed-off-by: Juan Quintela <quintela@redhat.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
* x86: fpus is uint16_t not unsigned intJuan Quintela2009-10-052-9/+10
| | | | | | | We save more that fpus on that 16 bits (fpstt), we need an additional field Signed-off-by: Juan Quintela <quintela@redhat.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
* x86: fpuc is uint16_t not unsigned intJuan Quintela2009-10-052-7/+5Star
| | | | | Signed-off-by: Juan Quintela <quintela@redhat.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
* x86: make a20_mask int32_tJuan Quintela2009-10-053-11/+6Star
| | | | | | | | | | This makes the savevm code correct, and sign extensins gives us exactly what we need (namely, sign extend to 64 bits when used with 64bit addresess. Once there, change 0x100000 for 1 << 20, that maks all a20 use the same syntax. Signed-off-by: Juan Quintela <quintela@redhat.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
* x86: hflags is not modified at all, just save it directlyJuan Quintela2009-10-051-8/+3Star
| | | | | Signed-off-by: Juan Quintela <quintela@redhat.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
* target-i386: Fix exceptions for fxsave/fxrstorKevin Wolf2009-10-042-4/+14
| | | | | | | | | | | | This patch corrects the following aspects of exception generation in fxsave/fxrstor: * Generate #GP if the operand is not aligned to a 16 byte boundary * Generate #UD if the LOCK prefix is used * For CR0.EM = 1 #NM is generated, not #UD Signed-off-by: Kevin Wolf <mail@kevin-wolf.de> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* target-i386: add RDTSCP supportAndre Przywara2009-10-045-16/+63
| | | | | | | | | | | | | | RDTSCP reads the time stamp counter and atomically also the content of a 32-bit MSR, which can be freely set by the OS. This allows CPU local data to be queried by userspace. Linux uses this to allow a fast implementation of the getcpu() syscall, which uses the vsyscall page to avoid a context switch. AMD CPUs since K8RevF and Intel CPUs since Nehalem support this instruction. RDTSCP is guarded by the RDTSCP CPUID bit (Fn8000_0001:EDX[27]). Signed-off-by: Andre Przywara <andre.przywara@amd.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* target-i386: add SSE4a instruction supportAndre Przywara2009-10-043-2/+85
| | | | | | | | | | | | | | This adds support for the AMD Phenom/Barcelona's SSE4a instructions. Those include insertq and extrq, which are doing shift and mask on XMM registers, in two versions (immediate shift/length values and stored in another XMM register). Additionally it implements movntss, movntsd, which are scalar non-temporal stores (avoiding cache trashing). These are implemented as normal stores, though. SSE4a is guarded by the SSE4A CPUID bit (Fn8000_0001:ECX[6]). Signed-off-by: Andre Przywara <andre.przywara@amd.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* target-i386: add lock mov cr0 = cr8Andre Przywara2009-10-041-0/+4
| | | | | | | | | | AMD CPUs featuring a shortcut to access CR8 even from 32-bit mode. If you use the LOCK prefix with "mov CR0", it accesses CR8 instead. This behavior is guarded by the CR8_LEGACY CPUID bit (Fn8000_0001:ECX[1]). Signed-off-by: Andre Przywara <andre.przywara@amd.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* Revert "Get rid of _t suffix"Anthony Liguori2009-10-012-15/+15
| | | | | | | | | | | | In the very least, a change like this requires discussion on the list. The naming convention is goofy and it causes a massive merge problem. Something like this _must_ be presented on the list first so people can provide input and cope with it. This reverts commit 99a0949b720a0936da2052cb9a46db04ffc6db29. Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
* Get rid of _t suffixmalc2009-10-012-15/+15
| | | | | | | Some not so obvious bits, slirp and Xen were left alone for the time being. Signed-off-by: malc <av1474@comtv.ru>
* x86: use globals for CPU registersLaurent Desnogues2009-09-301-71/+125
| | | | | | Use globals for the 8 or 16 CPU registers on i386 and x86_64. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* target-i386: kill a tmp registerAurelien Jarno2009-09-271-4/+3Star
| | | | Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* target-i386: use subfi instead of sub with a non-freed constantAurelien Jarno2009-09-271-7/+7
| | | | Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* gcc wants 1st static and then constJuan Quintela2009-09-251-1/+1
| | | | | Signed-off-by: Juan Quintela <quintela@redhat.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* ioports: remove unused env parameter and compile only onceBlue Swirl2009-09-201-6/+6
| | | | | | | The CPU state parameter is not used, remove it and adjust callers. Now we can compile ioport.c once for all targets. Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* i386: Drop redundant kvm_enabled testJan Kiszka2009-09-121-2/+1Star
| | | | | | | cpu_synchronize_state already does this. Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* Work around OpenSolaris sys/regset.h namespace pollutionBlue Swirl2009-09-121-0/+9
| | | | Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* Fix sys-queue.h conflict for goodBlue Swirl2009-09-122-3/+3
| | | | | | | | | | | | | | | Problem: Our file sys-queue.h is a copy of the BSD file, but there are some additions and it's not entirely compatible. Because of that, there have been conflicts with system headers on BSD systems. Some hacks have been introduced in the commits 15cc9235840a22c289edbe064a9b3c19c5f49896, f40d753718c72693c5f520f0d9899f6e50395e94, 96555a96d724016e13190b28cffa3bc929ac60dc and 3990d09adf4463eca200ad964cc55643c33feb50 but the fixes were fragile. Solution: Avoid the conflict entirely by renaming the functions and the file. Revert the previous hacks. Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* kvm_arch_get_registers() shouldn't be called directlyGleb Natapov2009-09-111-1/+1
| | | | | | | | Direct call to kvm_arch_get_registers() bypass logic in cpu_synchronize_state() Signed-off-by: Gleb Natapov <gleb@redhat.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
* Fix Sparse warnings: add "static"Blue Swirl2009-09-051-1/+1
| | | | Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* kvm: Simplify cpu_synchronize_state()Avi Kivity2009-08-281-2/+2
| | | | | | | | | | | cpu_synchronize_state() is a little unreadable since the 'modified' argument isn't self-explanatory. Simplify it by making it always synchronize the kernel state into qemu, and automatically flush the registers back to the kernel if they've been synchronized on this exit. Signed-off-by: Avi Kivity <avi@redhat.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
* introduce kvm64 CPUAndre Przywara2009-08-281-0/+26
| | | | | | | | | | In addition to the TCG based qemu64 type let's introduce a kvm64 CPU type, which is the least common denominator of all KVM-capable x86-CPUs (based on Intel Pentium 4 Prescott). It can be used as a base type for migration. Signed-off-by: Andre Przywara <andre.przywara@amd.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
* allow overriding of CPUID level on command lineAndre Przywara2009-08-281-10/+29
| | | | | | | | | | | | The CPUID level determines how many CPUID leafs are exposed to the guest. Some features (like multi-core) cannot be propagated without the proper level, but guests maybe confused by bogus entries in some leafs. So add level= and xlevel= to the list of -cpu options to allow the user to override the default settings. While at it, merge unnecessary local variables into one and allow hexadecimal arguments. Signed-off-by: Andre Przywara <andre.przywara@amd.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
* set CPUID bits to present cores and threads topologyAndre Przywara2009-08-281-3/+25
| | | | | | | | | | | Controlled by the enhanced -smp option set the CPUID bits to present the guest the desired topology. This is vendor specific, but (with the exception of the CMP_LEGACY bit) not conflicting, so we set all bits everytime. There is no real multithreading support for AMD CPUs, so report cores instead. Signed-off-by: Andre Przywara <andre.przywara@amd.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
* push CPUID level to 4 to allow Intel multicore decodingAndre Przywara2009-08-281-2/+2
| | | | | | | | Intel CPUs store the number of cores in CPUID leaf 4. So push the maxleaf value to 4 to allow the guests access to this leaf. Signed-off-by: Andre Przywara <andre.przywara@amd.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
* cleanup cpu-exec.c, part 0/N: consolidate handle_cpu_signalNathan Froyd2009-08-241-0/+1
| | | | | | | | | | | | | | | handle_cpu_signal is very nearly copy-paste code for each target, with a few minor variations. This patch sets up appropriate defaults for a generic handle_cpu_signal and provides overrides for particular targets that did things differently. Fixing things like the persistent (XXX: use sigsetjmp) should now become somewhat easier. Previous comments on this patch suggest that the "activate soft MMU for this block" comments refer to defunct functionality. I have removed such blocks for the appropriate targets in this patch. Signed-off-by: Nathan Froyd <froydnj@codesourcery.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
* Unbreak large mem support by removing kqemuAnthony Liguori2009-08-244-72/+0Star
| | | | | | | | | | | | | | | | | | | | | | kqemu introduces a number of restrictions on the i386 target. The worst is that it prevents large memory from working in the default build. Furthermore, kqemu is fundamentally flawed in a number of ways. It relies on the TSC as a time source which will not be reliable on a multiple processor system in userspace. Since most modern processors are multicore, this severely limits the utility of kqemu. kvm is a viable alternative for people looking to accelerate qemu and has the benefit of being supported by the upstream Linux kernel. If someone can implement work arounds to remove the restrictions introduced by kqemu, I'm happy to avoid and/or revert this patch. N.B. kqemu will still function in the 0.11 series but this patch removes it from the 0.12 series. Paul, please Ack or Nack this patch. Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
* rename WORDS_BIGENDIAN to HOST_WORDS_BIGENDIANJuan Quintela2009-07-273-4/+4
| | | | | Signed-off-by: Juan Quintela <quintela@redhat.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
* Only allow -cpu host when KVM is enabledAnthony Liguori2009-07-171-4/+3Star
| | | | | | -cpu host is not at all useful when using tcg. Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
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