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* target-mips: add CP0.PageGrain.ELPA supportLeon Alrae2015-06-121-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | CP0.PageGrain.ELPA enables support for large physical addresses. This field is encoded as follows: 0: Large physical address support is disabled. 1: Large physical address support is enabled. If this bit is a 1, the following changes occur to coprocessor 0 registers: - The PFNX field of the EntryLo0 and EntryLo1 registers is writable and concatenated with the PFN field to form the full page frame number. - Access to optional COP0 registers with PA extension, LLAddr, TagLo is defined. P5600 can operate in 32-bit or 40-bit Physical Address Mode. Therefore if XPA is disabled (CP0.PageGrain.ELPA = 0) then assume 32-bit Address Mode. In MIPS64 assume 36 as default PABITS (when CP0.PageGrain.ELPA = 0). env->PABITS value is constant and indicates maximum PABITS available on a core, whereas env->PAMask is calculated from env->PABITS and is also affected by CP0.PageGrain.ELPA. Signed-off-by: Leon Alrae <leon.alrae@imgtec.com> Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>
* target-mips: add MSA defines and data structureYongbok Kim2014-11-031-0/+1
| | | | | | | | add defines and data structure for MIPS SIMD Architecture Reviewed-by: James Hogan <james.hogan@imgtec.com> Signed-off-by: Yongbok Kim <yongbok.kim@imgtec.com> Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
* target-mips: define ISA_MIPS64R6Leon Alrae2014-10-131-9/+19
| | | | | Signed-off-by: Leon Alrae <leon.alrae@imgtec.com> Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>
* target-mips: add CPU definition for MIPS32R5Petar Jovanovic2014-02-101-0/+8
| | | | | | | | Add mips32r5-generic among CPU definitions for MIPS. Define ISA_MIPS32R3 and ISA_MIPS32R5. Signed-off-by: Petar Jovanovic <petar.jovanovic@imgtec.com> Reviewed-by: Eric Johnson <eric.johnson@imgtec.com>
* MIPS: Initial support of fulong mini pc (CPU definition)Huacai Chen2010-06-291-0/+4
| | | | | Signed-off-by: Huacai Chen <zltjiangshi@gmail.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* target-mips: microMIPS ASE supportNathan Froyd2010-06-091-0/+1
| | | | | | | | Add instruction decoding for the microMIPS ASE. All we do is decode and then forward to the existing gen_* routines. Signed-off-by: Nathan Froyd <froydnj@codesourcery.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* target-mips: update address space definitionsAurelien Jarno2010-03-131-4/+4
| | | | Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* Move TARGET_PHYS_ADDR_SPACE_BITS to target-*/cpu.h.Richard Henderson2010-03-121-0/+4
| | | | | | | | | | Removes a set of ifdefs from exec.c. Introduce TARGET_VIRT_ADDR_SPACE_BITS for all targets other than Alpha. This will be used for page_find_alloc, which is supposed to be using virtual addresses in the first place. Signed-off-by: Richard Henderson <rth@twiddle.net>
* Hardware convenience libraryPaul Brook2009-05-191-3/+0Star
| | | | | | | | | | | | | | The only target dependency for most hardware is sizeof(target_phys_addr_t). Build these files into a convenience library, and use that instead of building for every target. Remove and poison various target specific macros to avoid bogus target dependencies creeping back in. Big/Little endian is not handled because devices should not know or care about this to start with. Signed-off-by: Paul Brook <paul@codesourcery.com>
* Support for VR5432, and some of its special instructions. Original patchths2007-12-251-5/+9
| | | | | | | by Dirk Behme. git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3859 c046a42c-6fe2-441c-8c8c-71466251a162
* Larger physical address space for 32-bit MIPS.ths2007-12-021-0/+3
| | | | git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3765 c046a42c-6fe2-441c-8c8c-71466251a162
* Clean out the N32 macros from target-mips, and introduce MIPS ABI specificths2007-11-081-1/+1
| | | | | | | defines for linux-user. git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3556 c046a42c-6fe2-441c-8c8c-71466251a162
* Use the standard ASE check for MIPS-3D and MT.ths2007-10-231-0/+2
| | | | git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3427 c046a42c-6fe2-441c-8c8c-71466251a162
* Code provision for n32/n64 mips userland emulation. Not functional yet.ths2007-09-301-1/+1
| | | | git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3284 c046a42c-6fe2-441c-8c8c-71466251a162
* Per-CPU instruction decoding implementation, by Aurelien Jarno.ths2007-09-241-0/+35
| | | | git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3228 c046a42c-6fe2-441c-8c8c-71466251a162
* MIPS TLB style selection at runtime, by Herve Poussineau.ths2007-05-131-2/+0Star
| | | | git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2809 c046a42c-6fe2-441c-8c8c-71466251a162
* Kill broken host register definitions, thanks to Paul Brook and Herveths2007-04-291-2/+0Star
| | | | | | | Poussineau for debugging this. git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2747 c046a42c-6fe2-441c-8c8c-71466251a162
* Update comment. We can't easily adhere to the architecture spec becauseths2007-04-191-3/+3
| | | | | | | it would involve counting the actually executed instructions. git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2708 c046a42c-6fe2-441c-8c8c-71466251a162
* Choose number of TLBs at runtime, by Herve Poussineau.ths2007-04-171-1/+0Star
| | | | git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2693 c046a42c-6fe2-441c-8c8c-71466251a162
* Throw RI for invalid MFMC0-class instructions. Introduce optionalths2007-04-111-0/+5
| | | | | | | | MIPS_STRICT_STANDARD define to adhere more to the spec than it makes sense in normal operation. git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2650 c046a42c-6fe2-441c-8c8c-71466251a162
* Actually enable 64bit configuration.ths2007-04-011-4/+1Star
| | | | git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2565 c046a42c-6fe2-441c-8c8c-71466251a162
* Move mips CPU specific initialization to translate_init.c.ths2007-03-211-37/+0Star
| | | | git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2522 c046a42c-6fe2-441c-8c8c-71466251a162
* MIPS -cpu selection support, by Herve Poussineau.ths2007-03-181-26/+0Star
| | | | git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2491 c046a42c-6fe2-441c-8c8c-71466251a162
* MIPS FPU dynamic activation, part 1, by Herve Poussineau.ths2007-02-281-9/+4Star
| | | | git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2463 c046a42c-6fe2-441c-8c8c-71466251a162
* Preliminiary MIPS64 support, disabled by default due to performance impact.ths2006-12-211-3/+10
| | | | git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2250 c046a42c-6fe2-441c-8c8c-71466251a162
* Add MIPS32R2 instructions, and generally straighten out the instructionths2006-12-061-16/+34
| | | | | | | decoding. This is also the first percent towards MIPS64 support. git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2224 c046a42c-6fe2-441c-8c8c-71466251a162
* MIPS TLB performance improvements, by Daniel Jacobowitz.ths2006-12-061-0/+1
| | | | git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2220 c046a42c-6fe2-441c-8c8c-71466251a162
* mips config fixes (initial patch by Stefan Weil)bellard2006-06-141-11/+14
| | | | git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@1977 c046a42c-6fe2-441c-8c8c-71466251a162
* MIPS FPU support (Marius Goeger)bellard2006-06-141-3/+9
| | | | git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@1964 c046a42c-6fe2-441c-8c8c-71466251a162
* MIPS target (Jocelyn Mayer)bellard2005-07-021-0/+58
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@1464 c046a42c-6fe2-441c-8c8c-71466251a162
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