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* Remove unused function parameters from gen_pc_load and rename the functionStefan Weil2011-04-201-2/+1Star
| | | | | | | | | | | | | | | | | | | | | | | | | | Function gen_pc_load was introduced in commit d2856f1ad4c259e5766847c49acbb4e390731bd4. The only reason for parameter searched_pc was a debug statement in target-i386/translate.c. Parameter puc was needed by target-sparc until commit d7da2a10402f1644128b66414ca8f86bdea9ae7c. Remove searched_pc from the debug statement and remove both parameters from the parameter list of gen_pc_load. As the function name gen_pc_load was also misleading, it is now called restore_state_to_opc. This new name was suggested by Peter Maydell, thanks. v2: Remove last parameter, too, and rename the function. v3: Fix [] typo in target-arm/translate.c. Fix wrong SHA1 object name in commit message (copy+paste error). Cc: Aurelien Jarno <aurelien@aurel32.net> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Stefan Weil <weil@mail.berlios.de>
* Fix conversions from pointer to tcg_target_longStefan Weil2011-04-101-1/+1
| | | | | | | | | | | | tcg_gen_exit_tb takes a parameter of type tcg_target_long, so the type casts of pointer to long should be replaced by type casts of pointer to tcg_target_long (suggested by Blue Swirl). These changes are needed for build environments where sizeof(long) != sizeof(void *), especially for w64. Signed-off-by: Stefan Weil <weil@mail.berlios.de> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* target-mips: fix save_cpu_state() callsAurelien Jarno2011-01-241-6/+6
| | | | | | | | | | The rule is: - don't save PC if the exception is only triggered by softmmu. - save PC if the exception can be triggered by an helper. Fix a 64-bit kernel crash when loading modules. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* mips: Break TBs after mfc0_countEdgar E. Iglesias2011-01-181-2/+6
| | | | | | | | Break the TB after reading the count register. This makes it possible to take timer interrupts immediately after a read of a possibly expired timer. Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
* target-mips: fix translation of MT instructionsNathan Froyd2010-12-221-4/+4
| | | | | | | | | | | | | | | | The translation of dmt/emt/dvpe/evpe was doing the moral equivalent of: int x; ... /* no initialization of x */ x = f (x); which confused later bits of TCG rather badly, leading to crashes. Fix the helpers to only return results (those instructions have no inputs), and fix the translation code accordingly. Signed-off-by: Nathan Froyd <froydnj@codesourcery.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* target-xxx: Use fprintf_function (format checking)Stefan Weil2010-10-301-7/+5Star
| | | | | | | | | | | | | fprintf_function uses format checking with GCC_FMT_ATTR. Format errors were fixed in * target-i386/helper.c * target-mips/translate.c * target-ppc/translate.c Cc: Blue Swirl <blauwirbel@gmail.com> Signed-off-by: Stefan Weil <weil@mail.berlios.de> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* mips: avoid write only variablesBlue Swirl2010-10-131-0/+29
| | | | | | | | | | Compiling with GCC 4.6.0 20100925 produced a lot of warnings like: /src/qemu/target-mips/translate.c: In function 'gen_ld': /src/qemu/target-mips/translate.c:1039:17: error: variable 'opn' set but not used [-Werror=unused-but-set-variable] Fix by adding a dummy cast so that the variable is not unused. Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* Correctly identify multiple cpus in SMP systemsHervé Poussineau2010-07-311-2/+1Star
| | | | | Signed-off-by: Hervé Poussineau <hpoussin@reactos.org> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* mips: more fixes to the MIPS interrupt glue logicAurelien Jarno2010-07-251-2/+10
| | | | | | | | | | Commit 36388314febad3d7675ab919287f03733a560ff6 moved most of the interrupt logic to cpu-exec.c. Remove the remaining useless code and fix software interrupts. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> Acked-by: Edgar E. Iglesias <edgar@axis.com> Tested-by: Edgar E. Iglesias <edgar@axis.com>
* target-mips: add loongson 2E & 2F integer instructionsAurelien Jarno2010-07-111-0/+271
| | | | | | | This patch adds support for loongson 2E & 2F instructions. They are the same instructions, but differ by the opcode encoding. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* target-mips: add Loongson support prefetchAurelien Jarno2010-07-011-35/+43
| | | | | | | Loongson CPU uses a load to zero register for prefetch. Emulate it as a NOP. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* target-mips: split load and storeAurelien Jarno2010-07-011-155/+183
| | | | Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* target-mips: fix DINSU instructionAurelien Jarno2010-06-301-1/+1
| | | | Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* target-mips: enable movn/movz on loongson 2E & 2FAurelien Jarno2010-06-291-1/+2
| | | | Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* target-mips: Fix compilationStefan Weil2010-06-091-1/+1
| | | | | | | | | TCGv t1 needs tcg_temp_free instead of tcg_temp_free_i32. Cc: Nathan Froyd <froydnj@codesourcery.com> Cc: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Stefan Weil <weil@mail.berlios.de> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* target-mips: microMIPS ASE supportNathan Froyd2010-06-091-5/+2385
| | | | | | | | Add instruction decoding for the microMIPS ASE. All we do is decode and then forward to the existing gen_* routines. Signed-off-by: Nathan Froyd <froydnj@codesourcery.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* target-mips: mips16 cleanupsNathan Froyd2010-06-091-7/+17
| | | | | | | | | | | Change code handling mips16-specific branches to use ISA-neutral special opcodes. Since there are several places where the delay slot requirements for microMIPS branches differ from mips16 branches, using opcodes is easier than checking hflags, then checking mips16 vs. microMIPS. Signed-off-by: Nathan Froyd <froydnj@codesourcery.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* target-mips: refactor c{, abs}.cond.fmt insnsNathan Froyd2010-06-091-83/+81Star
| | | | | | | | Move all knowledge about coprocessor-checking and register numbering into the gen_cmp* helper functions. Signed-off-by: Nathan Froyd <froydnj@codesourcery.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* target-mips: move FP FMT comments closer to the definitionsAurelien Jarno2010-06-091-14/+14
| | | | Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* target-mips: define constants for magic numbersNathan Froyd2010-06-091-142/+295
| | | | | | | | | Add FMT_* constants for the floating-point format field in opcodes and tweak a few places to use them. Add enums for various invocations of FOP and tweak gen_farith and its lone caller accordingly. Signed-off-by: Nathan Froyd <froydnj@codesourcery.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* target-mips: break out [ls][wd]c1 and rdhwr insn generationNathan Froyd2010-06-081-47/+59
| | | | | | Signed-off-by: Nathan Froyd <froydnj@codesourcery.com> Acked-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* target-mips: Remove duplicate CPU log.Richard Henderson2010-05-051-6/+0Star
| | | | | | | Logging for -d cpu is done in generic code. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* target-mips: Fix format specifiers for fpu_fprintfStefan Weil2010-04-091-14/+20
| | | | | | | | | | | In the previous patch which introduced fprintf_function to allow parameter checking by gcc some compiler warnings remained unfixed. These warnings are fixed here. Signed-off-by: Stefan Weil <weil@mail.berlios.de> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* target-mips: Fix one more format specifier for cpu_fprintfStefan Weil2010-04-081-1/+3
| | | | | | | env->bcond must be printed using TARGET_FMT_ld. Signed-off-by: Stefan Weil <weil@mail.berlios.de> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* remove TARGET_* defines from translate-all.cPaolo Bonzini2010-04-081-0/+2
| | | | | Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* target-mips: use newer logical opsAurelien Jarno2010-03-041-8/+4Star
| | | | Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* target-mips: use setcond when possibleAurelien Jarno2010-03-021-77/+20Star
| | | | Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* target-mips: fix ROTR and DROTR by zeroNathan Froyd2010-02-231-0/+4
| | | | | Signed-off-by: Nathan Froyd <froydnj@codesourcery.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* target-mips: fix CpU exception for coprocessor 0Nathan Froyd2010-02-231-1/+1
| | | | | | | | When we signal a CpU exception for coprocessor 0, we should indicate that it's for coprocessor 0 instead of coprocessor 1. Signed-off-by: Nathan Froyd <froydnj@codesourcery.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* target-mips: remove useless sign extensionAurelien Jarno2010-02-231-2/+0Star
| | | | Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* target-mips: fix user-mode emulation startupNathan Froyd2009-12-131-0/+8
| | | | | | | | | | | | | | | Running programs with the MIPS user-mode emulator fails during dynamic loading, as floating-point instructions are not enabled in in env->hflags. Move the code for doing so from fpu_init to cpu_reset so the MIPS_HFLAG_{FPU,F64} setting doesn't get clobbered by cpu_reset setting env->hflags to MIPS_HFLAG_UM. The same end can be achieved by swapping the ordering of fpu_init and cpu_reset in cpu_mips_init, but it seemed better to consolidate the CONFIG_USER_ONLY code into a single location. Signed-off-by: Nathan Froyd <froydnj@codesourcery.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* target-mips: add copyright notice for mips16 workNathan Froyd2009-12-131-0/+1
| | | | | | | Also cross off mips16 ASE in TODO. Signed-off-by: Nathan Froyd <froydnj@codesourcery.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* target-mips: add mips16 instruction decodingNathan Froyd2009-12-131-9/+1063
| | | | | | | | | | | | | | There's no good way to add this incrementally, so we do it all at once. The only changes to shared code are in handle_delay_slot. We need to flip ISAMode when doing a jump-and-exchange. We also need to set ISAMode the low bit of the target address for jump-to-register. Also, since we're now adding bits that can be in MIPS_HFLAG_BMASK_EXT, make sure we use MIPS_HFLAG_BMASK_BASE in the places where we just want basic information about a branch. Signed-off-by: Nathan Froyd <froydnj@codesourcery.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* target-mips: add enums for MIPS16 opcodesNathan Froyd2009-12-131-0/+112
| | | | | Signed-off-by: Nathan Froyd <froydnj@codesourcery.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* target-mips: split out delay slot handlingNathan Froyd2009-12-131-55/+79
| | | | | | | | Move delay slot handling to common code whose invocation can be controlled from gen_intermediate_code_internal. Signed-off-by: Nathan Froyd <froydnj@codesourcery.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* target-mips: add gen_base_offset_addrNathan Froyd2009-12-131-24/+16Star
| | | | | | | | This is a common pattern in existing code. We'll also use it to implement the mips16 SAVE/RESTORE instructions. Signed-off-by: Nathan Froyd <froydnj@codesourcery.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* target-mips: make gen_compute_branch 16/32-bit-awareNathan Froyd2009-12-131-7/+8
| | | | | Signed-off-by: Nathan Froyd <froydnj@codesourcery.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* target-mips: move ROTR and ROTRV inside gen_shift_{imm, }Nathan Froyd2009-12-131-139/+148
| | | | | | | | | | It's easier to implement mips16 shift instructions if we're not examining the opcode inside gen_shift_{imm,}. So move ROTR and ROTRV and do the special-case handling of SRL and SRLV inside decode_opc. Likewise for their 64-bit counterparts. Signed-off-by: Nathan Froyd <froydnj@codesourcery.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* target-mips: use physical address in lladdrAurelien Jarno2009-11-301-28/+13Star
| | | | | | | | Currently the ll/sc instructions use the virtual address in both user and system mode. Use the physical address insteead in system mode. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* target-mips: make CP0_LLAddr register CPU dependentAurelien Jarno2009-11-221-2/+5
| | | | | | | | Depending on the CPU, CP0_LLAddr is either read-only or read-write, and the returned value can be shifted by a variable amount of bits. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Hervé Poussineau <hpoussin@reactos.org>
* target-mips: rename CP0_LLAddr into lladdrAurelien Jarno2009-11-221-6/+6
| | | | | | | | The variable CP0_LLAddr represent the full lladdr, not the actual register value, which is only part of this value and depends on the CPU. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* target-mips: fix indentationAurelien Jarno2009-11-141-2/+2
| | | | Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* mips: fix cpu_reset memory leakBlue Swirl2009-11-141-4/+51
| | | | | | | | | Remove cpu_mips_register() - move mmu_init(), fpu_init() and mvp_init() into cpu_mips_init() - move the other parts in cpu_mips_init() Reported-by: Blue Swirl <blauwirbel@gmail.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* Revert "Get rid of _t suffix"Anthony Liguori2009-10-011-2/+2
| | | | | | | | | | | | In the very least, a change like this requires discussion on the list. The naming convention is goofy and it causes a massive merge problem. Something like this _must_ be presented on the list first so people can provide input and cope with it. This reverts commit 99a0949b720a0936da2052cb9a46db04ffc6db29. Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
* Get rid of _t suffixmalc2009-10-011-2/+2
| | | | | | | Some not so obvious bits, slirp and Xen were left alone for the time being. Signed-off-by: malc <av1474@comtv.ru>
* target-mips: make sure constants are in the second argumentAurelien Jarno2009-09-301-7/+7
| | | | Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* mips: Fix spelling in commentStefan Weil2009-09-301-2/+2
| | | | | | | | | inofficial -> unofficial Thanks to Blue Swirl. Signed-off-by: Stefan Weil <weil@mail.berlios.de> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* target-mips: log instructions start in TCG codeAurelien Jarno2009-09-281-0/+4
| | | | Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* target-mips: remove MAX_OP_PER_INSTR workaroundAurelien Jarno2009-09-231-2/+1Star
| | | | | | | Now that MAX_OP_PER_INSTR has been increased to a safer value, removed the target-mips specific workaround. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* target-mips: fix single-steppingNathan Froyd2009-09-141-3/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | Single-stepping branches on MIPS didn't work right, because the generation of EXCP_DEBUG happened after the generation of the code to exit the current TB. That is, given the code: bne v0,v1,target nop ... target: addu v0,v0,v1 1: when you single-stepped through the NOP, execution wouldn't actually halt until you reached the label `1'. This patch corrects that and also changes single-stepping so that a branch and its delay slot are executed as one instruction for the purposes of single-stepping. This behavior is comparable to what other MIPS tools (e.g. MIPSsim with MDI) do. GDB avoids placing breakpoints in branch delay slots, so this change doesn't break anything on the GDB side. Signed-off-by: Nathan Froyd <froydnj@codesourcery.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
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