| Commit message (Expand) | Author | Age | Files | Lines |
* | tcg: Add type for vCPU pointers | LluĂs Vilanova | 2016-03-01 | 1 | -1/+1 |
* | tcg: Change tcg_global_mem_new_* to take a TCGv_ptr | Richard Henderson | 2016-02-09 | 1 | -2/+2 |
* | log: do not unnecessarily include qom/cpu.h | Paolo Bonzini | 2016-02-03 | 1 | -0/+1 |
* | tilegx: Clean up includes | Peter Maydell | 2016-01-29 | 1 | -0/+1 |
* | target-tilegx: Implement prefetch instructions in pipe y2 | Chen Gang | 2015-10-22 | 1 | -8/+14 |
* | Merge remote-tracking branch 'remotes/rth/tags/pull-tcg-20151007' into staging | Peter Maydell | 2015-10-08 | 1 | -44/+14 |
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| * | tcg: Remove gen_intermediate_code_pc | Richard Henderson | 2015-10-07 | 1 | -37/+4 |
| * | tcg: Pass data argument to restore_state_to_opc | Richard Henderson | 2015-10-07 | 1 | -2/+3 |
| * | tcg: Add TCG_MAX_INSNS | Richard Henderson | 2015-10-07 | 1 | -0/+3 |
| * | target-*: Increment num_insns immediately after tcg_gen_insn_start | Richard Henderson | 2015-10-07 | 1 | -1/+2 |
| * | target-*: Unconditionally emit tcg_gen_insn_start | Richard Henderson | 2015-10-07 | 1 | -4/+2 |
| * | tcg: Rename debug_insn_start to insn_start | Richard Henderson | 2015-10-07 | 1 | -1/+1 |
* | | target-tilegx: Support iret instruction and related special registers | Chen Gang | 2015-10-07 | 1 | -1/+13 |
* | | target-tilegx: Use TILEGX_EXCP_OPCODE_UNKNOWN and TILEGX_EXCP_OPCODE_UNIMPLEM... | Chen Gang | 2015-10-07 | 1 | -17/+24 |
* | | target-tilegx: Implement v2mults instruction | Chen Gang | 2015-10-07 | 1 | -0/+4 |
* | | target-tilegx: Implement v?int_* instructions. | Chen Gang | 2015-10-07 | 1 | -0/+14 |
* | | target-tilegx: Implement v2sh* instructions | Chen Gang | 2015-10-07 | 1 | -1/+17 |
* | | target-tilegx: Handle nofault prefetch instructions | Richard Henderson | 2015-10-07 | 1 | -14/+26 |
* | | target-tilegx: Fix a typo for mnemonic about "ld_add" | Chen Gang | 2015-10-07 | 1 | -1/+1 |
* | | target-tilegx: Decode ill pseudo-instructions | Chen Gang | 2015-10-07 | 1 | -14/+67 |
* | | target-tilegx: Let x1 pipe process bpt instruction only | Chen Gang | 2015-10-07 | 1 | -1/+7 |
* | | target-tilegx: Implement complex multiply instructions | Richard Henderson | 2015-10-07 | 1 | -1/+30 |
* | | target-tilegx: Implement table index instructions | Richard Henderson | 2015-10-07 | 1 | -0/+15 |
* | | target-tilegx: Implement crc instructions | Richard Henderson | 2015-10-07 | 1 | -1/+7 |
* | | target-tilegx: Implement v1multu instruction | Chen Gang | 2015-10-07 | 1 | -0/+4 |
* | | target-tilegx: Implement v*add and v*sub instructions | Chen Gang | 2015-10-07 | 1 | -21/+116 |
* | | target-tilegx: Implement v*shl, v*shru, and v*shrs instructions | Chen Gang | 2015-10-07 | 1 | -0/+39 |
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* | target-tilegx: Handle v1shl, v1shru, v1shrs | Richard Henderson | 2015-09-15 | 1 | -1/+16 |
* | target-tilegx: Handle v1shli, v1shrui | Richard Henderson | 2015-09-15 | 1 | -0/+14 |
* | target-tilegx: Handle v4int_l/h | Richard Henderson | 2015-09-15 | 1 | -0/+8 |
* | target-tilegx: Handle atomic instructions | Richard Henderson | 2015-09-15 | 1 | -1/+79 |
* | target-tilegx: Handle mtspr, mfspr | Richard Henderson | 2015-09-15 | 1 | -3/+73 |
* | target-tilegx: Handle v1cmpeq, v1cmpne | Richard Henderson | 2015-09-15 | 1 | -0/+51 |
* | target-tilegx: Handle mask instructions | Richard Henderson | 2015-09-15 | 1 | -2/+9 |
* | target-tilegx: Handle scalar multiply instructions | Richard Henderson | 2015-09-15 | 1 | -0/+112 |
* | target-tilegx: Handle conditional move instructions | Richard Henderson | 2015-09-15 | 1 | -1/+8 |
* | target-tilegx: Handle shift instructions | Richard Henderson | 2015-09-15 | 1 | -2/+54 |
* | target-tilegx: Handle bitfield instructions | Richard Henderson | 2015-09-15 | 1 | -0/+74 |
* | target-tilegx: Implement system and memory management instructions | Richard Henderson | 2015-09-15 | 1 | -23/+54 |
* | target-tilegx: Handle comparison instructions | Richard Henderson | 2015-09-15 | 1 | -6/+33 |
* | target-tilegx: Handle conditional branch instructions | Richard Henderson | 2015-09-15 | 1 | -13/+38 |
* | target-tilegx: Handle unconditional jump instructions | Richard Henderson | 2015-09-15 | 1 | -17/+41 |
* | target-tilegx: Handle post-increment load and store instructions | Richard Henderson | 2015-09-15 | 1 | -8/+86 |
* | target-tilegx: Handle basic load and store instructions | Richard Henderson | 2015-09-15 | 1 | -15/+115 |
* | target-tilegx: Handle most bit manipulation instructions | Richard Henderson | 2015-09-15 | 1 | -1/+67 |
* | target-tilegx: Handle arithmetic instructions | Richard Henderson | 2015-09-15 | 1 | -6/+90 |
* | target-tilegx: Handle simple logical operations | Richard Henderson | 2015-09-15 | 1 | -3/+96 |
* | target-tilegx: Framework for decoding bundles | Richard Henderson | 2015-09-15 | 1 | -0/+1145 |