| Commit message (Expand) | Author | Age | Files | Lines |
|---|
| ... | |
| * | target/arm: Convert T16 branch and exchange | Richard Henderson | 2019-09-05 | 1 | -41/+29 |
| * | target/arm: Convert T16 one low register and immediate | Richard Henderson | 2019-09-05 | 1 | -42/+2 |
| * | target/arm: Convert T16 add/sub (3 low, 2 low and imm) | Richard Henderson | 2019-09-05 | 1 | -24/+2 |
| * | target/arm: Convert T16 load/store multiple | Richard Henderson | 2019-09-05 | 1 | -39/+9 |
| * | target/arm: Convert T16 add pc/sp (immediate) | Richard Henderson | 2019-09-05 | 1 | -11/+1 |
| * | target/arm: Convert T16 load/store (immediate offset) | Richard Henderson | 2019-09-05 | 1 | -89/+5 |
| * | target/arm: Convert T16 load/store (register offset) | Richard Henderson | 2019-09-05 | 1 | -49/+2 |
| * | target/arm: Convert T16 data-processing (two low regs) | Richard Henderson | 2019-09-05 | 1 | -145/+7 |
| * | target/arm: Add skeleton for T16 decodetree | Richard Henderson | 2019-09-05 | 1 | -0/+6 |
| * | target/arm: Simplify disas_arm_insn | Richard Henderson | 2019-09-05 | 1 | -53/+16 |
| * | target/arm: Simplify disas_thumb2_insn | Richard Henderson | 2019-09-05 | 1 | -76/+3 |
| * | target/arm: Convert TT | Richard Henderson | 2019-09-05 | 1 | -60/+30 |
| * | target/arm: Convert SG | Richard Henderson | 2019-09-05 | 1 | -22/+29 |
| * | target/arm: Convert Table Branch | Richard Henderson | 2019-09-05 | 1 | -23/+34 |
| * | target/arm: Convert Unallocated memory hint | Richard Henderson | 2019-09-05 | 1 | -8/+0 |
| * | target/arm: Convert PLI, PLD, PLDW | Richard Henderson | 2019-09-05 | 1 | -17/+20 |
| * | target/arm: Convert SETEND | Richard Henderson | 2019-09-05 | 1 | -9/+13 |
| * | target/arm: Convert CPS (privileged) | Richard Henderson | 2019-09-05 | 1 | -51/+40 |
| * | target/arm: Convert Clear-Exclusive, Barriers | Richard Henderson | 2019-09-05 | 1 | -69/+58 |
| * | target/arm: Convert RFE and SRS | Richard Henderson | 2019-09-05 | 1 | -89/+55 |
| * | target/arm: Convert SVC | Richard Henderson | 2019-09-05 | 1 | -6/+13 |
| * | target/arm: Convert B, BL, BLX (immediate) | Richard Henderson | 2019-09-05 | 1 | -75/+58 |
| * | target/arm: Diagnose base == pc for LDM/STM | Richard Henderson | 2019-09-05 | 1 | -2/+3 |
| * | target/arm: Diagnose too few registers in list for LDM/STM | Richard Henderson | 2019-09-05 | 1 | -8/+18 |
| * | target/arm: Diagnose writeback register in list for LDM for v7 | Richard Henderson | 2019-09-05 | 1 | -0/+9 |
| * | target/arm: Convert LDM, STM | Richard Henderson | 2019-09-05 | 1 | -198/+230 |
| * | target/arm: Convert MOVW, MOVT | Richard Henderson | 2019-09-05 | 1 | -56/+33 |
| * | target/arm: Convert Signed multiply, signed and unsigned divide | Richard Henderson | 2019-09-05 | 1 | -272/+218 |
| * | target/arm: Convert packing, unpacking, saturation, and reversal | Richard Henderson | 2019-09-05 | 1 | -309/+232 |
| * | target/arm: Convert Parallel addition and subtraction | Richard Henderson | 2019-09-05 | 1 | -117/+112 |
| * | target/arm: Convert USAD8, USADA8, SBFX, UBFX, BFC, BFI, UDF | Richard Henderson | 2019-09-05 | 1 | -96/+105 |
| * | target/arm: Diagnose UNPREDICTABLE ldrex/strex cases | Richard Henderson | 2019-09-05 | 1 | -2/+38 |
| * | target/arm: Convert Synchronization primitives | Richard Henderson | 2019-09-05 | 1 | -258/+318 |
| * | target/arm: Convert load/store (register, immediate, literal) | Richard Henderson | 2019-09-05 | 1 | -443/+362 |
| * | target/arm: Convert T32 ADDW/SUBW | Richard Henderson | 2019-09-05 | 1 | -11/+13 |
| * | target/arm: Convert the rest of A32 Miscelaneous instructions | Richard Henderson | 2019-09-05 | 1 | -82/+45 |
| * | target/arm: Convert ERET | Richard Henderson | 2019-09-05 | 1 | -39/+23 |
| * | target/arm: Convert CLZ | Richard Henderson | 2019-09-05 | 1 | -16/+15 |
| * | target/arm: Convert BX, BXJ, BLX (register) | Richard Henderson | 2019-09-05 | 1 | -40/+38 |
| * | target/arm: Convert Cyclic Redundancy Check | Richard Henderson | 2019-09-05 | 1 | -65/+56 |
| * | target/arm: Convert MRS/MSR (banked, register) | Richard Henderson | 2019-09-05 | 1 | -129/+97 |
| * | target/arm: Convert MSR (immediate) and hints | Richard Henderson | 2019-09-05 | 1 | -18/+42 |
| * | target/arm: Simplify op_smlawx for SMLAW* | Richard Henderson | 2019-09-05 | 1 | -8/+8 |
| * | target/arm: Simplify op_smlaxxx for SMLAL* | Richard Henderson | 2019-09-05 | 1 | -7/+8 |
| * | target/arm: Convert Halfword multiply and multiply accumulate | Richard Henderson | 2019-09-05 | 1 | -97/+121 |
| * | target/arm: Convert Saturating addition and subtraction | Richard Henderson | 2019-09-05 | 1 | -27/+48 |
| * | target/arm: Simplify UMAAL | Richard Henderson | 2019-09-05 | 1 | -22/+12 |
| * | target/arm: Convert multiply and multiply accumulate | Richard Henderson | 2019-09-05 | 1 | -107/+141 |
| * | target/arm: Convert Data Processing (immediate) | Richard Henderson | 2019-09-05 | 1 | -334/+115 |
| * | target/arm: Convert Data Processing (reg-shifted-reg) | Richard Henderson | 2019-09-05 | 1 | -20/+54 |
