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* target/arm: Remove default_exception_elRichard Henderson2022-06-101-5/+0Star
| | | | | | | | | | This function is no longer used. At the same time, remove DisasContext.secure_routed_to_el3, as it in turn becomes unused. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220609202901.1177572-21-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* target/arm: Introduce helper_exception_with_syndromeRichard Henderson2022-06-101-5/+13
| | | | | | | | | | | | With the helper we can use exception_target_el at runtime, instead of default_exception_el at translate time. While we're at it, remove the DisasContext parameter from gen_exception, as it is no longer used. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220609202901.1177572-20-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* target/arm: Introduce gen_exception_el_vRichard Henderson2022-06-101-5/+8
| | | | | | | | | | Split out a common helper function for gen_exception_el and gen_exception_insn_el_v. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220609202901.1177572-19-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* target/arm: Introduce gen_exceptionRichard Henderson2022-06-101-4/+7
| | | | | | | | | | Create a new wrapper function that passes the default exception target to gen_exception_el. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220609202901.1177572-18-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* target/arm: Rename gen_exception to gen_exception_elRichard Henderson2022-06-101-9/+9
| | | | | | | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220609202901.1177572-17-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* target/arm: Move gen_exception to translate.cRichard Henderson2022-06-101-0/+7
| | | | | | | | | This function is not required by any other translation file. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220609202901.1177572-16-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* target/arm: Remove TBFLAG_ANY.DEBUG_TARGET_ELRichard Henderson2022-06-101-1/+0Star
| | | | | | | | | | We no longer need this value during translation, as it is now handled within the helpers. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220609202901.1177572-15-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* target/arm: Introduce gen_exception_insnRichard Henderson2022-06-101-16/+13Star
| | | | | | | | | | Create a new wrapper function that passes the default exception target to gen_exception_insn_el. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220609202901.1177572-13-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* target/arm: Rename gen_exception_insn to gen_exception_insn_elRichard Henderson2022-06-101-19/+20
| | | | | | | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220609202901.1177572-12-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* target/arm: Introduce gen_exception_insn_el_vRichard Henderson2022-06-101-15/+12Star
| | | | | | | | | | Create a function below gen_exception_insn that takes the target_el as a TCGv_i32, replacing gen_exception_el. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220609202901.1177572-11-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* target/arm: Rename helper_exception_with_syndromeRichard Henderson2022-06-101-3/+3
| | | | | | | | | | Rename to helper_exception_with_syndrome_el, to emphasize that the target el is a parameter. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220609202901.1177572-10-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* target/arm: Implement ESB instructionRichard Henderson2022-05-091-0/+23
| | | | | | | | | Check for and defer any pending virtual SError. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220506180242.216785-17-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* target/arm: Avoid bare abort() or assert(0)Richard Henderson2022-05-051-2/+2
| | | | | | | | | | Standardize on g_assert_not_reached() for "should not happen". Retain abort() when preceeded by fprintf or error_report. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20220501055028.646596-7-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* target/arm: Reorg ARMCPRegInfo type field bitsRichard Henderson2022-05-051-2/+4
| | | | | | | | | | | | | | Instead of defining ARM_CP_FLAG_MASK to remove flags, define ARM_CP_SPECIAL_MASK to isolate special cases. Sort the specials to the low bits. Use an enum. Split the large comment block so as to document each value separately. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20220501055028.646596-6-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* target/arm: Split out cpregs.hRichard Henderson2022-05-051-2/+1Star
| | | | | | | | | | | Move ARMCPRegInfo and all related declarations to a new internal header, out of the public cpu.h. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220501055028.646596-2-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* target/arm: Use tcg_constant in trans_CSELRichard Henderson2022-04-281-4/+3Star
| | | | | | | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20220426163043.100432-36-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* target/arm: Use tcg_constant in trans_CPS_v7mRichard Henderson2022-04-281-6/+3Star
| | | | | | | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20220426163043.100432-35-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* target/arm: Use tcg_constant in CLRM, DLS, WLS, LERichard Henderson2022-04-281-11/+5Star
| | | | | | | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20220426163043.100432-34-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* target/arm: Use tcg_constant in LDM, STMRichard Henderson2022-04-281-8/+4Star
| | | | | | | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20220426163043.100432-33-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* target/arm: Use tcg_constant for TT, SAT, SMMLARichard Henderson2022-04-281-9/+5Star
| | | | | | | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20220426163043.100432-32-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* target/arm: Use tcg_constant for v7m MRS, MSRRichard Henderson2022-04-281-4/+3Star
| | | | | | | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20220426163043.100432-31-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* target/arm: Use tcg_constant for MOVW, UMAAL, CRC32Richard Henderson2022-04-281-8/+3Star
| | | | | | | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20220426163043.100432-30-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* target/arm: Use tcg_constant for op_s_{rri,rxi}_rotRichard Henderson2022-04-281-6/+5Star
| | | | | | | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20220426163043.100432-29-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* target/arm: Use tcg_constant for gen_srsRichard Henderson2022-04-281-6/+2Star
| | | | | | | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20220426163043.100432-28-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* target/arm: Use tcg_constant for do_coproc_insnRichard Henderson2022-04-281-30/+13Star
| | | | | | | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20220426163043.100432-27-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* target/arm: Use tcg_constant for vector shift expandersRichard Henderson2022-04-281-18/+9Star
| | | | | | | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20220426163043.100432-26-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* target/arm: Use tcg_constant for gen_{msr,mrs}Richard Henderson2022-04-281-13/+9Star
| | | | | | | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20220426163043.100432-25-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* target/arm: Use tcg_constant for disas_iwmmxt_insnRichard Henderson2022-04-281-15/+10Star
| | | | | | | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20220426163043.100432-24-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* target/arm: Use tcg_constant for aa32 exceptionsRichard Henderson2022-04-281-25/+7Star
| | | | | | | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20220426163043.100432-23-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* target/arm: Simplify aa32 DISAS_WFIRichard Henderson2022-04-221-8/+4Star
| | | | | | | | | | The length of the previous insn may be computed from the difference of start and end addresses. Use tcg_constant_i32 while we're at it. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* target/arm: Simplify gen_sarRichard Henderson2022-04-221-5/+3Star
| | | | | | | | | Use tcg_gen_umin_i32 instead of tcg_gen_movcond_i32. Use tcg_constant_i32 while we're at it. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* target/arm: Simplify GEN_SHIFT in translate.cRichard Henderson2022-04-221-10/+8Star
| | | | | | | | | | | | | | | | | | | Instead of computing tmp1 = shift & 0xff; dest = (tmp1 > 0x1f ? 0 : value) << (tmp1 & 0x1f) use tmpd = value << (shift & 0x1f); dest = shift & 0xe0 ? 0 : tmpd; which has a flatter dependency tree. Use tcg_constant_i32 while we're at it. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* target/arm: Split out gen_rebuild_hflagsRichard Henderson2022-04-221-16/+24
| | | | | | | | | | For aa32, the function has a parameter to use the new el. For aa64, that never happens. Use tcg_constant_i32 while we're at it. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* target/arm: Extend store_cpu_offset to take field sizeRichard Henderson2022-04-221-1/+20
| | | | | | | | | | Currently we assume all fields are 32-bit. Prepare for fields of a single byte, using sizeof_field(). Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> [PMM: use sizeof_field() instead of raw sizeof()] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* target/arm: Change DisasContext.aarch64 to boolRichard Henderson2022-04-221-1/+1
| | | | | | | | | | Bool is a more appropriate type for this value. Move the member down in the struct to keep the bool type members together and remove a hole. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* exec/translator: Pass the locked filepointer to disas_log hookRichard Henderson2022-04-201-3/+4
| | | | | | | | | | We have fetched and locked the logfile in translator_loop. Pass the filepointer down to the disas_log hook so that it need not be fetched and locked again. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220417183019.755276-13-richard.henderson@linaro.org>
* Replace config-time define HOST_WORDS_BIGENDIANMarc-André Lureau2022-04-061-1/+1
| | | | | | | | | | | | | | | | | | | Replace a config-time define with a compile time condition define (compatible with clang and gcc) that must be declared prior to its usage. This avoids having a global configure time define, but also prevents from bad usage, if the config header wasn't included before. This can help to make some code independent from qemu too. gcc supports __BYTE_ORDER__ from about 4.6 and clang from 3.2. Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com> [ For the s390x parts I'm involved in ] Acked-by: Halil Pasic <pasic@linux.ibm.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220323155743.1585078-7-marcandre.lureau@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
* exec/memop: Adding signedness to quad definitionsFrédéric Pétrot2022-01-081-1/+1
| | | | | | | | | | | | | | Renaming defines for quad in their various forms so that their signedness is now explicit. Done using git grep as suggested by Philippe, with a bit of hand edition to keep assignments aligned. Signed-off-by: Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20220106210108.138226-2-frederic.petrot@univ-grenoble-alpes.fr Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
* target/arm: Assert thumb pc is alignedRichard Henderson2021-12-151-0/+3
| | | | | | | | | | | | | Misaligned thumb PC is architecturally impossible. Assert is better than proceeding, in case we've missed something somewhere. Expand a comment about aligning the pc in gdbstub. Fail an incoming migrate if a thumb pc is misaligned. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* target/arm: Take an exception if PC is misalignedRichard Henderson2021-12-151-1/+21
| | | | | | | | | | | | | | | | | | For A64, any input to an indirect branch can cause this. For A32, many indirect branch paths force the branch to be aligned, but BXWritePC does not. This includes the BX instruction but also other interworking changes to PC. Prior to v8, this case is UNDEFINED. With v8, this is CONSTRAINED UNPREDICTABLE and may either raise an exception or force align the PC. We choose to raise an exception because we have the infrastructure, it makes the generated code for gen_bx simpler, and it has the possibility of catching more guest bugs. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* target/arm: Split arm_pre_translate_insnRichard Henderson2021-12-151-3/+7
| | | | | | | | | | | | | Create arm_check_ss_active and arm_check_kernelpage. Reverse the order of the tests. While it doesn't matter in practice, because only user-only has a kernel page and user-only never sets ss_active, ss_active has priority over execution exceptions and it is best to keep them in the proper order. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* target/arm: Hoist pc_next to a local variable in thumb_tr_translate_insnRichard Henderson2021-12-151-8/+8
| | | | | | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* target/arm: Hoist pc_next to a local variable in arm_tr_translate_insnRichard Henderson2021-12-151-4/+5
| | | | | | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* target/arm: Use tcg_constant_i32() in gen_rev16()Philippe Mathieu-Daudé2021-11-021-2/+1Star
| | | | | | | | | | Since the mask is a constant value, use tcg_constant_i32() instead of a TCG temporary. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20211029231834.2476117-6-f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* target/arm: Use the constant variant of store_cpu_field() when possiblePhilippe Mathieu-Daudé2021-11-021-15/+6Star
| | | | | | | | | | When using a constant variable, we can replace the store_cpu_field() call by store_cpu_field_constant() which avoid using TCG temporaries. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20211029231834.2476117-4-f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* target/arm: Use tcg_constant_i32() in op_smlad()Philippe Mathieu-Daudé2021-11-021-2/+1Star
| | | | | | | | | Avoid using a TCG temporary for a read-only constant. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20211029231834.2476117-2-f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* target/arm: Drop checks for singlestep_enabledRichard Henderson2021-10-161-30/+6Star
| | | | | | GDB single-stepping is now handled generically. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* target/arm: Add TB flag for "MVE insns not predicated"Peter Maydell2021-09-211-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | Our current codegen for MVE always calls out to helper functions, because some byte lanes might be predicated. The common case is that in fact there is no predication active and all lanes should be updated together, so we can produce better code by detecting that and using the TCG generic vector infrastructure. Add a TB flag that is set when we can guarantee that there is no active MVE predication, and a bool in the DisasContext. Subsequent patches will use this flag to generate improved code for some instructions. In most cases when the predication state changes we simply end the TB after that instruction. For the code called from vfp_access_check() that handles lazy state preservation and creating a new FP context, we can usually avoid having to try to end the TB because luckily the new value of the flag following the register changes in those sequences doesn't depend on any runtime decisions. We do have to end the TB if the guest has enabled lazy FP state preservation but not automatic state preservation, but this is an odd corner case that is not going to be common in real-world code. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210913095440.13462-4-peter.maydell@linaro.org
* target/arm: Avoid goto_tb if we're trying to exit to the main loopPeter Maydell2021-09-211-1/+33
| | | | | | | | | | | | | | | | | | | | | Currently gen_jmp_tb() assumes that if it is called then the jump it is handling is the only reason that we might be trying to end the TB, so it will use goto_tb if it can. This is usually the case: mostly "we did something that means we must end the TB" happens on a non-branch instruction. However, there are cases where we decide early in handling an instruction that we need to end the TB and return to the main loop, and then the insn is a complex one that involves gen_jmp_tb(). For instance, for M-profile FP instructions, in gen_preserve_fp_state() which is called from vfp_access_check() we want to force an exit to the main loop if lazy state preservation is active and we are in icount mode. Make gen_jmp_tb() look at the current value of is_jmp, and only use goto_tb if the previous is_jmp was DISAS_NEXT or DISAS_TOO_MANY. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210913095440.13462-2-peter.maydell@linaro.org
* accel/tcg: Add DisasContextBase argument to translator_ld*Ilya Leoshkevich2021-09-141-4/+5
| | | | | | Signed-off-by: Ilya Leoshkevich <iii@linux.ibm.com> [rth: Split out of a larger patch.] Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
generated by cgit v1.2.3-55-g7522 (git 2.39.0) at 2025-01-30 17:40:20 +0100