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| * | target/arm: Pass HCR to attribute subroutines.Richard Henderson2022-10-101-13/+17
| * | target/arm: Remove env argument from combined_attrs_fwbRichard Henderson2022-10-101-3/+2Star
| * | target/arm: Hoist read of *is_secure in S1_ptw_translateRichard Henderson2022-10-101-10/+12
| * | target/arm: Introduce arm_hcr_el2_eff_secstateRichard Henderson2022-10-102-10/+21
| * | target/arm: Drop secure check for HCR.TGE vs SCTLR_EL1.MRichard Henderson2022-10-101-2/+2
| * | target/arm: Reorg regime_translation_disabledRichard Henderson2022-10-101-7/+25
| * | target/arm: Fold secure and non-secure a-profile mmu indexesRichard Henderson2022-10-107-203/+85Star
| * | target/arm: Add is_secure parameter to do_ats_writeRichard Henderson2022-10-101-5/+14
| * | target/arm: Merge regime_is_secure into get_phys_addrRichard Henderson2022-10-102-44/+42Star
| * | target/arm: Add TBFLAG_M32.SECURERichard Henderson2022-10-103-2/+7
| * | target/arm: Add is_secure parameter to v7m_read_half_insnRichard Henderson2022-10-101-5/+4Star
| * | target/arm: Split out get_phys_addr_with_secureRichard Henderson2022-10-102-29/+55
| * | target/arm: Add is_secure parameter to regime_translation_disabledRichard Henderson2022-10-101-9/+11
| * | target/arm: Fix S2 disabled check in S1_ptw_translateRichard Henderson2022-10-101-3/+3
| * | target/arm: Add is_secure parameter to get_phys_addr_lpaeRichard Henderson2022-10-101-10/+10
| * | target/arm: Make the final stage1+2 write to secure be unconditionalRichard Henderson2022-10-101-11/+10Star
| * | target/arm: Split s2walk_secure from ipa_secure in get_phys_addrRichard Henderson2022-10-101-9/+9
| * | target/arm: allow setting SCR_EL3.EnTP2 when FEAT_SME is implementedJerome Forissier2022-10-102-28/+31
| * | target/arm/kvm: Retry KVM_CREATE_VM call if it fails EINTRPeter Maydell2022-10-101-1/+3
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* / dump: Replace opaque DumpState pointer with a typed oneJanosch Frank2022-10-062-6/+4Star
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* accel/tcg: Introduce tb_pc and log_pcRichard Henderson2022-10-041-2/+2
* hw/core: Add CPUClass.get_pcRichard Henderson2022-10-041-0/+13
* accel/tcg: Rename CPUIOTLBEntry to CPUTLBEntryFullRichard Henderson2022-10-043-10/+10
* target/arm: mark SP_EL1 with ARM_CP_EL3_NO_EL2_KEEPJerome Forissier2022-09-291-1/+1
* target/arm: Rearrange cpu64.c so all the CPU initfns are togetherPeter Maydell2022-09-291-356/+356
* target/arm: Update SDCR_VALID_MASK to include SCCDPeter Maydell2022-09-291-1/+7
* target/arm: Make writes to MDCR_EL3 use PMU start/finish callsPeter Maydell2022-09-291-4/+14
* target/arm: Mark registers which call pmu_op_start() as ARM_CP_IOPeter Maydell2022-09-291-6/+6
* target/arm: Add is_secure parameter to get_phys_addr_pmsav5Richard Henderson2022-09-221-2/+2
* target/arm: Add secure parameter to get_phys_addr_pmsav7Richard Henderson2022-09-221-3/+2Star
* target/arm: Add is_secure parameter to pmsav7_use_background_regionRichard Henderson2022-09-221-5/+5
* target/arm: Add secure parameter to get_phys_addr_pmsav8Richard Henderson2022-09-221-3/+2Star
* target/arm: Add is_secure parameter to get_phys_addr_v6Richard Henderson2022-09-221-6/+5Star
* target/arm: Add is_secure parameter to get_phys_addr_v5Richard Henderson2022-09-221-7/+7
* target/arm: Add secure parameter to pmsav8_mpu_lookupRichard Henderson2022-09-223-7/+6Star
* target/arm: Add is_secure parameter to v8m_security_lookupRichard Henderson2022-09-223-8/+12
* target/arm: Remove is_subpage argument to pmsav8_mpu_lookupRichard Henderson2022-09-223-15/+15
* target/arm: Use GetPhysAddrResult in pmsav8_mpu_lookupRichard Henderson2022-09-223-26/+21Star
* target/arm: Use GetPhysAddrResult in get_phys_addr_pmsav8Richard Henderson2022-09-221-14/+14
* target/arm: Use GetPhysAddrResult in get_phys_addr_pmsav7Richard Henderson2022-09-221-19/+17Star
* target/arm: Use GetPhysAddrResult in get_phys_addr_pmsav5Richard Henderson2022-09-221-12/+12
* target/arm: Use GetPhysAddrResult in get_phys_addr_v5Richard Henderson2022-09-221-14/+11Star
* target/arm: Use GetPhysAddrResult in get_phys_addr_v6Richard Henderson2022-09-221-16/+14Star
* target/arm: Use GetPhysAddrResult in get_phys_addr_lpaeRichard Henderson2022-09-221-43/+26Star
* target/arm: Create GetPhysAddrResultRichard Henderson2022-09-225-125/+109Star
* target/arm: Fix alignment for VLD4.32Clément Chigot2022-09-221-1/+5
* Merge tag 'pull-semi-20220914' of https://gitlab.com/rth7680/qemu into stagingStefan Hajnoczi2022-09-172-23/+5Star
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| * target/arm: Honour -semihosting-config userspace=onPeter Maydell2022-09-132-23/+5Star
| * semihosting: Allow optional use of semihosting from userspacePeter Maydell2022-09-132-4/+4
* | target/arm: Report FEAT_PMUv3p5 for TCG '-cpu max'Peter Maydell2022-09-142-2/+2