| Commit message (Expand) | Author | Age | Files | Lines |
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| * | | target/arm: Pass HCR to attribute subroutines. | Richard Henderson | 2022-10-10 | 1 | -13/+17 |
| * | | target/arm: Remove env argument from combined_attrs_fwb | Richard Henderson | 2022-10-10 | 1 | -3/+2 |
| * | | target/arm: Hoist read of *is_secure in S1_ptw_translate | Richard Henderson | 2022-10-10 | 1 | -10/+12 |
| * | | target/arm: Introduce arm_hcr_el2_eff_secstate | Richard Henderson | 2022-10-10 | 2 | -10/+21 |
| * | | target/arm: Drop secure check for HCR.TGE vs SCTLR_EL1.M | Richard Henderson | 2022-10-10 | 1 | -2/+2 |
| * | | target/arm: Reorg regime_translation_disabled | Richard Henderson | 2022-10-10 | 1 | -7/+25 |
| * | | target/arm: Fold secure and non-secure a-profile mmu indexes | Richard Henderson | 2022-10-10 | 7 | -203/+85 |
| * | | target/arm: Add is_secure parameter to do_ats_write | Richard Henderson | 2022-10-10 | 1 | -5/+14 |
| * | | target/arm: Merge regime_is_secure into get_phys_addr | Richard Henderson | 2022-10-10 | 2 | -44/+42 |
| * | | target/arm: Add TBFLAG_M32.SECURE | Richard Henderson | 2022-10-10 | 3 | -2/+7 |
| * | | target/arm: Add is_secure parameter to v7m_read_half_insn | Richard Henderson | 2022-10-10 | 1 | -5/+4 |
| * | | target/arm: Split out get_phys_addr_with_secure | Richard Henderson | 2022-10-10 | 2 | -29/+55 |
| * | | target/arm: Add is_secure parameter to regime_translation_disabled | Richard Henderson | 2022-10-10 | 1 | -9/+11 |
| * | | target/arm: Fix S2 disabled check in S1_ptw_translate | Richard Henderson | 2022-10-10 | 1 | -3/+3 |
| * | | target/arm: Add is_secure parameter to get_phys_addr_lpae | Richard Henderson | 2022-10-10 | 1 | -10/+10 |
| * | | target/arm: Make the final stage1+2 write to secure be unconditional | Richard Henderson | 2022-10-10 | 1 | -11/+10 |
| * | | target/arm: Split s2walk_secure from ipa_secure in get_phys_addr | Richard Henderson | 2022-10-10 | 1 | -9/+9 |
| * | | target/arm: allow setting SCR_EL3.EnTP2 when FEAT_SME is implemented | Jerome Forissier | 2022-10-10 | 2 | -28/+31 |
| * | | target/arm/kvm: Retry KVM_CREATE_VM call if it fails EINTR | Peter Maydell | 2022-10-10 | 1 | -1/+3 |
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* / | dump: Replace opaque DumpState pointer with a typed one | Janosch Frank | 2022-10-06 | 2 | -6/+4 |
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* | accel/tcg: Introduce tb_pc and log_pc | Richard Henderson | 2022-10-04 | 1 | -2/+2 |
* | hw/core: Add CPUClass.get_pc | Richard Henderson | 2022-10-04 | 1 | -0/+13 |
* | accel/tcg: Rename CPUIOTLBEntry to CPUTLBEntryFull | Richard Henderson | 2022-10-04 | 3 | -10/+10 |
* | target/arm: mark SP_EL1 with ARM_CP_EL3_NO_EL2_KEEP | Jerome Forissier | 2022-09-29 | 1 | -1/+1 |
* | target/arm: Rearrange cpu64.c so all the CPU initfns are together | Peter Maydell | 2022-09-29 | 1 | -356/+356 |
* | target/arm: Update SDCR_VALID_MASK to include SCCD | Peter Maydell | 2022-09-29 | 1 | -1/+7 |
* | target/arm: Make writes to MDCR_EL3 use PMU start/finish calls | Peter Maydell | 2022-09-29 | 1 | -4/+14 |
* | target/arm: Mark registers which call pmu_op_start() as ARM_CP_IO | Peter Maydell | 2022-09-29 | 1 | -6/+6 |
* | target/arm: Add is_secure parameter to get_phys_addr_pmsav5 | Richard Henderson | 2022-09-22 | 1 | -2/+2 |
* | target/arm: Add secure parameter to get_phys_addr_pmsav7 | Richard Henderson | 2022-09-22 | 1 | -3/+2 |
* | target/arm: Add is_secure parameter to pmsav7_use_background_region | Richard Henderson | 2022-09-22 | 1 | -5/+5 |
* | target/arm: Add secure parameter to get_phys_addr_pmsav8 | Richard Henderson | 2022-09-22 | 1 | -3/+2 |
* | target/arm: Add is_secure parameter to get_phys_addr_v6 | Richard Henderson | 2022-09-22 | 1 | -6/+5 |
* | target/arm: Add is_secure parameter to get_phys_addr_v5 | Richard Henderson | 2022-09-22 | 1 | -7/+7 |
* | target/arm: Add secure parameter to pmsav8_mpu_lookup | Richard Henderson | 2022-09-22 | 3 | -7/+6 |
* | target/arm: Add is_secure parameter to v8m_security_lookup | Richard Henderson | 2022-09-22 | 3 | -8/+12 |
* | target/arm: Remove is_subpage argument to pmsav8_mpu_lookup | Richard Henderson | 2022-09-22 | 3 | -15/+15 |
* | target/arm: Use GetPhysAddrResult in pmsav8_mpu_lookup | Richard Henderson | 2022-09-22 | 3 | -26/+21 |
* | target/arm: Use GetPhysAddrResult in get_phys_addr_pmsav8 | Richard Henderson | 2022-09-22 | 1 | -14/+14 |
* | target/arm: Use GetPhysAddrResult in get_phys_addr_pmsav7 | Richard Henderson | 2022-09-22 | 1 | -19/+17 |
* | target/arm: Use GetPhysAddrResult in get_phys_addr_pmsav5 | Richard Henderson | 2022-09-22 | 1 | -12/+12 |
* | target/arm: Use GetPhysAddrResult in get_phys_addr_v5 | Richard Henderson | 2022-09-22 | 1 | -14/+11 |
* | target/arm: Use GetPhysAddrResult in get_phys_addr_v6 | Richard Henderson | 2022-09-22 | 1 | -16/+14 |
* | target/arm: Use GetPhysAddrResult in get_phys_addr_lpae | Richard Henderson | 2022-09-22 | 1 | -43/+26 |
* | target/arm: Create GetPhysAddrResult | Richard Henderson | 2022-09-22 | 5 | -125/+109 |
* | target/arm: Fix alignment for VLD4.32 | Clément Chigot | 2022-09-22 | 1 | -1/+5 |
* | Merge tag 'pull-semi-20220914' of https://gitlab.com/rth7680/qemu into staging | Stefan Hajnoczi | 2022-09-17 | 2 | -23/+5 |
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| * | target/arm: Honour -semihosting-config userspace=on | Peter Maydell | 2022-09-13 | 2 | -23/+5 |
| * | semihosting: Allow optional use of semihosting from userspace | Peter Maydell | 2022-09-13 | 2 | -4/+4 |
* | | target/arm: Report FEAT_PMUv3p5 for TCG '-cpu max' | Peter Maydell | 2022-09-14 | 2 | -2/+2 |