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| * target/arm: Implement fp16 for Neon VRINTXPeter Maydell2020-09-013-42/+9Star
| | | | | | | | | | | | | | | | | | Convert the Neon VRINTX insn to use gvec, and use this to implement fp16 support for it. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20200828183354.27913-42-peter.maydell@linaro.org
| * target/arm: Implement fp16 for Neon VRINT-with-specified-rounding-modePeter Maydell2020-09-014-79/+30Star
| | | | | | | | | | | | | | | | | | Convert the Neon VRINT-with-specified-rounding-mode insns to gvec, and use this to implement the fp16 versions. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20200828183354.27913-41-peter.maydell@linaro.org
| * target/arm: Implement fp16 for Neon VCVT with rounding modesPeter Maydell2020-09-013-67/+66Star
| | | | | | | | | | | | | | | | | | Convert the Neon VCVT with-specified-rounding-mode instructions to gvec, and use this to implement fp16 support for them. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20200828183354.27913-40-peter.maydell@linaro.org
| * target/arm: Implement fp16 for Neon VCVT fixed-pointPeter Maydell2020-09-014-1/+21
| | | | | | | | | | | | | | | | | | Implement fp16 for the Neon VCVT insns which convert between float and fixed-point. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20200828183354.27913-39-peter.maydell@linaro.org
| * target/arm: Convert Neon VCVT fixed-point to gvecPeter Maydell2020-09-013-17/+43
| | | | | | | | | | | | | | | | | | Convert the Neon VCVT float<->fixed-point insns to a gvec style, in preparation for adding fp16 support. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20200828183354.27913-38-peter.maydell@linaro.org
| * target/arm: Implement fp16 for Neon float-integer VCVTPeter Maydell2020-09-013-11/+42
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Convert the Neon float-integer VCVT insns to gvec, and use this to implement fp16 support for them. Note that unlike the VFP int<->fp16 VCVT insns we converted earlier and which convert to/from a 32-bit integer, these Neon insns convert to/from 16-bit integers. So we can use the existing vfp conversion helpers for the f32<->u32/i32 case but need to provide our own for f16<->u16/i16. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20200828183354.27913-37-peter.maydell@linaro.org
| * target/arm: Implement fp16 for Neon pairwise fp opsPeter Maydell2020-09-013-26/+68
| | | | | | | | | | | | | | | | | | | | | | Convert the Neon pairwise fp ops to use a single gvic-style helper to do the full operation instead of one helper call for each 32-bit part. This allows us to use the same framework to implement the fp16. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20200828183354.27913-36-peter.maydell@linaro.org
| * target/arm: Implement fp16 for Neon VRSQRTSPeter Maydell2020-09-014-36/+34Star
| | | | | | | | | | | | | | | | | | | | | | | | Convert the Neon VRSQRTS insn to using a gvec helper, and use this to implement the fp16 case. As with VRECPS, we adjust the phrasing of the new implementation slightly so that the fp32 version parallels the fp16 one. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20200828183354.27913-35-peter.maydell@linaro.org
| * target/arm: Implement fp16 for Neon VRECPSPeter Maydell2020-09-014-34/+35
| | | | | | | | | | | | | | | | | | | | | | | | | | Convert the Neon VRECPS insn to using a gvec helper, and use this to implement the fp16 case. The phrasing of the new float32_recps_nf() is slightly different from the old recps_f32() so that it parallels the f16 version; for f16 we can't assume that flush-to-zero is always enabled. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20200828183354.27913-34-peter.maydell@linaro.org
| * target/arm: Implement fp16 for Neon fp compare-vs-0Peter Maydell2020-09-013-28/+45
| | | | | | | | | | | | | | | | | | | | Convert the neon floating-point vector compare-vs-0 insns VCEQ0, VCGT0, VCLE0, VCGE0 and VCLT0 to use a gvec helper, and use this to implement the fp16 case. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20200828183354.27913-33-peter.maydell@linaro.org
| * target/arm: Implement fp16 for Neon VFMA, VMFSPeter Maydell2020-09-013-91/+40Star
| | | | | | | | | | | | | | | | | | | | | | | | Convert the neon floating-point vector operations VFMA and VFMS to use a gvec helper, and use this to implement the fp16 case. This is the last use of do_3same_fp() so we can now delete that function. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20200828183354.27913-32-peter.maydell@linaro.org
| * target/arm: Implement fp16 for Neon VMLA, VMLS operationsPeter Maydell2020-09-013-31/+50
| | | | | | | | | | | | | | | | | | Convert the Neon floating-point VMLA and VMLS insns over to using a gvec helper, and use this to implement the fp16 case. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20200828183354.27913-31-peter.maydell@linaro.org
| * target/arm: Implement fp16 for Neon VMAXNM, VMINNMPeter Maydell2020-09-013-8/+27
| | | | | | | | | | | | | | | | | | Convert the Neon floating point VMAXNM and VMINNM insns to using a gvec helper and use this to implement the fp16 case. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20200828183354.27913-30-peter.maydell@linaro.org
| * target/arm: Implement fp16 for Neon VMAX, VMINPeter Maydell2020-09-013-3/+14
| | | | | | | | | | | | | | | | | | Convert the Neon float-point VMAX and VMIN insns over to using a gvec helper, and use this to implement the fp16 case. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20200828183354.27913-29-peter.maydell@linaro.org
| * target/arm: Implement fp16 for VACGE, VACGTPeter Maydell2020-09-013-2/+34
| | | | | | | | | | | | | | | | | | | | Convert the neon floating-point vector absolute comparison ops VACGE and VACGT over to using a gvec hepler and use this to implement the fp16 case. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20200828183354.27913-28-peter.maydell@linaro.org
| * target/arm: Implement fp16 for VCEQ, VCGE, VCGT comparisonsPeter Maydell2020-09-013-3/+56
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Convert the Neon floating-point vector comparison ops VCEQ, VCGE and VCGT over to using a gvec helper and use this to implement the fp16 case. (We put the float16_ceq() etc functions above the DO_2OP() macro definition because later when we convert the compare-against-zero instructions we'll want their definitions to be visible at that point in the source file.) Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20200828183354.27913-27-peter.maydell@linaro.org
| * target/arm: Implement fp16 for Neon VABS, VNEG of floatsPeter Maydell2020-09-011-6/+28
| | | | | | | | | | | | | | | | | | Rewrite Neon VABS/VNEG of floats to use gvec logical AND and XOR, so that we can implement the fp16 version of the insns. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20200828183354.27913-26-peter.maydell@linaro.org
| * target/arm: Implement fp16 for Neon VRECPE, VRSQRTE using gvecPeter Maydell2020-09-011-2/+29
| | | | | | | | | | | | | | | | | | | | We already have gvec helpers for floating point VRECPE and VRQSRTE, so convert the Neon decoder to use them and add the fp16 support. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20200828183354.27913-25-peter.maydell@linaro.org
| * target/arm: Implement FP16 for Neon VADD, VSUB, VABD, VMULPeter Maydell2020-09-013-17/+26
| | | | | | | | | | | | | | | | | | | | | | | | Implement FP16 support for the Neon insns which use the DO_3S_FP_GVEC macro: VADD, VSUB, VABD, VMUL. For VABD this requires us to implement a new gvec_fabd_h helper using the machinery we have already for the other helpers. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20200828183354.27913-24-peter.maydell@linaro.org
| * target/arm: Implement VFP fp16 VMOV between gp and halfprec registersPeter Maydell2020-09-012-0/+35
| | | | | | | | | | | | | | | | | | | | | | | | | | Implement the VFP fp16 variant of VMOV that transfers a 16-bit value between a general purpose register and a VFP register. Note that Rt == 15 is UNPREDICTABLE; since this insn is v8 and later only we have no need to replicate the old "updates CPSR.NZCV" behaviour that the singleprec version of this insn does. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20200828183354.27913-22-peter.maydell@linaro.org
| * target/arm: Implement new VFP fp16 insn VMOVXPeter Maydell2020-09-012-0/+28
| | | | | | | | | | | | | | | | | | | | | | The fp16 extension includes a new instruction VMOVX, which copies the upper 16 bits of a 32-bit source VFP register into the lower 16 bits of the destination and zeroes the high half of the destination. Implement it. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20200828183354.27913-21-peter.maydell@linaro.org
| * target/arm: Implement new VFP fp16 insn VINSPeter Maydell2020-09-012-0/+31
| | | | | | | | | | | | | | | | | | | | The fp16 extension includes a new instruction VINS, which copies the lower 16 bits of a 32-bit source VFP register into the upper 16 bits of the destination. Implement it. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20200828183354.27913-20-peter.maydell@linaro.org
| * target/arm: Implement VFP fp16 VRINT*Peter Maydell2020-09-015-8/+122
| | | | | | | | | | | | | | | | Implement the fp16 version of the VFP VRINT* insns. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20200828183354.27913-19-peter.maydell@linaro.org
| * target/arm: Implement VFP fp16 VSELPeter Maydell2020-09-012-6/+16
| | | | | | | | | | | | | | | | Implement the fp16 versions of the VFP VSEL instruction. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20200828183354.27913-18-peter.maydell@linaro.org
| * target/arm: Implement VFP vp16 VCVT-with-specified-rounding-modePeter Maydell2020-09-012-10/+28
| | | | | | | | | | | | | | | | | | | | Implement the fp16 versions of the VFP VCVT instruction forms which convert between floating point and integer with a specified rounding mode. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20200828183354.27913-17-peter.maydell@linaro.org
| * target/arm: Implement VFP fp16 VCVT between float and fixed-pointPeter Maydell2020-09-012-0/+61
| | | | | | | | | | | | | | | | | | Implement the fp16 versions of the VFP VCVT instruction forms which convert between floating point and fixed-point. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20200828183354.27913-16-peter.maydell@linaro.org
| * target/arm: Use macros instead of open-coding fp16 conversion helpersPeter Maydell2020-09-012-80/+12Star
| | | | | | | | | | | | | | | | | | | | | | | | | | Now the VFP_CONV_FIX macros can handle fp16's distinction between the width of the operation and the width of the type used to pass operands, use the macros rather than the open-coded functions. This creates an extra six helper functions, all of which we are going to need for the AArch32 VFP fp16 instructions. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20200828183354.27913-15-peter.maydell@linaro.org
| * target/arm: Make VFP_CONV_FIX macros take separate float type and float sizePeter Maydell2020-09-011-23/+23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently the VFP_CONV_FIX macros take a single fsz argument for the size of the float type, which is used both to select the name of the functions to call (eg float32_is_any_nan()) and also for the type to use for the float inputs and outputs (eg float32). Separate these into fsz and ftype arguments, so that we can use them for fp16, which uses 'float16' in the function names but is still passing inputs and outputs in a 32-bit sized type. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20200828183354.27913-14-peter.maydell@linaro.org
| * target/arm: Implement VFP fp16 VCVT between float and integerPeter Maydell2020-09-012-0/+69
| | | | | | | | | | | | | | | | | | Implement the fp16 versions of the VFP VCVT instruction forms which convert between floating point and integer. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20200828183354.27913-13-peter.maydell@linaro.org
| * target/arm: Implement VFP fp16 VLDR and VSTRPeter Maydell2020-09-012-2/+36
| | | | | | | | | | | | | | | | Implement the fp16 versions of the VFP VLDR/VSTR (immediate). Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20200828183354.27913-12-peter.maydell@linaro.org
| * target/arm: Implement VFP fp16 VCMPPeter Maydell2020-09-014-7/+51
| | | | | | | | | | | | | | | | Implement fp16 version of VCMP. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20200828183354.27913-11-peter.maydell@linaro.org
| * target/arm: Implement VFP fp16 for VMOV immediatePeter Maydell2020-09-012-0/+24
| | | | | | | | | | | | | | | | Implement VFP fp16 support for the VMOV immediate insn. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20200828183354.27913-10-peter.maydell@linaro.org
| * target/arm: Implement VFP fp16 for VABS, VNEG, VSQRTPeter Maydell2020-09-014-0/+55
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Implement VFP fp16 for VABS, VNEG and VSQRT. This is all the fp16 insns that use the DO_VFP_2OP macro, because there is no fp16 version of VMOV_reg. Notes: * the gen_helper_vfp_negh already exists as we needed to create it for the fp16 multiply-add insns * as usual we need to use the f16 version of the fp_status; this is only relevant for VSQRT Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20200828183354.27913-9-peter.maydell@linaro.org
| * target/arm: Macroify uses of do_vfp_2op_sp() and do_vfp_2op_dp()Peter Maydell2020-09-011-35/+14Star
| | | | | | | | | | | | | | | | | | Macroify the uses of do_vfp_2op_sp() and do_vfp_2op_dp(); this will make it easier to add the halfprec support. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20200828183354.27913-8-peter.maydell@linaro.org
| * target/arm: Implement VFP fp16 for fused-multiply-addPeter Maydell2020-09-014-0/+77
| | | | | | | | | | | | | | | | | | Implement VFP fp16 support for fused multiply-add insns VFNMA, VFNMS, VFMA, VFMS. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20200828183354.27913-7-peter.maydell@linaro.org
| * target/arm: Macroify trans functions for VFMA, VFMS, VFNMA, VFNMSPeter Maydell2020-09-011-37/+13Star
| | | | | | | | | | | | | | | | | | | | | | Macroify creation of the trans functions for single and double precision VFMA, VFMS, VFNMA, VFNMS. The repetition was OK for two sizes, but we're about to add halfprec and it will get a bit more than seems reasonable. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20200828183354.27913-6-peter.maydell@linaro.org
| * target/arm: Implement VFP fp16 VMLA, VMLS, VNMLS, VNMLA, VNMULPeter Maydell2020-09-014-0/+95
| | | | | | | | | | | | | | | | | | | | Implement fp16 versions of the VFP VMLA, VMLS, VNMLS, VNMLA, VNMUL instructions. (These are all the remaining ones which we implement via do_vfp_3op_[hsd]p().) Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20200828183354.27913-5-peter.maydell@linaro.org
| * target/arm: Implement VFP fp16 for VFP_BINOP operationsPeter Maydell2020-09-015-0/+106
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Implmeent VFP fp16 support for simple binary-operator VFP insns VADD, VSUB, VMUL, VDIV, VMINNM and VMAXNM: * make the VFP_BINOP() macro generate float16 helpers as well as float32 and float64 * implement a do_vfp_3op_hp() function similar to the existing do_vfp_3op_sp() * add decode for the half-precision insn patterns Note that the VFP_BINOP macro use creates a couple of unused helper functions vfp_maxh and vfp_minh, but they're small so it's not worth splitting the BINOP operations into "needs halfprec" and "no halfprec" groups. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20200828183354.27913-4-peter.maydell@linaro.org
| * target/arm: Use correct ID register check for aa32_fp16_arithPeter Maydell2020-09-011-6/+1Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The aa32_fp16_arith feature check function currently looks at the AArch64 ID_AA64PFR0 register. This is (as the comment notes) not correct. The bogus check was put in mostly to allow testing of the fp16 variants of the VCMLA instructions and it was something of a mistake that we allowed them to exist in master. Switch the feature check function to testing VMFR1.FPHP, which is what it ought to be. This will remove emulation of the VCMLA and VCADD insns from AArch32 code running on an AArch64 '-cpu max' using system emulation. (They were never enabled for aarch32 linux-user and system-emulation.) Since we weren't advertising their existence via the AArch32 ID register, well-behaved guests wouldn't have been using them anyway. Once we have implemented all the AArch32 support for the FP16 extension we will advertise it in the MVFR1 ID register field, which will reenable these insns along with all the others. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20200828183354.27913-3-peter.maydell@linaro.org
| * target/arm: Remove local definitions of float constantsPeter Maydell2020-09-013-19/+0Star
| | | | | | | | | | | | | | | | | | | | In several places the target/arm code defines local float constants for 2, 3 and 1.5, which are also provided by include/fpu/softfloat.h. Remove the unnecessary local duplicate versions. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20200828183354.27913-2-peter.maydell@linaro.org
* | target/arm/translate-a64:Remove redundant statement in ↵Chen Qun2020-09-011-3/+0Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | disas_simd_two_reg_misc_fp16() Clang static code analyzer show warning: target/arm/translate-a64.c:13007:5: warning: Value stored to 'rd' is never read rd = extract32(insn, 0, 5); ^ ~~~~~~~~~~~~~~~~~~~~~ target/arm/translate-a64.c:13008:5: warning: Value stored to 'rn' is never read rn = extract32(insn, 5, 5); ^ ~~~~~~~~~~~~~~~~~~~~~ Reported-by: Euler Robot <euler.robot@huawei.com> Signed-off-by: Chen Qun <kuhn.chenqun@huawei.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-Id: <20200827110311.164316-5-kuhn.chenqun@huawei.com> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
* | target/arm/translate-a64:Remove dead assignment in handle_scalar_simd_shli()Chen Qun2020-09-011-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Clang static code analyzer show warning: target/arm/translate-a64.c:8635:14: warning: Value stored to 'tcg_rn' during its initialization is never read TCGv_i64 tcg_rn = new_tmp_a64(s); ^~~~~~ ~~~~~~~~~~~~~~ target/arm/translate-a64.c:8636:14: warning: Value stored to 'tcg_rd' during its initialization is never read TCGv_i64 tcg_rd = new_tmp_a64(s); ^~~~~~ ~~~~~~~~~~~~~~ Reported-by: Euler Robot <euler.robot@huawei.com> Signed-off-by: Chen Qun <kuhn.chenqun@huawei.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-Id: <20200827110311.164316-4-kuhn.chenqun@huawei.com> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
* | target/arm/kvm: Remove superfluous breakLiao Pingfang2020-09-011-1/+0Star
|/ | | | | | | | | | | Remove superfluous break. Signed-off-by: Liao Pingfang <liao.pingfang@zte.com.cn> Signed-off-by: Yi Wang <wang.yi59@zte.com.cn> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Message-Id: <1594630986-36148-1-git-send-email-wang.yi59@zte.com.cn> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
* target/arm: Convert sq{, r}dmulh to gvec for aa64 advsimdRichard Henderson2020-08-283-10/+81
| | | | | | | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20200815013145.539409-21-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* target/arm: Convert integer multiply-add (indexed) to gvec for aa64 advsimdRichard Henderson2020-08-283-0/+73
| | | | | | | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20200815013145.539409-20-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* target/arm: Convert integer multiply (indexed) to gvec for aa64 advsimdRichard Henderson2020-08-283-4/+45
| | | | | | | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20200815013145.539409-19-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* target/arm: Generalize inl_qrdmlah_* helper functionsRichard Henderson2020-08-281-51/+29Star
| | | | | | | | | | | Unify add/sub helpers and add a parameter for rounding. This will allow saturating non-rounding to reuse this code. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> [PMM: fixed accidental use of '=' rather than '+=' in do_sqrdmlah_s] Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20200815013145.539409-15-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* target/arm: Tidy SVE tszimm shift formatsRichard Henderson2020-08-281-19/+16Star
| | | | | | | | | | Rather than require the user to fill in the immediate (shl or shr), create full formats that include the immediate. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20200815013145.539409-14-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* target/arm: Split out gen_gvec_ool_zzRichard Henderson2020-08-281-8/+12
| | | | | | | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20200815013145.539409-13-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* target/arm: Split out gen_gvec_ool_zzzRichard Henderson2020-08-281-35/+18Star
| | | | | | | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20200815013145.539409-12-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
generated by cgit v1.2.3-55-g7522 (git 2.39.0) at 2025-01-16 03:48:48 +0100