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* target/arm: Check PMCNTEN for whether PMCCNTR is enabledAaron Lindsay2018-04-261-1/+1
* target/arm: Use v7m_stack_read() for reading the frame signaturePeter Maydell2018-04-261-4/+5
* target/arm: Remove stale TODO commentPeter Maydell2018-04-261-7/+1Star
* icount: fix cpu_restore_state_from_tb for non-tb-exit casesPavel Dovgalyuk2018-04-111-3/+3
* tcg: Introduce tcg_set_insn_start_paramRichard Henderson2018-04-101-1/+1
* target/arm: Report unsupported MPU region sizes more clearlyPeter Maydell2018-04-101-3/+3
* target-arm: Check undefined opcodes for SWP in A32 decoderOnur Sahin2018-04-101-2/+7
* target/arm: Always set FAR to a known unknown value for debug exceptionsPeter Maydell2018-03-231-1/+10
* target/arm: Set FSR for BKPT, BRK when raising exceptionPeter Maydell2018-03-232-1/+2
* target/arm: Factor out code to calculate FSR for debug exceptionsPeter Maydell2018-03-232-10/+27
* target/arm: Honour MDCR_EL2.TDE when routing exceptions due to BKPT/BRKPeter Maydell2018-03-234-7/+36
* arm/translate-a64: treat DISAS_UPDATE as variant of DISAS_EXITVictor Kamensky2018-03-231-3/+3
* cpu: get rid of unused cpu_init() definesIgor Mammedov2018-03-191-2/+0Star
* cpu: add CPU_RESOLVING_TYPE macroIgor Mammedov2018-03-191-0/+1
* target/arm: Make 'any' CPU just an alias for 'max'Peter Maydell2018-03-092-54/+55
* target/arm: Add "-cpu max" supportPeter Maydell2018-03-093-0/+47
* target/arm: Move definition of 'host' cpu type into cpu.cPeter Maydell2018-03-092-19/+24
* target/arm: Query host CPU features on-demand at instance initPeter Maydell2018-03-096-36/+69
* linux-user: Implement aarch64 PR_SVE_SET/GET_VLRichard Henderson2018-03-092-0/+42
* target/arm: Add a core count propertyAlistair Francis2018-03-093-2/+15
* qapi: Empty out qapi-schema.jsonMarkus Armbruster2018-03-021-1/+2
* target/arm: Enable ARM_FEATURE_V8_FCMARichard Henderson2018-03-022-0/+2
* target/arm: Decode t32 simd 3reg and 2reg_scalar extensionRichard Henderson2018-03-021-1/+13
* target/arm: Decode aa32 armv8.3 2-reg-indexRichard Henderson2018-03-021-0/+61
* target/arm: Decode aa32 armv8.3 3-sameRichard Henderson2018-03-021-0/+68
* target/arm: Decode aa64 armv8.3 fcmlaRichard Henderson2018-03-023-8/+246
* target/arm: Decode aa64 armv8.3 fcaddRichard Henderson2018-03-023-1/+151
* target/arm: Add ARM_FEATURE_V8_FCMARichard Henderson2018-03-021-0/+1
* target/arm: Enable ARM_FEATURE_V8_RDMRichard Henderson2018-03-022-0/+2
* target/arm: Decode aa32 armv8.1 two reg and a scalarRichard Henderson2018-03-021-2/+40
* target/arm: Decode aa32 armv8.1 three sameRichard Henderson2018-03-021-19/+67
* target/arm: Decode aa64 armv8.1 scalar/vector x indexed elementRichard Henderson2018-03-021-0/+29
* target/arm: Decode aa64 armv8.1 three same extraRichard Henderson2018-03-023-0/+166
* target/arm: Decode aa64 armv8.1 scalar three same extraRichard Henderson2018-03-024-1/+198
* target/arm: Refactor disas_simd_indexed size checksRichard Henderson2018-03-021-31/+30Star
* target/arm: Refactor disas_simd_indexed decodeRichard Henderson2018-03-021-66/+59Star
* target/arm: Add ARM_FEATURE_V8_RDMRichard Henderson2018-03-021-0/+1
* target/arm: Add Cortex-M33Peter Maydell2018-03-021-0/+31
* target/arm: Define init-svtor property for the reset secure VTOR valuePeter Maydell2018-03-022-4/+17
* target/arm: Define an IDAU interfacePeter Maydell2018-03-024-3/+104
* target/arm: Enable ARM_V8_FP16 feature bit for the AArch64 "any" CPUPeter Maydell2018-03-011-0/+1
* arm/translate-a64: add all single op FP16 to handle_fp_1src_halfAlex Bennée2018-03-011-0/+71
* arm/translate-a64: implement simd_scalar_three_reg_same_fp16Alex Bennée2018-03-011-0/+99
* arm/translate-a64: add all FP16 ops in simd_scalar_pairwiseAlex Bennée2018-03-011-26/+54
* arm/translate-a64: add FP16 FMOV to simd_mod_immAlex Bennée2018-03-011-10/+25
* arm/translate-a64: add FP16 FRSQRTE to simd_two_reg_misc_fp16Alex Bennée2018-03-011-0/+7
* arm/helper.c: re-factor rsqrte and add rsqrte_f16Alex Bennée2018-03-012-118/+104Star
* arm/translate-a64: add FP16 FSQRT to simd_two_reg_misc_fp16Alex Bennée2018-03-013-0/+19
* arm/translate-a64: add FP16 FRCPX to simd_two_reg_misc_fp16Alex Bennée2018-03-013-0/+34
* arm/translate-a64: add FP16 FRECPEAlex Bennée2018-03-011-0/+8
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