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* arm/helper.c: re-factor recpe and add recepe_f16Alex Bennée2018-03-012-97/+128
* arm/translate-a64: add FP16 FNEG/FABS to simd_two_reg_misc_fp16Alex Bennée2018-03-011-1/+15
* arm/translate-a64: add FP16 SCVTF/UCVFT to simd_two_reg_misc_fp16Alex Bennée2018-03-013-24/+104
* arm/translate-a64: add FP16 FCMxx (zero) to simd_two_reg_misc_fp16Alex Bennée2018-03-011-23/+57
* arm/translate-a64: add FCVTxx to simd_two_reg_misc_fp16Alex Bennée2018-03-013-1/+118
* arm/translate-a64: add FP16 FPRINTx to simd_two_reg_misc_fp16Alex Bennée2018-03-013-5/+142
* arm/translate-a64: initial decode for simd_two_reg_misc_fp16Alex Bennée2018-03-011-0/+40
* arm/translate-a64: add FP16 x2 ops for simd_indexedAlex Bennée2018-03-013-6/+76
* arm/translate-a64: add FP16 FMULX/MLS/FMLA to simd_indexedAlex Bennée2018-03-011-16/+66
* arm/translate-a64: add FP16 pairwise ops simd_three_reg_same_fp16Alex Bennée2018-03-011-75/+133
* arm/translate-a64: add FP16 FR[ECP/SQRT]S to simd_three_reg_same_fp16Alex Bennée2018-03-013-0/+42
* arm/translate-a64: add FP16 FMULA/X/S to simd_three_reg_same_fp16Alex Bennée2018-03-013-0/+41
* arm/translate-a64: add FP16 F[A]C[EQ/GE/GT] to simd_three_reg_same_fp16Alex Bennée2018-03-013-0/+69
* arm/translate-a64: add FP16 FADD/FABD/FSUB/FMUL/FDIV to simd_three_reg_same_fp16Alex Bennée2018-03-013-0/+36
* arm/translate-a64: initial decode for simd_three_reg_same_fp16Alex Bennée2018-03-011-0/+73
* arm/translate-a64: handle_3same_64 comment fixAlex Bennée2018-03-011-2/+1Star
* arm/translate-a64: implement half-precision F(MIN|MAX)(V|NMV)Alex Bennée2018-03-013-54/+110
* target/arm/helper: pass explicit fpst to set_rmodeAlex Bennée2018-03-014-22/+22
* target/arm/cpu.h: add additional float_status flagsAlex Bennée2018-03-013-36/+75
* target/arm/cpu.h: update comment for half-precision valuesAlex Bennée2018-03-011-0/+1
* target/arm/cpu64: introduce ARM_V8_FP16 feature bitAlex Bennée2018-03-011-0/+1
* target/arm: Fix register definitions for VMIDR and VMPIDRPeter Maydell2018-02-221-4/+4
* target/*/cpu.h: remove softfloat.hAlex Bennée2018-02-215-2/+4
* target/arm: Implement v8M MSPLIM and PSPLIM registersPeter Maydell2018-02-153-0/+69
* target/arm: Migrate v7m.other_spPeter Maydell2018-02-151-0/+11
* target/arm: Add AIRCR to vmstate structPeter Maydell2018-02-151-0/+4
* target/arm: Implement writing to CONTROL_NS for v8MPeter Maydell2018-02-151-0/+10
* hw/intc/armv7m_nvic: Implement SCRPeter Maydell2018-02-152-0/+19
* hw/intc/armv7m_nvic: Implement cache ID registersPeter Maydell2018-02-152-0/+62
* hw/intc/armv7m_nvic: Don't hardcode M profile ID registers in NVICPeter Maydell2018-02-151-0/+28
* target/arm: Handle SVE registers when using clear_vec_highRichard Henderson2018-02-151-100/+62Star
* target/arm: Enforce access to ZCR_EL at translationRichard Henderson2018-02-154-19/+28
* target/arm: Suppress TB end for FPCR/FPSRRichard Henderson2018-02-151-2/+2
* target/arm: Enforce FP access to FPCR/FPSRRichard Henderson2018-02-153-19/+25
* target/arm: Remove ARM_CP_64BIT from ZCR_EL registersRichard Henderson2018-02-151-4/+4
* target/arm/translate.c: Fix missing 'break' for TT insnsPeter Maydell2018-02-091-0/+1
* target/arm/kvm: gic: Prevent creating userspace GICv3 with KVMChristoffer Dall2018-02-091-0/+4
* target/arm: Add SVE state to TB->FLAGSRichard Henderson2018-02-094-1/+36
* target/arm: Add ZCR_ELxRichard Henderson2018-02-092-0/+136
* target/arm: Add SVE to migration stateRichard Henderson2018-02-091-0/+53
* target/arm: Add predicate registers for SVERichard Henderson2018-02-091-0/+12
* target/arm: Expand vector registers for SVERichard Henderson2018-02-094-28/+81
* target/arm: enable user-mode SHA-3, SM3, SM4 and SHA-512 instruction supportArd Biesheuvel2018-02-091-0/+4
* target/arm: implement SM4 instructionsArd Biesheuvel2018-02-094-0/+103
* target/arm: implement SM3 instructionsArd Biesheuvel2018-02-094-3/+186
* target/arm: implement SHA-3 instructionsArd Biesheuvel2018-02-092-4/+145
* target/arm: implement SHA-512 instructionsArd Biesheuvel2018-02-094-1/+205
* target/arm: Handle exceptions during exception stack popPeter Maydell2018-02-091-21/+94
* target/arm: Make exception vector loads honour the SAUPeter Maydell2018-02-091-16/+55
* target/arm: Make v7m_push_callee_stack() honour MPUPeter Maydell2018-02-091-15/+49
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