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* Merge remote-tracking branch 'remotes/rth-gitlab/tags/pull-tcg-20210710' into...Peter Maydell2021-07-123-36/+8Star
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| * target/arm: Use translator_use_goto_tb for aarch32Richard Henderson2021-07-091-11/+1Star
| * target/arm: Use translator_use_goto_tb for aarch64Richard Henderson2021-07-091-20/+5Star
| * target/arm: Use DISAS_TOO_MANY for ISB and SBRichard Henderson2021-07-091-2/+2
| * tcg: Avoid including 'trace-tcg.h' in target translate.cPhilippe Mathieu-Daudé2021-07-093-3/+0Star
* | Merge remote-tracking branch 'remotes/bonzini-gitlab/tags/for-upstream' into ...Peter Maydell2021-07-111-0/+6
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| * | meson: Introduce target-specific KconfigPhilippe Mathieu-Daudé2021-07-091-0/+6
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* / target/arm: Correct the encoding of MDCCSR_EL0 and DBGDSCRinthnick@vmware.com2021-07-091-3/+13
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* target/arm: Implement MVE shifts by registerPeter Maydell2021-07-025-4/+57
* target/arm: Implement MVE shifts by immediatePeter Maydell2021-07-025-10/+105
* target/arm: Implement MVE long shifts by registerPeter Maydell2021-07-025-3/+182
* target/arm: Implement MVE long shifts by immediatePeter Maydell2021-07-025-0/+132
* target/arm: Implement MVE VADDLVPeter Maydell2021-07-024-1/+90
* target/arm: Implement MVE VSHLCPeter Maydell2021-07-024-0/+72
* target/arm: Implement MVE saturating narrowing shiftsPeter Maydell2021-07-024-0/+174
* target/arm: Implement MVE VSHRN, VRSHRNPeter Maydell2021-07-024-0/+76
* target/arm: Implement MVE VSRI, VSLIPeter Maydell2021-07-024-0/+62
* target/arm: Implement MVE VSHLLPeter Maydell2021-07-024-4/+105
* target/arm: Implement MVE vector shift right by immediate insnsPeter Maydell2021-07-026-18/+72
* target/arm: Implement MVE vector shift left by immediate insnsPeter Maydell2021-07-024-0/+147
* target/arm: Implement MVE logical immediate insnsPeter Maydell2021-07-024-0/+95
* target/arm: Use dup_const() instead of bitfield_replicate()Peter Maydell2021-07-021-1/+1
* target/arm: Use asimd_imm_const for A64 decodePeter Maydell2021-07-023-82/+24Star
* target/arm: Make asimd_imm_const() publicPeter Maydell2021-07-023-63/+73
* target/arm: Fix bugs in MVE VRMLALDAVH, VRMLSLDAVHPeter Maydell2021-07-021-17/+21
* target/arm: Fix MVE widening/narrowing VLDR/VSTR offset calculationPeter Maydell2021-07-021-8/+9
* target/arm: Check NaN mode before silencing NaNJoe Komlodi2021-07-022-9/+27
* target/arm: Improve REVSHRichard Henderson2021-06-291-3/+1Star
* target/arm: Improve vector REVRichard Henderson2021-06-291-4/+2Star
* target/arm: Improve REV32Richard Henderson2021-06-291-13/+4Star
* tcg: Add flags argument to tcg_gen_bswap16_*, tcg_gen_bswap32_i64Richard Henderson2021-06-292-6/+8
* target/arm: Implement MTE3Peter Collingbourne2021-06-242-32/+52
* target/arm: Make VMOV scalar <-> gpreg beatwise for MVEPeter Maydell2021-06-243-8/+75
* target/arm: Implement MVE VADDVPeter Maydell2021-06-244-0/+76
* target/arm: Implement MVE VHCADDPeter Maydell2021-06-244-3/+19
* target/arm: Implement MVE VCADDPeter Maydell2021-06-244-2/+51
* target/arm: Implement MVE VADC, VSBCPeter Maydell2021-06-244-0/+99
* target/arm: Implement MVE VRHADDPeter Maydell2021-06-244-0/+19
* target/arm: Implement MVE VQDMULL (vector)Peter Maydell2021-06-244-0/+70
* target/arm: Implement MVE VQDMLSDH and VQRDMLSDHPeter Maydell2021-06-244-0/+69
* target/arm: Implement MVE VQDMLADH and VQRDMLADHPeter Maydell2021-06-244-0/+114
* target/arm: Implement MVE VRSHLPeter Maydell2021-06-244-0/+17
* target/arm: Implement MVE VSHL insnPeter Maydell2021-06-244-0/+19
* target/arm: Implement MVE VQRSHLPeter Maydell2021-06-244-0/+19
* target/arm: Implement MVE VQSHL (vector)Peter Maydell2021-06-244-0/+56
* target/arm: Implement MVE VQADD, VQSUB (vector)Peter Maydell2021-06-244-0/+39
* target/arm: Implement MVE VQDMULH, VQRDMULH (vector)Peter Maydell2021-06-244-0/+40
* target/arm: Implement MVE VQDMULL scalarPeter Maydell2021-06-244-4/+119
* target/arm: Implement MVE VQDMULH and VQRDMULH (scalar)Peter Maydell2021-06-244-0/+38
* target/arm: Implement MVE VQADD and VQSUBPeter Maydell2021-06-244-0/+87
generated by cgit v1.2.3-55-g7522 (git 2.39.0) at 2024-12-12 00:37:22 +0100