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* Hexagon HVX (target/hexagon) import instruction encodingsTaylor Simpson2021-11-031-0/+4
| | | | | Acked-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
* Hexagon HVX (target/hexagon) instruction decodingTaylor Simpson2021-11-031-2/+22
| | | | | | | Add new file to target/hexagon/meson.build Acked-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
* Merge remote-tracking branch ↵Peter Maydell2021-05-051-1/+0Star
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 'remotes/vivier2/tags/trivial-branch-for-6.1-pull-request' into staging Trivial patches pull request 20210503 # gpg: Signature made Mon 03 May 2021 09:34:56 BST # gpg: using RSA key CD2F75DDC8E3A4DC2E4F5173F30C38BD3F2FBE3C # gpg: issuer "laurent@vivier.eu" # gpg: Good signature from "Laurent Vivier <lvivier@redhat.com>" [full] # gpg: aka "Laurent Vivier <laurent@vivier.eu>" [full] # gpg: aka "Laurent Vivier (Red Hat) <lvivier@redhat.com>" [full] # Primary key fingerprint: CD2F 75DD C8E3 A4DC 2E4F 5173 F30C 38BD 3F2F BE3C * remotes/vivier2/tags/trivial-branch-for-6.1-pull-request: (23 commits) hw/rx/rx-gdbsim: Do not accept invalid memory size docs: More precisely describe memory-backend-*::id's user scripts: fix generation update-binfmts templates docs/system: Document the removal of "compat" property for POWER CPUs mc146818rtc: put it into the 'misc' category Do not include exec/address-spaces.h if it's not really necessary Do not include cpu.h if it's not really necessary Do not include hw/boards.h if it's not really necessary Do not include sysemu/sysemu.h if it's not really necessary hw: Do not include qemu/log.h if it is not necessary hw: Do not include hw/irq.h if it is not necessary hw: Do not include hw/sysbus.h if it is not necessary hw: Remove superfluous includes of hw/hw.h ui: Fix memory leak in qemu_xkeymap_mapping_table() hw/usb: Constify VMStateDescription hw/display/qxl: Constify VMStateDescription hw/arm: Constify VMStateDescription vmstate: Constify some VMStateDescriptions Fix typo in CFI build documentation hw/pcmcia: Do not register PCMCIA type if not required ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * hw: Do not include qemu/log.h if it is not necessaryThomas Huth2021-05-021-1/+0Star
| | | | | | | | | | | | | | | | | | | | Many files include qemu/log.h without needing it. Remove the superfluous include statements. Signed-off-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20210328054833.2351597-1-thuth@redhat.com> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
* | Hexagon (target/hexagon) change variables from int to bool when appropriateTaylor Simpson2021-05-011-40/+40
| | | | | | | | | | | | | | | | | | Suggested-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <1617930474-31979-8-git-send-email-tsimpson@quicinc.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* | Hexagon (target/hexagon) remove unnecessary inline directivesTaylor Simpson2021-05-011-3/+3
| | | | | | | | | | | | | | | | Suggested-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <1617930474-31979-4-git-send-email-tsimpson@quicinc.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* | target/hexagon: Change DECODE_MAPPED_REG operand name to OPNUMTaylor Simpson2021-05-011-2/+2
|/ | | | | | | Reported-by: Richard Henderson <<richard.henderson@linaro.org> Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> Message-Id: <1615784049-26215-1-git-send-email-tsimpson@quicinc.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* Hexagon (target/hexagon) instruction/packet decodeTaylor Simpson2021-02-181-0/+957
Take the words from instruction memory and build a packet_t for TCG code generation The following operations are performed Convert the .new encoded offset to the register number of the producer Reorder the packet so .new producer is before consumer Apply constant extenders Separate subinsn's into two instructions Break compare-jumps into two instructions Create instructions for :endloop Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <1612763186-18161-14-git-send-email-tsimpson@quicinc.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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