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* Include qemu-common.h exactly where neededMarkus Armbruster2019-06-121-1/+0Star
| | | | | | | | | | | | | | | | No header includes qemu-common.h after this commit, as prescribed by qemu-common.h's file comment. Signed-off-by: Markus Armbruster <armbru@redhat.com> Message-Id: <20190523143508.25387-5-armbru@redhat.com> [Rebased with conflicts resolved automatically, except for include/hw/arm/xlnx-zynqmp.h hw/arm/nrf51_soc.c hw/arm/msf2-soc.c block/qcow2-refcount.c block/qcow2-cluster.c block/qcow2-cache.c target/arm/cpu.h target/lm32/cpu.h target/m68k/cpu.h target/mips/cpu.h target/moxie/cpu.h target/nios2/cpu.h target/openrisc/cpu.h target/riscv/cpu.h target/tilegx/cpu.h target/tricore/cpu.h target/unicore32/cpu.h target/xtensa/cpu.h; bsd-user/main.c and net/tap-bsd.c fixed up]
* target/hppa: add TLB protection id checkSven Schnelle2019-03-121-8/+12
| | | | | | | Signed-off-by: Sven Schnelle <svens@stackframe.org> Message-Id: <20190311191602.25796-10-svens@stackframe.org> [rth: Add required tlb flushing when prot id registers change.] Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* target/hppa: fix setting registers via gdbSven Schnelle2019-02-061-1/+1
| | | | | | | | | | | While doing 'set $pcoqh=0xf0000000' i triggered the assertion below. The argument order for deposit64() is wrong, and val needs to be moved to the end. Signed-off-by: Sven Schnelle <svens@stackframe.org> Message-Id: <20190128165333.3814-1-svens@stackframe.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* target/hppa: Add system registers to gdbstubRichard Henderson2018-01-311-0/+156
| | | | Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* target/hppa: Add control registersRichard Henderson2018-01-301-6/+6
| | | | Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* target/hppa: Split address size from register sizeRichard Henderson2018-01-301-4/+15
| | | | | | | | | For system mode, we will need 64-bit virtual addresses even when we have 32-bit register sizes. Since the rest of QEMU equates TARGET_LONG_BITS with the address size, redefine everything related to register size in terms of a new TARGET_REGISTER_BITS. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* target/hppa: Fix gdb_write_registerRichard Henderson2017-02-071-0/+1
| | | | | | | Add a missing break, detected by Coverity. Reported-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
* target-hppa: Add framework and enable compilationRichard Henderson2017-01-231-0/+111
This is just about the minimum required to enable compilation without actually executing any instructions. This contains the HPPACPU structure and the required callbacks, the gdbstub, the basic translation loop, and a translate_one function that always results in an illegal instruction. Signed-off-by: Richard Henderson <rth@twiddle.net>