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* target/hppa: Raise exception 26 on emulated hardwareHelge Deller2018-10-171-1/+2
| | | | | | | | | | | | | | | | | | | | On PCXS chips (PA7000, pa 1.1a), trap #18 is raised on memory faults, while all later chips (>= PA7100) generate either trap #26, #27 or #28 (depending on the fault type). Since the current qemu emulation emulates a B160L machine (with a PA7300LC PCX-L2 chip, we should raise trap #26 (EXCP_DMAR) instead of #18 (EXCP_DMP) on access faults by the Linux kernel to page zero. With the patch we now get the correct output (I tested against real hardware): Kernel Fault: Code=26 (Data memory access rights trap) instead of: Kernel Fault: Code=18 (Data memory protection/unaligned access trap) Signed-off-by: Helge Deller <deller@gmx.de> Message-Id: <20181007205153.GA30270@ls3530.fritz.box> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* target/hppa: Only use EXCP_DTLB_MISSRichard Henderson2018-01-311-1/+3
| | | | | | | | Unknown why this works, but if we return EXCP_ITLB_MISS we will triple-fault the first userland instruction fetch. Is it something to do with having a combined I/DTLB? Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* target/hppa: Implement B,GATE insnRichard Henderson2018-01-311-0/+8
| | | | Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* target/hppa: Implement LPARichard Henderson2018-01-301-0/+21
| | | | Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* target/hppa: Implement P*TLB and P*TLBE insnsRichard Henderson2018-01-301-0/+37
| | | | | | We now have all of the TLB manipulation instructions. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* target/hppa: Implement I*TLBA and I*TLBP insnsRichard Henderson2018-01-301-2/+78
| | | | | | The TLB can now be populated, but it cannot yet be cleared. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* target/hppa: Implement tlb_fillRichard Henderson2018-01-301-7/+155
| | | | | | | | However since HPPA has a software-managed TLB, and the relevant TLB manipulation instructions are not implemented, this does not actually do anything. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* target/hppa: Add control registersRichard Henderson2018-01-301-1/+1
| | | | Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* target/hppa: Define hardware exception typesRichard Henderson2018-01-301-1/+3
| | | | Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* target/hppa: Skeleton support for hppa-softmmuHelge Deller2018-01-301-0/+54
With the addition of default-configs/hppa-softmmu.mak, this will compile. It is not enabled with this patch, however. Signed-off-by: Helge Deller <deller@gmx.de> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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