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* overall/alpha tcg cpus|hppa: Fix Lesser GPL version numberChetan Pant2020-11-151-1/+1
| | | | | | | | | | | | There is no "version 2" of the "Lesser" General Public License. It is either "GPL version 2.0" or "Lesser GPL version 2.1". This patch replaces all occurrences of "Lesser GPL version 2" with "Lesser GPL version 2.1" in comment section. Signed-off-by: Chetan Pant <chetan4windows@gmail.com> Message-Id: <20201023123353.19796-1-chetan4windows@gmail.com> Reviewed-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
* meson: targetPaolo Bonzini2020-08-211-1/+1
| | | | | | | | | Similar to hw_arch, each architecture defines two sourceset which are placed in dictionaries target_arch and target_softmmu_arch. These are then picked up from there when building the per-emulator static_library. Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
* meson: rename included C source files to .c.incPaolo Bonzini2020-08-211-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | With Makefiles that have automatically generated dependencies, you generated includes are set as dependencies of the Makefile, so that they are built before everything else and they are available when first building the .c files. Alternatively you can use a fine-grained dependency, e.g. target/arm/translate.o: target/arm/decode-neon-shared.inc.c With Meson you have only one choice and it is a third option, namely "build at the beginning of the corresponding target"; the way you express it is to list the includes in the sources of that target. The problem is that Meson decides if something is a source vs. a generated include by looking at the extension: '.c', '.cc', '.m', '.C' are sources, while everything else is considered an include---including '.inc.c'. Use '.c.inc' to avoid this, as it is consistent with our other convention of using '.rst.inc' for included reStructuredText files. The editorconfig file is adjusted. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
* target/hppa: Free some temps in do_subRichard Henderson2020-07-241-0/+2
| | | | | | | | | | | | Two temps allocated but not freed. Do enough subtractions within a single TB and one can run out of temps entirely. Fixes: b2167459ae ("target-hppa: Implement basic arithmetic") Buglink: https://bugs.launchpad.net/qemu/+bug/1880287 Tested-by: Sven Schnelle <svens@stackframe.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20200720174039.517902-1-richard.henderson@linaro.org>
* target/hppa: Allow, but diagnose, LDCW aligned only mod 4Richard Henderson2020-01-271-1/+14
| | | | | | | | | | | | | | | | | The PA-RISC 1.1 specification says that LDCW must be aligned mod 16 or the operation is undefined. However, real hardware only generates an unaligned access trap for unaligned mod 4. Match real hardware, but diagnose with GUEST_ERROR a violation of the specification. At the same time fix a bug in the initialization of mop, where the size was specified twice, and another to free the zero temporary. Tested-by: Helge Deller <deller@gmx.de> Reported-by: Helge Deller <deller@gmx.de> Suggested-by: John David Anglin <dave.anglin@bell.net> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg: Search includes from the project root source directoryPhilippe Mathieu-Daudé2020-01-161-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We currently search both the root and the tcg/ directories for tcg files: $ git grep '#include "tcg/' | wc -l 28 $ git grep '#include "tcg[^/]' | wc -l 94 To simplify the preprocessor search path, unify by expliciting the tcg/ directory. Patch created mechanically by running: $ for x in \ tcg.h tcg-mo.h tcg-op.h tcg-opc.h \ tcg-op-gvec.h tcg-gvec-desc.h; do \ sed -i "s,#include \"$x\",#include \"tcg/$x\"," \ $(git grep -l "#include \"$x\""); \ done Acked-by: David Gibson <david@gibson.dropbear.id.au> (ppc parts) Reviewed-by: Paolo Bonzini <pbonzini@redhat.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Stefan Weil <sw@weilnetz.de> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-Id: <20200101112303.20724-2-philmd@redhat.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* target/hppa: fetch code with translator_ldEmilio G. Cota2019-10-281-1/+1
| | | | | | Signed-off-by: Emilio G. Cota <cota@braap.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
* target/hppa: prevent trashing of temporary in do_depw_sar()Sven Schnelle2019-09-141-4/+6
| | | | | | | | | nullify_over() calls brcond which destroys all temporaries. Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Signed-off-by: Sven Schnelle <svens@stackframe.org> Message-Id: <20190913101714.29019-3-svens@stackframe.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* target/hppa: prevent trashing of temporary in trans_mtctl()Sven Schnelle2019-09-141-1/+4
| | | | | | | | nullify_over() calls brcond which destroys all temporaries. Signed-off-by: Sven Schnelle <svens@stackframe.org> Message-Id: <20190913101714.29019-2-svens@stackframe.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg: TCGMemOp is now accelerator independent MemOpTony Nguyen2019-09-031-7/+7
| | | | | | | | | | | | | | Preparation for collapsing the two byte swaps, adjust_endianness and handle_bswap, along the I/O path. Target dependant attributes are conditionalized upon NEED_CPU_H. Signed-off-by: Tony Nguyen <tony.nguyen@bt.com> Acked-by: David Gibson <david@gibson.dropbear.id.au> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Acked-by: Cornelia Huck <cohuck@redhat.com> Message-Id: <81d9cd7d7f5aaadfa772d6c48ecee834e9cf7882.1566466906.git.tony.nguyen@bt.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* icount: remove unnecessary gen_io_end callsPavel Dovgalyuk2019-08-201-1/+0Star
| | | | | | | | | | | Prior patch resets can_do_io flag at the TB entry. Therefore there is no need in resetting this flag at the end of the block. This patch removes redundant gen_io_end calls. Signed-off-by: Pavel Dovgalyuk <Pavel.Dovgaluk@ispras.ru> Message-Id: <156404429499.18669.13404064982854123855.stgit@pasha-Precision-3630-Tower> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Pavel Dovgalyuk <pavel.dovgaluk@gmail.com>
* decodetree: Add DisasContext argument to !function expandersRichard Henderson2019-05-061-8/+8
| | | | | | This does require adjusting all existing users. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* target/hppa: Implement Fast TLB Insert instructionsNick Hudson2019-04-291-0/+54
| | | | | | | | | | | | | These instructions are present on pcxl and pcxl2 machines, and are used by NetBSD and OpenBSD. See https://parisc.wiki.kernel.org/images-parisc/a/a9/Pcxl2_ers.pdf page 13-9 (195/206) Signed-off-by: Nick Hudson <skrll@netbsd.org> Message-Id: <20190423063621.8203-2-nick.hudson@gmx.co.uk> [rth: Use extending loads, locally managed temporaries.] Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg: Hoist max_insns computation to tb_gen_codeRichard Henderson2019-04-241-3/+2Star
| | | | | | | | | | In order to handle TB's that translate to too much code, we need to place the control of the length of the translation in the hands of the code gen master loop. Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* target/hppa: Avoid squishing DISAS_IAQ_N_STALE_EXITRichard Henderson2019-03-151-14/+28
| | | | | | | | | | | Within a delay slot, we were squishing both DISAS_IAQ_N_STALE and DISAS_IAQ_N_STALE_EXIT to DISAS_IAQ_N_UPDATED. This lost the required exit to the main loop, and could result in interrupts never being delivered. Tested-by: Sven Schnelle <svens@stackframe.org> Reported-by: Sven Schnelle <svens@stackframe.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* target/hppa: exit TB if either Data or Instruction TLB changesSven Schnelle2019-03-121-4/+3Star
| | | | | | | | | | | | | | | The current code assumes that we don't need to exit the TB if a Data Cache Flush or Insert has happend. However, as we have a shared Data/Instruction TLB, a Data cache flush also flushes Instruction TLB entries, and a Data cache TLB insert might also evict a Instruction TLB entry. So exit the TB in all cases if Instruction translation is enabled. Signed-off-by: Sven Schnelle <svens@stackframe.org> Message-Id: <20190311191602.25796-11-svens@stackframe.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* target/hppa: add TLB protection id checkSven Schnelle2019-03-121-0/+10
| | | | | | | Signed-off-by: Sven Schnelle <svens@stackframe.org> Message-Id: <20190311191602.25796-10-svens@stackframe.org> [rth: Add required tlb flushing when prot id registers change.] Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* target/hppa: fix b,gate instructionSven Schnelle2019-03-121-1/+12
| | | | | | | | | | | b,gate does GR[t] ← cat(GR[t]{0..29},IAOQ_Front{30..31}); instead of saving the link address to register t. Signed-off-by: Sven Schnelle <svens@stackframe.org> Message-Id: <20190311191602.25796-8-svens@stackframe.org> [rth: Move link check outside of ifndef CONFIG_USER_ONLY; use ctx->privilege; nullify the insn earlier.] Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* target/hppa: ignore DIAG opcodeSven Schnelle2019-03-121-0/+7
| | | | | | | | | | | DIAG is usually only used by diagnostics software as it's CPU specific. In most of the cases it's better to ignore it and log a message that it's not implemented. Signed-off-by: Sven Schnelle <svens@stackframe.org> Message-Id: <20190311191602.25796-7-svens@stackframe.org> [rth: Free the nullify condition.] Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* target/hppa: fix overwriting source reg in addbSven Schnelle2019-03-121-1/+3
| | | | | | | | | | | When one of the source registers is the same as the destination register, the source register gets overwritten with the destionation value before do_add_sv() is called, which leads to unexpection condition matches. Signed-off-by: Sven Schnelle <svens@stackframe.org> Message-Id: <20190311191602.25796-2-svens@stackframe.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* target/hppa: Check for page crossings in use_goto_tbRichard Henderson2019-03-121-6/+4Star
| | | | | | | | | | We got away with eliding this check when target/hppa was user-only, but missed adding this check when adding system support. Fixes an early crash in the HP-UX 11 installer. Reported-by: Sven Schnelle <svens@stackframe.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* target/hppa: Optimize blr r0,rnRichard Henderson2019-03-081-6/+10
| | | | | | | We can eliminate an extra TB in this case, which merely loads a "return address" into rn. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* target/hppa: Do not return freed temporaryRichard Henderson2019-03-081-3/+2Star
| | | | | | | For priv levels 1 & 2, we were doing so from do_ibranch_priv. Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* target/hppa: fix dcor instructionSven Schnelle2019-02-121-1/+1
| | | | | | | | | | | | | | | | | | | It looks like the operands where exchanged. HP bootrom tests the following sequence: 0x00000000f0004064: ldil L%-66666800,r7 0x00000000f0004068: addi 19f,r7,r7 0x00000000f000406c: addi -1,r0,rp 0x00000000f0004070: addi f,r0,r4 0x00000000f0004074: addi 1,r4,r5 0x00000000f0004078: dcor rp,r6 0x00000000f000407c: cmpb,<>,n r6,r7,0xf000411 This returned 0x66666661 instead of the expected 0x9999999f in QEMU. Signed-off-by: Sven Schnelle <svens@stackframe.org> Message-Id: <20190211181907.2219-6-svens@stackframe.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* target/hppa: Fix addition '</<=' conditionsSven Schnelle2019-02-121-36/+57
| | | | | | | | | These conditions include the signed overflow bit. See page 5-3 of the Parisc 1.1 Architecture Reference Manual for details. Signed-off-by: Sven Schnelle <svens@stackframe.org> [rth: More changes for c == 3, to compute (N^V)|Z properly.] Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* target/hppa: Rearrange log conditionsRichard Henderson2019-02-121-7/+49
| | | | | | | We will be fixing do_cond vs signed overflow, which requires that do_log_cond not rely on do_cond. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* target/hppa: Merge translate_one into hppa_tr_translate_insnRichard Henderson2019-02-121-8/+3Star
| | | | | | | | | Now that the implementation is entirely within the generated decode function, eliminate the wrapper. Tested-by: Helge Deller <deller@gmx.de> Tested-by: Sven Schnelle <svens@stackframe.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* target/hppa: Convert fp operate insnsRichard Henderson2019-02-121-435/+308Star
| | | | | | Tested-by: Helge Deller <deller@gmx.de> Tested-by: Sven Schnelle <svens@stackframe.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* target/hppa: Convert fp fused multiply-add insnsRichard Henderson2019-02-121-53/+24Star
| | | | | | Tested-by: Helge Deller <deller@gmx.de> Tested-by: Sven Schnelle <svens@stackframe.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* target/hppa: Convert halt/reset insnsRichard Henderson2019-02-121-33/+14Star
| | | | | | Tested-by: Helge Deller <deller@gmx.de> Tested-by: Sven Schnelle <svens@stackframe.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* target/hppa: Convert fp indexed memory insnsRichard Henderson2019-02-121-93/+0Star
| | | | | | Tested-by: Helge Deller <deller@gmx.de> Tested-by: Sven Schnelle <svens@stackframe.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* target/hppa: Convert offset memory insnsRichard Henderson2019-02-121-165/+50Star
| | | | | | Tested-by: Helge Deller <deller@gmx.de> Tested-by: Sven Schnelle <svens@stackframe.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* target/hppa: Convert arithmetic immediate insnsRichard Henderson2019-02-121-89/+71Star
| | | | | | Tested-by: Helge Deller <deller@gmx.de> Tested-by: Sven Schnelle <svens@stackframe.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* target/hppa: Convert direct and indirect branchesRichard Henderson2019-02-121-101/+30Star
| | | | | | Tested-by: Helge Deller <deller@gmx.de> Tested-by: Sven Schnelle <svens@stackframe.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* target/hppa: Convert shift, extract, deposit insnsRichard Henderson2019-02-121-136/+79Star
| | | | | | Tested-by: Helge Deller <deller@gmx.de> Tested-by: Sven Schnelle <svens@stackframe.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* target/hppa: Convert conditional branchesRichard Henderson2019-02-121-126/+93Star
| | | | | | Tested-by: Helge Deller <deller@gmx.de> Tested-by: Sven Schnelle <svens@stackframe.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* target/hppa: Convert fp multiply-addRichard Henderson2019-02-121-29/+40
| | | | | | Tested-by: Helge Deller <deller@gmx.de> Tested-by: Sven Schnelle <svens@stackframe.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* target/hppa: Convert indexed memory insnsRichard Henderson2019-02-121-133/+36Star
| | | | | | Tested-by: Helge Deller <deller@gmx.de> Tested-by: Sven Schnelle <svens@stackframe.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* target/hppa: Convert arithmetic/logical insnsRichard Henderson2019-02-121-167/+147Star
| | | | | | Tested-by: Helge Deller <deller@gmx.de> Tested-by: Sven Schnelle <svens@stackframe.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* target/hppa: Convert memory management insnsRichard Henderson2019-02-121-111/+51Star
| | | | | | Tested-by: Helge Deller <deller@gmx.de> Tested-by: Sven Schnelle <svens@stackframe.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* target/hppa: Unify specializations of ORRichard Henderson2019-02-121-49/+59
| | | | | | | | | With decodetree.py, the specializations would conflict so we must have a single entry point for all variants of OR. Tested-by: Helge Deller <deller@gmx.de> Tested-by: Sven Schnelle <svens@stackframe.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* target/hppa: Convert remainder of system insnsRichard Henderson2019-02-121-55/+44Star
| | | | | | Tested-by: Helge Deller <deller@gmx.de> Tested-by: Sven Schnelle <svens@stackframe.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* target/hppa: Convert move to/from system registersRichard Henderson2019-02-121-35/+26Star
| | | | | | Tested-by: Helge Deller <deller@gmx.de> Tested-by: Sven Schnelle <svens@stackframe.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* target/hppa: Begin using scripts/decodetree.pyRichard Henderson2019-02-121-5/+19
| | | | | | | | Convert the BREAK instruction to start. Tested-by: Helge Deller <deller@gmx.de> Tested-by: Sven Schnelle <svens@stackframe.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* target/hppa: Use DisasContextBase.is_jmpRichard Henderson2019-02-121-483/+528
| | | | | | | | | Instead of returning DisasJumpType, immediately store it. Return true in preparation for conversion to the decodetree script. Tested-by: Helge Deller <deller@gmx.de> Tested-by: Sven Schnelle <svens@stackframe.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* target/hppa: use tb_cflags() to access tb->cflagsEmilio G. Cota2019-02-061-1/+1
| | | | | | Signed-off-by: Emilio G. Cota <cota@braap.org> Message-Id: <1518663946-2326-1-git-send-email-cota@braap.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg: Pass tb and index to tcg_gen_exit_tb separatelyRichard Henderson2018-06-021-3/+3
| | | | | | | | | Do the cast to uintptr_t within the helper, so that the compiler can type check the pointer argument. We can also do some more sanity checking of the index argument. Reviewed-by: Laurent Vivier <laurent@vivier.eu> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* translator: merge max_insns into DisasContextBaseEmilio G. Cota2018-05-091-5/+2Star
| | | | | | | | | | | While at it, use int for both num_insns and max_insns to make sure we have same-type comparisons. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Michael Clark <mjc@sifive.com> Signed-off-by: Emilio G. Cota <cota@braap.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg: Improve TCGv_ptr supportRichard Henderson2018-05-011-14/+2Star
| | | | | | | | | | | | Drop TCGV_PTR_TO_NAT and TCGV_NAT_TO_PTR internal macros. Add tcg_temp_local_new_ptr, tcg_gen_brcondi_ptr, tcg_gen_ext_i32_ptr, tcg_gen_trunc_i64_ptr, tcg_gen_extu_ptr_i64, tcg_gen_trunc_ptr_i32. Use inlines instead of macros where possible. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* target/hppa: Include priv level in user-only iaoqRichard Henderson2018-03-261-8/+4Star
| | | | | | | | | A recent glibc change relies on the fact that the iaoq must be 3, and computes an address based on that. QEMU had been ignoring the priv level for user-only, which produced an incorrect address. Reported-by: John David Anglin <dave.anglin@bell.net> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
generated by cgit v1.2.3-55-g7522 (git 2.39.0) at 2024-12-18 12:20:01 +0100