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* decodetree: Add DisasContext argument to !function expandersRichard Henderson2019-05-061-8/+8
| | | | | | This does require adjusting all existing users. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* target/hppa: Implement Fast TLB Insert instructionsNick Hudson2019-04-291-0/+54
| | | | | | | | | | | | | These instructions are present on pcxl and pcxl2 machines, and are used by NetBSD and OpenBSD. See https://parisc.wiki.kernel.org/images-parisc/a/a9/Pcxl2_ers.pdf page 13-9 (195/206) Signed-off-by: Nick Hudson <skrll@netbsd.org> Message-Id: <20190423063621.8203-2-nick.hudson@gmx.co.uk> [rth: Use extending loads, locally managed temporaries.] Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg: Hoist max_insns computation to tb_gen_codeRichard Henderson2019-04-241-3/+2Star
| | | | | | | | | | In order to handle TB's that translate to too much code, we need to place the control of the length of the translation in the hands of the code gen master loop. Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* target/hppa: Avoid squishing DISAS_IAQ_N_STALE_EXITRichard Henderson2019-03-151-14/+28
| | | | | | | | | | | Within a delay slot, we were squishing both DISAS_IAQ_N_STALE and DISAS_IAQ_N_STALE_EXIT to DISAS_IAQ_N_UPDATED. This lost the required exit to the main loop, and could result in interrupts never being delivered. Tested-by: Sven Schnelle <svens@stackframe.org> Reported-by: Sven Schnelle <svens@stackframe.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* target/hppa: exit TB if either Data or Instruction TLB changesSven Schnelle2019-03-121-4/+3Star
| | | | | | | | | | | | | | | The current code assumes that we don't need to exit the TB if a Data Cache Flush or Insert has happend. However, as we have a shared Data/Instruction TLB, a Data cache flush also flushes Instruction TLB entries, and a Data cache TLB insert might also evict a Instruction TLB entry. So exit the TB in all cases if Instruction translation is enabled. Signed-off-by: Sven Schnelle <svens@stackframe.org> Message-Id: <20190311191602.25796-11-svens@stackframe.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* target/hppa: add TLB protection id checkSven Schnelle2019-03-121-0/+10
| | | | | | | Signed-off-by: Sven Schnelle <svens@stackframe.org> Message-Id: <20190311191602.25796-10-svens@stackframe.org> [rth: Add required tlb flushing when prot id registers change.] Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* target/hppa: fix b,gate instructionSven Schnelle2019-03-121-1/+12
| | | | | | | | | | | b,gate does GR[t] ← cat(GR[t]{0..29},IAOQ_Front{30..31}); instead of saving the link address to register t. Signed-off-by: Sven Schnelle <svens@stackframe.org> Message-Id: <20190311191602.25796-8-svens@stackframe.org> [rth: Move link check outside of ifndef CONFIG_USER_ONLY; use ctx->privilege; nullify the insn earlier.] Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* target/hppa: ignore DIAG opcodeSven Schnelle2019-03-121-0/+7
| | | | | | | | | | | DIAG is usually only used by diagnostics software as it's CPU specific. In most of the cases it's better to ignore it and log a message that it's not implemented. Signed-off-by: Sven Schnelle <svens@stackframe.org> Message-Id: <20190311191602.25796-7-svens@stackframe.org> [rth: Free the nullify condition.] Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* target/hppa: fix overwriting source reg in addbSven Schnelle2019-03-121-1/+3
| | | | | | | | | | | When one of the source registers is the same as the destination register, the source register gets overwritten with the destionation value before do_add_sv() is called, which leads to unexpection condition matches. Signed-off-by: Sven Schnelle <svens@stackframe.org> Message-Id: <20190311191602.25796-2-svens@stackframe.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* target/hppa: Check for page crossings in use_goto_tbRichard Henderson2019-03-121-6/+4Star
| | | | | | | | | | We got away with eliding this check when target/hppa was user-only, but missed adding this check when adding system support. Fixes an early crash in the HP-UX 11 installer. Reported-by: Sven Schnelle <svens@stackframe.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* target/hppa: Optimize blr r0,rnRichard Henderson2019-03-081-6/+10
| | | | | | | We can eliminate an extra TB in this case, which merely loads a "return address" into rn. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* target/hppa: Do not return freed temporaryRichard Henderson2019-03-081-3/+2Star
| | | | | | | For priv levels 1 & 2, we were doing so from do_ibranch_priv. Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* target/hppa: fix dcor instructionSven Schnelle2019-02-121-1/+1
| | | | | | | | | | | | | | | | | | | It looks like the operands where exchanged. HP bootrom tests the following sequence: 0x00000000f0004064: ldil L%-66666800,r7 0x00000000f0004068: addi 19f,r7,r7 0x00000000f000406c: addi -1,r0,rp 0x00000000f0004070: addi f,r0,r4 0x00000000f0004074: addi 1,r4,r5 0x00000000f0004078: dcor rp,r6 0x00000000f000407c: cmpb,<>,n r6,r7,0xf000411 This returned 0x66666661 instead of the expected 0x9999999f in QEMU. Signed-off-by: Sven Schnelle <svens@stackframe.org> Message-Id: <20190211181907.2219-6-svens@stackframe.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* target/hppa: Fix addition '</<=' conditionsSven Schnelle2019-02-121-36/+57
| | | | | | | | | These conditions include the signed overflow bit. See page 5-3 of the Parisc 1.1 Architecture Reference Manual for details. Signed-off-by: Sven Schnelle <svens@stackframe.org> [rth: More changes for c == 3, to compute (N^V)|Z properly.] Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* target/hppa: Rearrange log conditionsRichard Henderson2019-02-121-7/+49
| | | | | | | We will be fixing do_cond vs signed overflow, which requires that do_log_cond not rely on do_cond. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* target/hppa: Merge translate_one into hppa_tr_translate_insnRichard Henderson2019-02-121-8/+3Star
| | | | | | | | | Now that the implementation is entirely within the generated decode function, eliminate the wrapper. Tested-by: Helge Deller <deller@gmx.de> Tested-by: Sven Schnelle <svens@stackframe.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* target/hppa: Convert fp operate insnsRichard Henderson2019-02-121-435/+308Star
| | | | | | Tested-by: Helge Deller <deller@gmx.de> Tested-by: Sven Schnelle <svens@stackframe.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* target/hppa: Convert fp fused multiply-add insnsRichard Henderson2019-02-121-53/+24Star
| | | | | | Tested-by: Helge Deller <deller@gmx.de> Tested-by: Sven Schnelle <svens@stackframe.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* target/hppa: Convert halt/reset insnsRichard Henderson2019-02-121-33/+14Star
| | | | | | Tested-by: Helge Deller <deller@gmx.de> Tested-by: Sven Schnelle <svens@stackframe.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* target/hppa: Convert fp indexed memory insnsRichard Henderson2019-02-121-93/+0Star
| | | | | | Tested-by: Helge Deller <deller@gmx.de> Tested-by: Sven Schnelle <svens@stackframe.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* target/hppa: Convert offset memory insnsRichard Henderson2019-02-121-165/+50Star
| | | | | | Tested-by: Helge Deller <deller@gmx.de> Tested-by: Sven Schnelle <svens@stackframe.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* target/hppa: Convert arithmetic immediate insnsRichard Henderson2019-02-121-89/+71Star
| | | | | | Tested-by: Helge Deller <deller@gmx.de> Tested-by: Sven Schnelle <svens@stackframe.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* target/hppa: Convert direct and indirect branchesRichard Henderson2019-02-121-101/+30Star
| | | | | | Tested-by: Helge Deller <deller@gmx.de> Tested-by: Sven Schnelle <svens@stackframe.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* target/hppa: Convert shift, extract, deposit insnsRichard Henderson2019-02-121-136/+79Star
| | | | | | Tested-by: Helge Deller <deller@gmx.de> Tested-by: Sven Schnelle <svens@stackframe.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* target/hppa: Convert conditional branchesRichard Henderson2019-02-121-126/+93Star
| | | | | | Tested-by: Helge Deller <deller@gmx.de> Tested-by: Sven Schnelle <svens@stackframe.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* target/hppa: Convert fp multiply-addRichard Henderson2019-02-121-29/+40
| | | | | | Tested-by: Helge Deller <deller@gmx.de> Tested-by: Sven Schnelle <svens@stackframe.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* target/hppa: Convert indexed memory insnsRichard Henderson2019-02-121-133/+36Star
| | | | | | Tested-by: Helge Deller <deller@gmx.de> Tested-by: Sven Schnelle <svens@stackframe.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* target/hppa: Convert arithmetic/logical insnsRichard Henderson2019-02-121-167/+147Star
| | | | | | Tested-by: Helge Deller <deller@gmx.de> Tested-by: Sven Schnelle <svens@stackframe.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* target/hppa: Convert memory management insnsRichard Henderson2019-02-121-111/+51Star
| | | | | | Tested-by: Helge Deller <deller@gmx.de> Tested-by: Sven Schnelle <svens@stackframe.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* target/hppa: Unify specializations of ORRichard Henderson2019-02-121-49/+59
| | | | | | | | | With decodetree.py, the specializations would conflict so we must have a single entry point for all variants of OR. Tested-by: Helge Deller <deller@gmx.de> Tested-by: Sven Schnelle <svens@stackframe.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* target/hppa: Convert remainder of system insnsRichard Henderson2019-02-121-55/+44Star
| | | | | | Tested-by: Helge Deller <deller@gmx.de> Tested-by: Sven Schnelle <svens@stackframe.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* target/hppa: Convert move to/from system registersRichard Henderson2019-02-121-35/+26Star
| | | | | | Tested-by: Helge Deller <deller@gmx.de> Tested-by: Sven Schnelle <svens@stackframe.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* target/hppa: Begin using scripts/decodetree.pyRichard Henderson2019-02-121-5/+19
| | | | | | | | Convert the BREAK instruction to start. Tested-by: Helge Deller <deller@gmx.de> Tested-by: Sven Schnelle <svens@stackframe.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* target/hppa: Use DisasContextBase.is_jmpRichard Henderson2019-02-121-483/+528
| | | | | | | | | Instead of returning DisasJumpType, immediately store it. Return true in preparation for conversion to the decodetree script. Tested-by: Helge Deller <deller@gmx.de> Tested-by: Sven Schnelle <svens@stackframe.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* target/hppa: use tb_cflags() to access tb->cflagsEmilio G. Cota2019-02-061-1/+1
| | | | | | Signed-off-by: Emilio G. Cota <cota@braap.org> Message-Id: <1518663946-2326-1-git-send-email-cota@braap.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg: Pass tb and index to tcg_gen_exit_tb separatelyRichard Henderson2018-06-021-3/+3
| | | | | | | | | Do the cast to uintptr_t within the helper, so that the compiler can type check the pointer argument. We can also do some more sanity checking of the index argument. Reviewed-by: Laurent Vivier <laurent@vivier.eu> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* translator: merge max_insns into DisasContextBaseEmilio G. Cota2018-05-091-5/+2Star
| | | | | | | | | | | While at it, use int for both num_insns and max_insns to make sure we have same-type comparisons. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Michael Clark <mjc@sifive.com> Signed-off-by: Emilio G. Cota <cota@braap.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg: Improve TCGv_ptr supportRichard Henderson2018-05-011-14/+2Star
| | | | | | | | | | | | Drop TCGV_PTR_TO_NAT and TCGV_NAT_TO_PTR internal macros. Add tcg_temp_local_new_ptr, tcg_gen_brcondi_ptr, tcg_gen_ext_i32_ptr, tcg_gen_trunc_i64_ptr, tcg_gen_extu_ptr_i64, tcg_gen_trunc_ptr_i32. Use inlines instead of macros where possible. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* target/hppa: Include priv level in user-only iaoqRichard Henderson2018-03-261-8/+4Star
| | | | | | | | | A recent glibc change relies on the fact that the iaoq must be 3, and computes an address based on that. QEMU had been ignoring the priv level for user-only, which produced an incorrect address. Reported-by: John David Anglin <dave.anglin@bell.net> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* target/hppa: Implement PROBE for system modeRichard Henderson2018-01-311-4/+16
| | | | Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* target/hppa: Fix 32-bit operand masks for 0E FCVTRichard Henderson2018-01-311-7/+7
| | | | | | | We masked the wrong bits, which prevented some of the 32-bit R registers. E.g. "fcnvxf,sgl,sgl fr22R,fr6R". Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* target/hppa: Implement STWARichard Henderson2018-01-311-1/+18
| | | | Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* target/hppa: Implement a pause instructionRichard Henderson2018-01-311-0/+36
| | | | | | | This is an extension to the base ISA, but we can use this in the kernel idle loop to reduce the host cpu time consumed. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* target/hppa: Implement LDSID for system modeHelge Deller2018-01-311-1/+13
| | | | | | Signed-off-by: Helge Deller <deller@gmx.de> Message-Id: <20180102203145.GA17059@ls3530.fritz.box> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* target/hppa: Fix commentHelge Deller2018-01-311-1/+1
| | | | | | Signed-off-by: Helge Deller <deller@gmx.de> Message-Id: <20171212212319.GA31494@ls3530.fritz.box> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* target/hppa: Increase number of temp regsRichard Henderson2018-01-311-1/+1
| | | | | | | HP-UX 10.20 CD contains "add r0, r0, r27" in a delay slot, which uses at least 5 temps. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* target/hppa: Implement B,GATE insnRichard Henderson2018-01-311-0/+48
| | | | Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* target/hppa: Optimize for flat addressing spaceRichard Henderson2018-01-311-9/+20
| | | | | | | | Linux sets sr4-sr7 all to the same value, which means that we need not do any runtime computation to find out what space to use in forming the GVA. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* target/hppa: Implement halt and reset instructionsHelge Deller2018-01-311-1/+24
| | | | | | | | | Real hardware would use an external device to control the power. But for the moment let's invent instructions in reserved space, to be used by our custom firmware. Signed-off-by: Helge Deller <deller@gmx.de> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* target/hppa: Implement SYNCDMA insnRichard Henderson2018-01-301-1/+2
| | | | Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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