summaryrefslogtreecommitdiffstats
path: root/target/hppa
Commit message (Collapse)AuthorAgeFilesLines
...
* target: Simplify how the TARGET_cpu_list() printMarkus Armbruster2019-04-182-10/+6Star
| | | | | | | | | | | | | | | | | The various TARGET_cpu_list() take an fprintf()-like callback and a FILE * to pass to it. Their callers (vl.c's main() via list_cpus(), bsd-user/main.c's main(), linux-user/main.c's main()) all pass fprintf() and stdout. Thus, the flexibility provided by the (rather tiresome) indirection isn't actually used. Drop the callback, and call qemu_printf() instead. Calling printf() would also work, but would make the code unsuitable for monitor context without making it simpler. Signed-off-by: Markus Armbruster <armbru@redhat.com> Message-Id: <20190417191805.28198-10-armbru@redhat.com> Reviewed-by: Dr. David Alan Gilbert <dgilbert@redhat.com>
* trace-events: Shorten file names in commentsMarkus Armbruster2019-03-221-2/+2
| | | | | | | | | | | | | | | We spell out sub/dir/ in sub/dir/trace-events' comments pointing to source files. That's because when trace-events got split up, the comments were moved verbatim. Delete the sub/dir/ part from these comments. Gets rid of several misspellings. Signed-off-by: Markus Armbruster <armbru@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-id: 20190314180929.27722-3-armbru@redhat.com Message-Id: <20190314180929.27722-3-armbru@redhat.com> Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
* target/hppa: Avoid squishing DISAS_IAQ_N_STALE_EXITRichard Henderson2019-03-151-14/+28
| | | | | | | | | | | Within a delay slot, we were squishing both DISAS_IAQ_N_STALE and DISAS_IAQ_N_STALE_EXIT to DISAS_IAQ_N_UPDATED. This lost the required exit to the main loop, and could result in interrupts never being delivered. Tested-by: Sven Schnelle <svens@stackframe.org> Reported-by: Sven Schnelle <svens@stackframe.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* target/hppa: exit TB if either Data or Instruction TLB changesSven Schnelle2019-03-121-4/+3Star
| | | | | | | | | | | | | | | The current code assumes that we don't need to exit the TB if a Data Cache Flush or Insert has happend. However, as we have a shared Data/Instruction TLB, a Data cache flush also flushes Instruction TLB entries, and a Data cache TLB insert might also evict a Instruction TLB entry. So exit the TB in all cases if Instruction translation is enabled. Signed-off-by: Sven Schnelle <svens@stackframe.org> Message-Id: <20190311191602.25796-11-svens@stackframe.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* target/hppa: add TLB protection id checkSven Schnelle2019-03-126-9/+70
| | | | | | | Signed-off-by: Sven Schnelle <svens@stackframe.org> Message-Id: <20190311191602.25796-10-svens@stackframe.org> [rth: Add required tlb flushing when prot id registers change.] Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* target/hppa: allow multiple itlbp without itlbaSven Schnelle2019-03-121-1/+1
| | | | | | | | | The ODE software calls itlbp on existing TLB entries without calling itlba first, so this seems to be valid. Signed-off-by: Sven Schnelle <svens@stackframe.org> Message-Id: <20190311191602.25796-9-svens@stackframe.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* target/hppa: fix b,gate instructionSven Schnelle2019-03-121-1/+12
| | | | | | | | | | | b,gate does GR[t] ← cat(GR[t]{0..29},IAOQ_Front{30..31}); instead of saving the link address to register t. Signed-off-by: Sven Schnelle <svens@stackframe.org> Message-Id: <20190311191602.25796-8-svens@stackframe.org> [rth: Move link check outside of ifndef CONFIG_USER_ONLY; use ctx->privilege; nullify the insn earlier.] Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* target/hppa: ignore DIAG opcodeSven Schnelle2019-03-122-0/+10
| | | | | | | | | | | DIAG is usually only used by diagnostics software as it's CPU specific. In most of the cases it's better to ignore it and log a message that it's not implemented. Signed-off-by: Sven Schnelle <svens@stackframe.org> Message-Id: <20190311191602.25796-7-svens@stackframe.org> [rth: Free the nullify condition.] Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* target/hppa: remove PSW I/R/Q bit checkSven Schnelle2019-03-121-5/+0Star
| | | | | | | | | | HP ODE use rfi to set the Q bit, and i don't see anything in the documentation that this is forbidden. So remove it. Signed-off-by: Sven Schnelle <svens@stackframe.org> Message-Id: <20190311191602.25796-6-svens@stackframe.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* target/hppa: add TLB trace eventsSven Schnelle2019-03-123-2/+39
| | | | | | | | | | To ease TLB debugging add a few trace events, which are disabled by default so that there's no performance impact. Signed-off-by: Sven Schnelle <svens@stackframe.org> Message-Id: <20190311191602.25796-5-svens@stackframe.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* target/hppa: report ITLB_EXCP_MISS for ITLB missesSven Schnelle2019-03-121-3/+1Star
| | | | | | | Signed-off-by: Sven Schnelle <svens@stackframe.org> Message-Id: <20190311191602.25796-4-svens@stackframe.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* target/hppa: fix TLB handling for page 0Sven Schnelle2019-03-121-5/+7
| | | | | | | | | | | | | | | | | | | | Assume the following sequence: pitlbe r0(sr0,r0) iitlba r4,(sr0,r0) ldil L%3000000,r5 iitlbp r5,(sr0,r0) This will purge the whole TLB and add an entry for page 0. However the current TLB implementation in helper_iitlba() will store to the last empty TLB entry, while helper_iitlbp() will write to the first empty entry. That is because an empty entry will match address 0 in helper_iitlba() Signed-off-by: Sven Schnelle <svens@stackframe.org> Message-Id: <20190311191602.25796-3-svens@stackframe.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* target/hppa: fix overwriting source reg in addbSven Schnelle2019-03-121-1/+3
| | | | | | | | | | | When one of the source registers is the same as the destination register, the source register gets overwritten with the destionation value before do_add_sv() is called, which leads to unexpection condition matches. Signed-off-by: Sven Schnelle <svens@stackframe.org> Message-Id: <20190311191602.25796-2-svens@stackframe.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* target/hppa: Check for page crossings in use_goto_tbRichard Henderson2019-03-121-6/+4Star
| | | | | | | | | | We got away with eliding this check when target/hppa was user-only, but missed adding this check when adding system support. Fixes an early crash in the HP-UX 11 installer. Reported-by: Sven Schnelle <svens@stackframe.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* target/hppa: Optimize blr r0,rnRichard Henderson2019-03-081-6/+10
| | | | | | | We can eliminate an extra TB in this case, which merely loads a "return address" into rn. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* target/hppa: Do not return freed temporaryRichard Henderson2019-03-081-3/+2Star
| | | | | | | For priv levels 1 & 2, we were doing so from do_ibranch_priv. Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* target/hppa: fix dcor instructionSven Schnelle2019-02-121-1/+1
| | | | | | | | | | | | | | | | | | | It looks like the operands where exchanged. HP bootrom tests the following sequence: 0x00000000f0004064: ldil L%-66666800,r7 0x00000000f0004068: addi 19f,r7,r7 0x00000000f000406c: addi -1,r0,rp 0x00000000f0004070: addi f,r0,r4 0x00000000f0004074: addi 1,r4,r5 0x00000000f0004078: dcor rp,r6 0x00000000f000407c: cmpb,<>,n r6,r7,0xf000411 This returned 0x66666661 instead of the expected 0x9999999f in QEMU. Signed-off-by: Sven Schnelle <svens@stackframe.org> Message-Id: <20190211181907.2219-6-svens@stackframe.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* target/hppa: Fix addition '</<=' conditionsSven Schnelle2019-02-121-36/+57
| | | | | | | | | These conditions include the signed overflow bit. See page 5-3 of the Parisc 1.1 Architecture Reference Manual for details. Signed-off-by: Sven Schnelle <svens@stackframe.org> [rth: More changes for c == 3, to compute (N^V)|Z properly.] Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* target/hppa: Rearrange log conditionsRichard Henderson2019-02-121-7/+49
| | | | | | | We will be fixing do_cond vs signed overflow, which requires that do_log_cond not rely on do_cond. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* target/hppa: move GETPC to HELPER() functionsSven Schnelle2019-02-121-10/+6Star
| | | | | | | | | When QEMU is compiled with -O0, these functions are inlined which will cause a wrong restart address generated for the TB. Signed-off-by: Sven Schnelle <svens@stackframe.org> Message-Id: <20190211181907.2219-2-svens@stackframe.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* target/hppa: Merge translate_one into hppa_tr_translate_insnRichard Henderson2019-02-121-8/+3Star
| | | | | | | | | Now that the implementation is entirely within the generated decode function, eliminate the wrapper. Tested-by: Helge Deller <deller@gmx.de> Tested-by: Sven Schnelle <svens@stackframe.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* target/hppa: Convert fp operate insnsRichard Henderson2019-02-122-435/+483
| | | | | | Tested-by: Helge Deller <deller@gmx.de> Tested-by: Sven Schnelle <svens@stackframe.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* target/hppa: Convert fp fused multiply-add insnsRichard Henderson2019-02-122-53/+36Star
| | | | | | Tested-by: Helge Deller <deller@gmx.de> Tested-by: Sven Schnelle <svens@stackframe.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* target/hppa: Convert halt/reset insnsRichard Henderson2019-02-122-33/+19Star
| | | | | | Tested-by: Helge Deller <deller@gmx.de> Tested-by: Sven Schnelle <svens@stackframe.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* target/hppa: Convert fp indexed memory insnsRichard Henderson2019-02-122-93/+21Star
| | | | | | Tested-by: Helge Deller <deller@gmx.de> Tested-by: Sven Schnelle <svens@stackframe.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* target/hppa: Convert offset memory insnsRichard Henderson2019-02-122-165/+99Star
| | | | | | Tested-by: Helge Deller <deller@gmx.de> Tested-by: Sven Schnelle <svens@stackframe.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* target/hppa: Convert arithmetic immediate insnsRichard Henderson2019-02-122-89/+92
| | | | | | Tested-by: Helge Deller <deller@gmx.de> Tested-by: Sven Schnelle <svens@stackframe.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* target/hppa: Convert direct and indirect branchesRichard Henderson2019-02-122-102/+63Star
| | | | | | Tested-by: Helge Deller <deller@gmx.de> Tested-by: Sven Schnelle <svens@stackframe.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* target/hppa: Convert shift, extract, deposit insnsRichard Henderson2019-02-122-136/+94Star
| | | | | | Tested-by: Helge Deller <deller@gmx.de> Tested-by: Sven Schnelle <svens@stackframe.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* target/hppa: Convert conditional branchesRichard Henderson2019-02-122-126/+123Star
| | | | | | Tested-by: Helge Deller <deller@gmx.de> Tested-by: Sven Schnelle <svens@stackframe.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* target/hppa: Convert fp multiply-addRichard Henderson2019-02-122-29/+52
| | | | | | Tested-by: Helge Deller <deller@gmx.de> Tested-by: Sven Schnelle <svens@stackframe.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* target/hppa: Convert indexed memory insnsRichard Henderson2019-02-122-133/+60Star
| | | | | | Tested-by: Helge Deller <deller@gmx.de> Tested-by: Sven Schnelle <svens@stackframe.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* target/hppa: Convert arithmetic/logical insnsRichard Henderson2019-02-122-167/+189
| | | | | | Tested-by: Helge Deller <deller@gmx.de> Tested-by: Sven Schnelle <svens@stackframe.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* target/hppa: Convert memory management insnsRichard Henderson2019-02-122-111/+89Star
| | | | | | Tested-by: Helge Deller <deller@gmx.de> Tested-by: Sven Schnelle <svens@stackframe.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* target/hppa: Unify specializations of ORRichard Henderson2019-02-121-49/+59
| | | | | | | | | With decodetree.py, the specializations would conflict so we must have a single entry point for all variants of OR. Tested-by: Helge Deller <deller@gmx.de> Tested-by: Sven Schnelle <svens@stackframe.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* target/hppa: Convert remainder of system insnsRichard Henderson2019-02-122-55/+56
| | | | | | Tested-by: Helge Deller <deller@gmx.de> Tested-by: Sven Schnelle <svens@stackframe.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* target/hppa: Convert move to/from system registersRichard Henderson2019-02-122-35/+41
| | | | | | Tested-by: Helge Deller <deller@gmx.de> Tested-by: Sven Schnelle <svens@stackframe.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* target/hppa: Begin using scripts/decodetree.pyRichard Henderson2019-02-123-5/+51
| | | | | | | | Convert the BREAK instruction to start. Tested-by: Helge Deller <deller@gmx.de> Tested-by: Sven Schnelle <svens@stackframe.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* target/hppa: Use DisasContextBase.is_jmpRichard Henderson2019-02-121-483/+528
| | | | | | | | | Instead of returning DisasJumpType, immediately store it. Return true in preparation for conversion to the decodetree script. Tested-by: Helge Deller <deller@gmx.de> Tested-by: Sven Schnelle <svens@stackframe.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* target/hppa: fix PSW Q bit behaviour to match hardwareSven Schnelle2019-02-061-5/+9
| | | | | | | | | | | | | | PA-RISC specification says: "Setting the PSW Q-bit, PSW{28}, to 1 with this instruction, if it was not already 1, is an undefined operation." However, at least HP-UX 10.20 sets the Q bit from 0 to 1 with the SSM instruction. Tested this both on HP9000/712 and HP9000/785/C3750, both machines set the Q bit from 0 to 1 without exception. This makes HP-UX 10.20 progress a little bit further. Signed-off-by: Sven Schnelle <svens@stackframe.org> Message-Id: <20190129191402.29539-1-svens@stackframe.org> [rth: Add a comment to the code as well.] Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* target/hppa: fix setting registers via gdbSven Schnelle2019-02-061-1/+1
| | | | | | | | | | | While doing 'set $pcoqh=0xf0000000' i triggered the assertion below. The argument order for deposit64() is wrong, and val needs to be moved to the end. Signed-off-by: Sven Schnelle <svens@stackframe.org> Message-Id: <20190128165333.3814-1-svens@stackframe.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* target/hppa: use tb_cflags() to access tb->cflagsEmilio G. Cota2019-02-061-1/+1
| | | | | | Signed-off-by: Emilio G. Cota <cota@braap.org> Message-Id: <1518663946-2326-1-git-send-email-cota@braap.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* vmstate: constify VMStateFieldMarc-André Lureau2018-11-271-4/+6
| | | | | | | | Because they are supposed to remain const. Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com> Message-Id: <20181114132931.22624-1-marcandre.lureau@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
* target/hppa: Raise exception 26 on emulated hardwareHelge Deller2018-10-171-1/+2
| | | | | | | | | | | | | | | | | | | | On PCXS chips (PA7000, pa 1.1a), trap #18 is raised on memory faults, while all later chips (>= PA7100) generate either trap #26, #27 or #28 (depending on the fault type). Since the current qemu emulation emulates a B160L machine (with a PA7300LC PCX-L2 chip, we should raise trap #26 (EXCP_DMAR) instead of #18 (EXCP_DMP) on access faults by the Linux kernel to page zero. With the patch we now get the correct output (I tested against real hardware): Kernel Fault: Code=26 (Data memory access rights trap) instead of: Kernel Fault: Code=18 (Data memory protection/unaligned access trap) Signed-off-by: Helge Deller <deller@gmx.de> Message-Id: <20181007205153.GA30270@ls3530.fritz.box> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* Merge remote-tracking branch 'remotes/rth/tags/tcg-next-pull-request' into ↵Peter Maydell2018-06-041-3/+3
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | staging tcg-next queue # gpg: Signature made Sat 02 Jun 2018 00:12:42 BST # gpg: using RSA key 64DF38E8AF7E215F # gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" # Primary key fingerprint: 7A48 1E78 868B 4DB6 A85A 05C0 64DF 38E8 AF7E 215F * remotes/rth/tags/tcg-next-pull-request: tcg: Pass tb and index to tcg_gen_exit_tb separately Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * tcg: Pass tb and index to tcg_gen_exit_tb separatelyRichard Henderson2018-06-021-3/+3
| | | | | | | | | | | | | | | | | | Do the cast to uintptr_t within the helper, so that the compiler can type check the pointer argument. We can also do some more sanity checking of the index argument. Reviewed-by: Laurent Vivier <laurent@vivier.eu> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* | target: Do not include "exec/exec-all.h" if it is not necessaryPhilippe Mathieu-Daudé2018-06-012-2/+0Star
| | | | | | | | | | | | | | | | | | | | | | | | | | Code change produced with: $ git grep '#include "exec/exec-all.h"' | \ cut -d: -f-1 | \ xargs egrep -L "(cpu_address_space_init|cpu_loop_|tlb_|tb_|GETPC|singlestep|TranslationBlock)" | \ xargs sed -i.bak '/#include "exec\/exec-all.h"/d' Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20180528232719.4721-10-f4bug@amsat.org> Acked-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
* | target/hppa: Include "qemu/log.h" to use qemu_log()Philippe Mathieu-Daudé2018-05-311-0/+1
|/ | | | | | | | | | | Since his inception in 61766fe9e2d, this file uses the qemu_log() API from "qemu/log.h". Include it to allow further includes cleanup. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20180528232719.4721-9-f4bug@amsat.org> Acked-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
* fpu/softfloat: Specialize on snan_bit_is_oneRichard Henderson2018-05-181-1/+0Star
| | | | | | | | | | | | | | | | Only MIPS requires snan_bit_is_one to be variable. While we are specializing softfloat behaviour, allow other targets to eliminate this runtime check. Cc: Aurelien Jarno <aurelien@aurel32.net> Cc: Yongbok Kim <yongbok.kim@mips.com> Cc: David Gibson <david@gibson.dropbear.id.au> Cc: Alexander Graf <agraf@suse.de> Cc: Guan Xuetao <gxt@mprc.pku.edu.cn> Tested-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* target/hppa: Remove floatX_maybe_silence_nan from conversionsRichard Henderson2018-05-181-2/+0Star
| | | | | | | | This is now handled properly by the generic softfloat code. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
generated by cgit v1.2.3-55-g7522 (git 2.39.0) at 2025-01-15 22:07:56 +0100