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* hw/i386: Consolidate topology functionsBabu Moger2020-03-181-12/+11Star
* cpu: Use DeviceClass reset instead of a special CPUClass resetPeter Maydell2020-03-181-4/+4
* i386: Add 2nd Generation AMD EPYC processorsMoger, Babu2020-03-181-1/+101
* i386: Add missing cpu feature bits in EPYC modelMoger, Babu2020-03-181-4/+13
* target/i386: Add new property note to versioned CPU modelsTao Xu2020-03-181-2/+9
* target/i386: Add Denverton-v2 (no MPX) CPU modelTao Xu2020-03-181-0/+12
* target/i386: enable monitor and ucode revision with -cpu maxPaolo Bonzini2020-02-121-0/+2
* target/i386: Add the 'model-id' for Skylake -v3 CPU modelsKashyap Chamarthy2020-01-241-0/+4
* qdev: set properties with device_class_set_props()Marc-André Lureau2020-01-241-2/+2
* target/i386: kvm: initialize microcode revision from KVMPaolo Bonzini2020-01-241-0/+4
* target/i386: add a ucode-rev propertyPaolo Bonzini2020-01-241-0/+10
* cpu: Use cpu_class_set_parent_reset()Greg Kurz2020-01-241-2/+1Star
* target/i386: Add missed features to Cooperlake CPU modelXiaoyao Li2020-01-071-1/+50
* Merge remote-tracking branch 'remotes/ehabkost/tags/x86-and-machine-pull-requ...Peter Maydell2020-01-061-1/+7
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| * i386: Resolve CPU models to v1 by defaultEduardo Habkost2019-12-191-1/+7
* | qom: add object_new_with_classPaolo Bonzini2019-12-171-4/+4
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* i386: Use g_autofree in a few placesEduardo Habkost2019-12-131-28/+13Star
* i386: Add new CPU model CooperlakeCathy Zhang2019-12-131-0/+60
* target/i386: add two missing VMX features for Skylake and CascadeLake ServerPaolo Bonzini2019-11-261-2/+4
* i386: Add -noTSX aliases for hle=off, rtm=off CPU modelsEduardo Habkost2019-11-211-0/+5
* i386: Add new versions of Skylake/Cascadelake/Icelake without TSXEduardo Habkost2019-11-211-0/+47
* target/i386: add support for MSR_IA32_TSX_CTRLPaolo Bonzini2019-11-211-1/+1
* target/i386: add VMX features to named CPU modelsPaolo Bonzini2019-11-211-0/+705
* target/i386: Export TAA_NO bit to guestsPawan Gupta2019-11-191-1/+1
* target/i386: add PSCHANGE_NO bit for the ARCH_CAPABILITIES MSRPaolo Bonzini2019-11-191-1/+1
* Merge commit 'df84f17' into HEADPaolo Bonzini2019-10-261-1/+3
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| * x86/cpu: Add support for UMONITOR/UMWAIT/TPAUSETao Xu2019-10-231-1/+1
| * i386/kvm: add NoNonArchitecturalCoreSharing Hyper-V enlightenmentVitaly Kuznetsov2019-10-221-0/+2
* | target/i386: Introduce Denverton CPU modelTao Xu2019-10-241-0/+47
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* target/i386: Add Snowridge-v2 (no MPX) CPU modelXiaoyao Li2019-10-151-0/+12
* i386: Fix legacy guest with xsave panic on host kvm without update cpuid.Bingsong Si2019-10-151-1/+7
* target/i386: drop the duplicated definition of cpuid AVX512_VBMI macroTao Xu2019-10-151-4/+4
* target/i386: add VMX featuresPaolo Bonzini2019-10-041-0/+225
* target/i386: expand feature words to 64 bitsPaolo Bonzini2019-10-041-34/+37
* target/i386: introduce generic feature dependency mechanismPaolo Bonzini2019-10-041-24/+48
* target/i386: handle filtered_features in a new function mark_unavailable_feat...Paolo Bonzini2019-10-041-39/+48
* Fix wrong behavior of cpu_memory_rw_debug() function in SMMDmitry Poletaev2019-10-041-1/+1
* i386: Add CPUID bit for CLZERO and XSAVEERPTRSebastian Andrzej Siewior2019-10-041-1/+1
* x86: Intel AVX512_BF16 feature enablingJing Liu2019-08-201-1/+38
* target-i386: adds PV_SCHED_YIELD CPUID feature bitWanpeng Li2019-08-201-1/+1
* kvm: i386: halt poll control MSR supportMarcelo Tosatti2019-08-201-1/+3
* Include hw/hw.h exactly where neededMarkus Armbruster2019-08-161-1/+0Star
* Include sysemu/reset.h a lot lessMarkus Armbruster2019-08-161-0/+1
* i386: Fix Snowridge CPU model name and featuresPaul Lai2019-07-291-2/+1Star
* i386: indicate that 'pconfig' feature was removed intentionallyDenis V. Lunev2019-07-191-1/+1
* i386: Add Cascadelake-Server-v2 CPU modelEduardo Habkost2019-07-051-0/+14
* i386: Make unversioned CPU models be aliasesEduardo Habkost2019-07-051-1/+51
* i386: Replace -noTSX, -IBRS, -IBPB CPU models with aliasesEduardo Habkost2019-07-051-580/+21Star
* i386: Define -IBRS, -noTSX, -IBRS versions of CPU modelsEduardo Habkost2019-07-051-0/+186
* i386: Register versioned CPU modelsEduardo Habkost2019-07-051-22/+201
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