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* target/i386: Simplify how x86_cpu_dump_local_apic_state() printsMarkus Armbruster2019-04-181-2/+1Star
| | | | | | | | | | | | | | | | x86_cpu_dump_local_apic_state() takes an fprintf()-like callback and a FILE * to pass to it, and so do its helper functions. Its only caller hmp_info_local_apic() passes monitor_fprintf() and the current monitor cast to FILE *. monitor_fprintf() casts it right back, and is otherwise identical to monitor_printf(). The type-punning is ugly. Drop the callback, and call qemu_printf() instead. Signed-off-by: Markus Armbruster <armbru@redhat.com> Reviewed-by: Dr. David Alan Gilbert <dgilbert@redhat.com> Message-Id: <20190417191805.28198-12-armbru@redhat.com>
* target: Simplify how the TARGET_cpu_list() printMarkus Armbruster2019-04-181-1/+1
| | | | | | | | | | | | | | | | | The various TARGET_cpu_list() take an fprintf()-like callback and a FILE * to pass to it. Their callers (vl.c's main() via list_cpus(), bsd-user/main.c's main(), linux-user/main.c's main()) all pass fprintf() and stdout. Thus, the flexibility provided by the (rather tiresome) indirection isn't actually used. Drop the callback, and call qemu_printf() instead. Calling printf() would also work, but would make the code unsuitable for monitor context without making it simpler. Signed-off-by: Markus Armbruster <armbru@redhat.com> Message-Id: <20190417191805.28198-10-armbru@redhat.com> Reviewed-by: Dr. David Alan Gilbert <dgilbert@redhat.com>
* i386: extended the cpuid_level when Intel PT is enabledLuwei Kang2019-03-111-0/+3
| | | | | | | | | | | Intel Processor Trace required CPUID[0x14] but the cpuid_level have no change when create a kvm guest with e.g. "-cpu qemu64,+intel-pt". Signed-off-by: Eduardo Habkost <ehabkost@redhat.com> Signed-off-by: Luwei Kang <luwei.kang@intel.com> Message-Id: <1548805979-12321-1-git-send-email-luwei.kang@intel.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
* Revert "i386: Add CPUID bit for PCONFIG"Robert Hoo2019-02-051-1/+0Star
| | | | | | | | | This reverts commit 5131dc433df54b37e8e918d8fba7fe10344e7a7b. For new instruction 'PCONFIG' will not be exposed to guest. Signed-off-by: Robert Hoo <robert.hu@linux.intel.com> Message-Id: <1545227081-213696-3-git-send-email-robert.hu@linux.intel.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
* x86: host-phys-bits-limit optionEduardo Habkost2019-01-141-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Some downstream distributions of QEMU set host-phys-bits=on by default. This worked very well for most use cases, because phys-bits really didn't have huge consequences. The only difference was on the CPUID data seen by guests, and on the handling of reserved bits. This changed in KVM commit 855feb673640 ("KVM: MMU: Add 5 level EPT & Shadow page table support"). Now choosing a large phys-bits value for a VM has bigger impact: it will make KVM use 5-level EPT even when it's not really necessary. This means using the host phys-bits value may not be the best choice. Management software could address this problem by manually configuring phys-bits depending on the size of the VM and the amount of MMIO address space required for hotplug. But this is not trivial to implement. However, there's another workaround that would work for most cases: keep using the host phys-bits value, but only if it's smaller than 48. This patch makes this possible by introducing a new "-cpu" option: "host-phys-bits-limit". Management software or users can make sure they will always use 4-level EPT using: "host-phys-bits=on,host-phys-bits-limit=48". This behavior is still not enabled by default because QEMU doesn't enable host-phys-bits=on by default. But users, management software, or downstream distributions may choose to change their defaults using the new option. Signed-off-by: Eduardo Habkost <ehabkost@redhat.com> Message-Id: <20181211192527.13254-1-ehabkost@redhat.com> [ehabkost: removed test code while some issues are addressed] Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
* i386/kvm: expose HV_CPUID_ENLIGHTMENT_INFO.EAX and ↵Vitaly Kuznetsov2019-01-141-0/+2
| | | | | | | | | | | | | | | | | | | HV_CPUID_NESTED_FEATURES.EAX as feature words It was found that QMP users of QEMU (e.g. libvirt) may need HV_CPUID_ENLIGHTMENT_INFO.EAX/HV_CPUID_NESTED_FEATURES.EAX information. In particular, 'hv_tlbflush' and 'hv_evmcs' enlightenments are only exposed in HV_CPUID_ENLIGHTMENT_INFO.EAX. HV_CPUID_NESTED_FEATURES.EAX is exposed for two reasons: convenience (we don't need to export it from hyperv_handle_properties() and as future-proof for Enlightened MSR-Bitmap, PV EPT invalidation and direct virtual flush features. Signed-off-by: Vitaly Kuznetsov <vkuznets@redhat.com> Message-Id: <20181126135958.20956-1-vkuznets@redhat.com> Reviewed-by: Roman Kagan <rkagan@virtuozzo.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
* x86/cpu: Enable MOVDIR64B cpu featureLiu Jingqi2018-12-111-0/+1
| | | | | | | | | | | | | | | | | | MOVDIR64B moves 64-bytes as direct-store with 64-bytes write atomicity. Direct store is implemented by using write combining (WC) for writing data directly into memory without caching the data. The bit definition: CPUID.(EAX=7,ECX=0):ECX[bit 28] MOVDIR64B The release document ref below link: https://software.intel.com/sites/default/files/managed/c5/15/\ architecture-instruction-set-extensions-programming-reference.pdf Cc: Xu Tao <tao3.xu@intel.com> Signed-off-by: Liu Jingqi <jingqi.liu@intel.com> Message-Id: <1541488407-17045-3-git-send-email-jingqi.liu@intel.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
* x86/cpu: Enable MOVDIRI cpu featureLiu Jingqi2018-12-111-0/+1
| | | | | | | | | | | | | | | | | | MOVDIRI moves doubleword or quadword from register to memory through direct store which is implemented by using write combining (WC) for writing data directly into memory without caching the data. The bit definition: CPUID.(EAX=7,ECX=0):ECX[bit 27] MOVDIRI The release document ref below link: https://software.intel.com/sites/default/files/managed/c5/15/\ architecture-instruction-set-extensions-programming-reference.pdf Cc: Xu Tao <tao3.xu@intel.com> Signed-off-by: Liu Jingqi <jingqi.liu@intel.com> Message-Id: <1541488407-17045-2-git-send-email-jingqi.liu@intel.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
* x86: hv_evmcs CPU flag supportVitaly Kuznetsov2018-11-061-0/+1
| | | | | | | | | | | | Adds a new CPU flag to enable the Enlightened VMCS KVM feature. QEMU enables KVM_CAP_HYPERV_ENLIGHTENED_VMCS and gets back the version to be advertised in lower 16 bits of CPUID.0x4000000A:EAX. Suggested-by: Ladi Prosek <lprosek@redhat.com> Signed-off-by: Vitaly Kuznetsov <vkuznets@redhat.com> Message-Id: <20181022165506.30332-3-vkuznets@redhat.com> Reviewed-by: Roman Kagan <rkagan@virtuozzo.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
* x86: define a new MSR based feature word -- FEATURE_WORDS_ARCH_CAPABILITIESRobert Hoo2018-10-311-0/+8
| | | | | | | | | | | Note RSBA is specially treated -- no matter host support it or not, qemu pretends it is supported. Signed-off-by: Robert Hoo <robert.hu@linux.intel.com> Message-Id: <1539578845-37944-4-git-send-email-robert.hu@linux.intel.com> [ehabkost: removed automatic enabling of RSBA] Reviewed-by: Eduardo Habkost <ehabkost@redhat.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
* hyperv: only add SynIC in compatible configurationsRoman Kagan2018-10-191-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Certain configurations do not allow SynIC to be used in QEMU. In particular, - when hyperv_vpindex is off, SINT routes can't be used as they refer to the destination vCPU by vp_index - older KVM (which doesn't expose KVM_CAP_HYPERV_SYNIC2) zeroes out SynIC message and event pages on every msr load, breaking migration OTOH in-KVM users of SynIC -- SynIC timers -- do work in those configurations, and we shouldn't stop the guest from using them. To cover both scenarios, introduce an X86CPU property that makes CPU init code to skip creation of the SynIC object (and thus disables any SynIC use in QEMU) but keeps the KVM part of the SynIC working. The property is clear by default but is set via compat logic for older machine types. As a result, when hv_synic and a modern machine type are specified, QEMU will refuse to run unless vp_index is on and the kernel is recent enough. OTOH with an older machine type QEMU will run fine with hv_synic=on against an older kernel and/or without vp_index enabled but will disallow the in-QEMU uses of SynIC (in e.g. VMBus). Signed-off-by: Roman Kagan <rkagan@virtuozzo.com> Message-Id: <20180921082217.29481-4-rkagan@virtuozzo.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
* i386/kvm: add support for Hyper-V IPI sendVitaly Kuznetsov2018-10-191-0/+1
| | | | | | | | | | | Hyper-V PV IPI support is merged to KVM, enable the feature in Qemu. When enabled, this allows Windows guests to send IPIs to other vCPUs with a single hypercall even when there are >64 vCPUs in the request. Signed-off-by: Vitaly Kuznetsov <vkuznets@redhat.com> Reviewed-by: Roman Kagan <rkagan@virtuozzo.com> Message-Id: <20181009130853.6412-3-vkuznets@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
* i386: Compile CPUX86State xsave_buf only when support KVM or HVFLiran Alon2018-10-021-1/+3
| | | | | | | | | | While at it, also rename var to indicate it is not used only in KVM. Reviewed-by: Nikita Leshchenko <nikita.leshchenko@oracle.com> Reviewed-by: Patrick Colp <patrick.colp@oracle.com> Signed-off-by: Liran Alon <liran.alon@oracle.com> Message-Id: <20180914003827.124570-2-liran.alon@oracle.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
* target/i386: rename HF_SVMI_MASK to HF_GUEST_MASKPaolo Bonzini2018-10-021-2/+2
| | | | | | | This flag will be used for KVM's nested VMX migration; the HF_GUEST_MASK name is already used in KVM, adopt it in QEMU as well. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
* target/i386: unify masking of interruptsPaolo Bonzini2018-10-021-0/+1
| | | | | | | | | Interrupt handling depends on various flags in env->hflags or env->hflags2, and the exact detail were not exactly replicated between x86_cpu_has_work and x86_cpu_exec_interrupt. Create a new function that extracts the highest-priority non-masked interrupt, and use it in both functions. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
* target/i386: update MPX flags when CPL changesPaolo Bonzini2018-08-231-3/+4
| | | | Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
* i386: Add CPUID bit for WBNOINVDRobert Hoo2018-08-161-0/+2
| | | | | | | | | WBNOINVD: Write back and do not invalidate cache, enumerated by CPUID.(EAX=80000008H, ECX=0):EBX[bit 9]. Signed-off-by: Robert Hoo <robert.hu@linux.intel.com> Message-Id: <1530781798-183214-5-git-send-email-robert.hu@linux.intel.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
* i386: Add CPUID bit for PCONFIGRobert Hoo2018-08-161-0/+1
| | | | | | | | | PCONFIG: Platform configuration, enumerated by CPUID.(EAX=07H, ECX=0): EDX[bit18]. Signed-off-by: Robert Hoo <robert.hu@linux.intel.com> Message-Id: <1530781798-183214-4-git-send-email-robert.hu@linux.intel.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
* i386: Add CPUID bit and feature words for IA32_ARCH_CAPABILITIES MSRRobert Hoo2018-08-161-0/+1
| | | | | | | | | | | | Support of IA32_PRED_CMD MSR already be enumerated by same CPUID bit as SPEC_CTRL. At present, mark CPUID_7_0_EDX_ARCH_CAPABILITIES unmigratable, per Paolo's comment. Signed-off-by: Robert Hoo <robert.hu@linux.intel.com> Message-Id: <1530781798-183214-3-git-send-email-robert.hu@linux.intel.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
* i386: Add new MSR indices for IA32_PRED_CMD and IA32_ARCH_CAPABILITIESRobert Hoo2018-08-161-0/+2
| | | | | | | | | | | | | IA32_PRED_CMD MSR gives software a way to issue commands that affect the state of indirect branch predictors. Enumerated by CPUID.(EAX=7H,ECX=0):EDX[26]. IA32_ARCH_CAPABILITIES MSR enumerates architectural features of RDCL_NO and IBRS_ALL. Enumerated by CPUID.(EAX=07H, ECX=0):EDX[29]. https://software.intel.com/sites/default/files/managed/c5/63/336996-Speculative-Execution-Side-Channel-Mitigations.pdf Signed-off-by: Robert Hoo <robert.hu@linux.intel.com> Message-Id: <1530781798-183214-2-git-send-email-robert.hu@linux.intel.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
* i386: do not migrate MSR_SMI_COUNT on machine types <2.12Paolo Bonzini2018-07-301-0/+1
| | | | | | | | MSR_SMI_COUNT started being migrated in QEMU 2.12. Do not migrate it on older machine types, or the subsection causes a load failure for guests that use SMM. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
* i386: Rename enum CacheType membersEduardo Habkost2018-07-231-2/+2
| | | | | | | | | | | | | | | Rename DCACHE to DATA_CACHE and ICACHE to INSTRUCTION_CACHE. This avoids conflict with Linux asm/cachectl.h macros and fixes build failure on mips hosts. Reported-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com> Message-Id: <20180717194010.30096-1-ehabkost@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Acked-by: Aleksandar Markovic <amarkovic@wavecomp.com> Reviewed-by: Babu Moger <babu.moger@amd.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
* target-i386: Add NPT supportJan Kiszka2018-07-021-0/+6
| | | | | | | | | | | | | | | | | | | This implements NPT suport for SVM by hooking into x86_cpu_handle_mmu_fault where it reads the stage-1 page table. Whether we need to perform this 2nd stage translation, and how, is decided during vmrun and stored in hflags2, along with nested_cr3 and nested_pg_mode. As get_hphys performs a direct cpu_vmexit in case of NPT faults, we need retaddr in that function. To avoid changing the signature of cpu_handle_mmu_fault, this passes the value from tlb_fill to get_hphys via the CPU state. This was tested successfully via the Jailhouse hypervisor. Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Message-Id: <567473a0-6005-5843-4c73-951f476085ca@web.de> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
* i386/kvm: add support for Hyper-V TLB flushVitaly Kuznetsov2018-07-021-0/+1
| | | | | | | | | | | | | | Add support for Hyper-V TLB flush which recently got added to KVM. Just like regular Hyper-V we announce HV_EX_PROCESSOR_MASKS_RECOMMENDED regardless of how many vCPUs we have. Windows is 'smart' and uses less expensive non-EX Hypercall whenever possible (when it wants to flush TLB for all vCPUs or the maximum vCPU index in the vCPU set requires flushing is less than 64). Signed-off-by: Vitaly Kuznetsov <vkuznets@redhat.com> Message-Id: <20180610184927.19309-1-vkuznets@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
* i386/cpu: make -cpu host support monitor/mwaitMichael S. Tsirkin2018-06-291-0/+9
| | | | | | | | | | | | | When guest CPU PM is enabled, and with -cpu host, expose the host CPU MWAIT leaf in the CPUID so guest can make good PM decisions. Note: the result is 100% CPU utilization reported by host as host no longer knows that the CPU is halted. Signed-off-by: Michael S. Tsirkin <mst@redhat.com> Reviewed-by: Eduardo Habkost <ehabkost@redhat.com> Message-Id: <20180622192148.178309-3-mst@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
* target-i386: Mark cpu_vmexit noreturnJan Kiszka2018-06-281-2/+2
| | | | | | | | | It calls cpu_loop_exit in system emulation mode (and should never be called in user emulation mode). Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Message-Id: <6f4d44ffde55d074cbceb48309c1678600abad2f.1522769774.git.jan.kiszka@web.de> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
* i386: Clean up cache CPUID codeEduardo Habkost2018-06-081-5/+9
| | | | | | | | | | | | | Always initialize CPUCaches structs with cache information, even if legacy_cache=true. Use different CPUCaches struct for CPUID[2], CPUID[4], and the AMD CPUID leaves. This will simplify a lot the logic inside cpu_x86_cpuid(). Signed-off-by: Eduardo Habkost <ehabkost@redhat.com> Signed-off-by: Babu Moger <babu.moger@amd.com> Message-Id: <1527176614-26271-2-git-send-email-babu.moger@amd.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
* x86/cpu: use standard-headers/asm-x86.kvm_para.hMichael S. Tsirkin2018-05-231-2/+0Star
| | | | | | | | Switch to the header we imported from Linux, this allows us to drop a hack in kvm_i386.h. More code will be dropped in the next patch. Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
* i386: Define the Virt SSBD MSR and handling of it (CVE-2018-3639)Konrad Rzeszutek Wilk2018-05-211-0/+2
| | | | | | | | | | | | | | | | | | | "Some AMD processors only support a non-architectural means of enabling speculative store bypass disable (SSBD). To allow a simplified view of this to a guest, an architectural definition has been created through a new CPUID bit, 0x80000008_EBX[25], and a new MSR, 0xc001011f. With this, a hypervisor can virtualize the existence of this definition and provide an architectural method for using SSBD to a guest. Add the new CPUID feature, the new MSR and update the existing SSBD support to use this MSR when present." (from x86/speculation: Add virtualized speculative store bypass disable support in Linux). Signed-off-by: Konrad Rzeszutek Wilk <konrad.wilk@oracle.com> Reviewed-by: Daniel P. Berrangé <berrange@redhat.com> Signed-off-by: Daniel P. Berrangé <berrange@redhat.com> Message-Id: <20180521215424.13520-4-berrange@redhat.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
* i386: define the 'ssbd' CPUID feature bit (CVE-2018-3639)Daniel P. Berrangé2018-05-211-0/+1
| | | | | | | | | | | | New microcode introduces the "Speculative Store Bypass Disable" CPUID feature bit. This needs to be exposed to guest OS to allow them to protect against CVE-2018-3639. Signed-off-by: Daniel P. Berrangé <berrange@redhat.com> Reviewed-by: Konrad Rzeszutek Wilk <konrad.wilk@oracle.com> Signed-off-by: Konrad Rzeszutek Wilk <konrad.wilk@oracle.com> Message-Id: <20180521215424.13520-2-berrange@redhat.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
* i386: Add new property to control cache infoBabu Moger2018-05-151-0/+5
| | | | | | | | | | | | | | | | The property legacy-cache will be used to control the cache information. If user passes "-cpu legacy-cache" then older information will be displayed even if the hardware supports new information. Otherwise use the statically loaded cache definitions if available. Renamed the previous cache structures to legacy_*. If there is any change in the cache information, then it needs to be initialized in builtin_x86_defs. Signed-off-by: Babu Moger <babu.moger@amd.com> Tested-by: Geoffrey McRae <geoff@hostfission.com> Message-Id: <20180514164156.27034-3-babu.moger@amd.com> Reviewed-by: Eduardo Habkost <ehabkost@redhat.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
* i386: Add cache information in X86CPUDefinitionBabu Moger2018-05-151-0/+7
| | | | | | | | | | Add cache information in X86CPUDefinition and CPUX86State. Signed-off-by: Babu Moger <babu.moger@amd.com> Tested-by: Geoffrey McRae <geoff@hostfission.com> Reviewed-by: Eduardo Habkost <ehabkost@redhat.com> Message-Id: <20180510204148.11687-3-babu.moger@amd.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
* i386: Helpers to encode cache information consistentlyEduardo Habkost2018-05-151-0/+53
| | | | | | | | | | | | | | | | | | Instead of having a collection of macros that need to be used in complex expressions to build CPUID data, define a CPUCacheInfo struct that can hold information about a given cache. Helper functions will take a CPUCacheInfo struct as input to encode CPUID leaves for a cache. This will help us ensure consistency between cache information CPUID leaves, and make the existing inconsistencies in CPUID info more visible. Signed-off-by: Eduardo Habkost <ehabkost@redhat.com> Signed-off-by: Babu Moger <babu.moger@amd.com> Tested-by: Geoffrey McRae <geoff@hostfission.com> Message-Id: <20180510204148.11687-2-babu.moger@amd.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
* x86/cpu: Enable CLDEMOTE(Demote Cache Line) cpu featureJingqi Liu2018-05-151-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | The CLDEMOTE instruction hints to hardware that the cache line that contains the linear address should be moved("demoted") from the cache(s) closest to the processor core to a level more distant from the processor core. This may accelerate subsequent accesses to the line by other cores in the same coherence domain, especially if the line was written by the core that demotes the line. Intel Snow Ridge has added new cpu feature, CLDEMOTE. The new cpu feature needs to be exposed to guest VM. The bit definition: CPUID.(EAX=7,ECX=0):ECX[bit 25] CLDEMOTE The release document ref below link: https://software.intel.com/sites/default/files/managed/c5/15/\ architecture-instruction-set-extensions-programming-reference.pdf Signed-off-by: Jingqi Liu <jingqi.liu@intel.com> Message-Id: <1525406253-54846-1-git-send-email-jingqi.liu@intel.com> Reviewed-by: Eduardo Habkost <ehabkost@redhat.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
* i386/kvm: add support for Hyper-V reenlightenment MSRsVitaly Kuznetsov2018-05-111-0/+4
| | | | | | | | | | | KVM recently gained support for Hyper-V Reenlightenment MSRs which are required to make KVM-on-Hyper-V enable TSC page clocksource to its guests when INVTSC is not passed to it (and it is not passed by default in Qemu as it effectively blocks migration). Signed-off-by: Vitaly Kuznetsov <vkuznets@redhat.com> Message-Id: <20180411115036.31832-2-vkuznets@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
* i386/hyperv: add hv-frequencies cpu propertyRoman Kagan2018-04-091-0/+1
| | | | | | | | | | | | | | | | | | | | In order to guarantee compatibility on migration, QEMU should have complete control over the features it announces to the guest via CPUID. However, the availability of Hyper-V frequency MSRs (HV_X64_MSR_TSC_FREQUENCY and HV_X64_MSR_APIC_FREQUENCY) depends solely on the support for them in the underlying KVM. Introduce "hv-frequencies" cpu property (off by default) which gives QEMU full control over whether these MSRs are announced. While at this, drop the redundant check of the cpu tsc frequency, and decouple this feature from hv-time. Signed-off-by: Roman Kagan <rkagan@virtuozzo.com> Reviewed-by: Eduardo Habkost <ehabkost@redhat.com> Message-Id: <20180330170209.20627-2-rkagan@virtuozzo.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
* cpu: get rid of unused cpu_init() definesIgor Mammedov2018-03-191-2/+0Star
| | | | | | | | | | | cpu_init(cpu_model) were replaced by cpu_create(cpu_type) so no users are left, remove it. Signed-off-by: Igor Mammedov <imammedo@redhat.com> Acked-by: David Gibson <david@gibson.dropbear.id.au> (ppc) Reviewed-by: Eduardo Habkost <ehabkost@redhat.com> Message-Id: <1518000027-274608-6-git-send-email-imammedo@redhat.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
* cpu: add CPU_RESOLVING_TYPE macroIgor Mammedov2018-03-191-0/+1
| | | | | | | | | | | | | | | | | | it will be used for providing to cpu name resolving class for parsing cpu model for system and user emulation code. Along with change add target to null-machine tests, so that when switch to CPU_RESOLVING_TYPE happens, it would ensure that null-machine usecase still works. Signed-off-by: Igor Mammedov <imammedo@redhat.com> Reviewed-by: Laurent Vivier <laurent@vivier.eu> (m68k) Acked-by: David Gibson <david@gibson.dropbear.id.au> (ppc) Acked-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> (tricore) Message-Id: <1518000027-274608-4-git-send-email-imammedo@redhat.com> Reviewed-by: Eduardo Habkost <ehabkost@redhat.com> [ehabkost: Added macro to riscv too] Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
* Merge remote-tracking branch 'remotes/bonzini/tags/for-upstream-sev' into ↵Peter Maydell2018-03-151-0/+3
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | staging * Migrate MSR_SMI_COUNT (Liran) * Update kernel headers (Gerd, myself) * SEV support (Brijesh) I have not tested non-x86 compilation, but I reordered the SEV patches so that all non-x86-specific changes go first to catch any possible issues (which weren't there anyway :)). # gpg: Signature made Tue 13 Mar 2018 16:37:06 GMT # gpg: using RSA key BFFBD25F78C7AE83 # gpg: Good signature from "Paolo Bonzini <bonzini@gnu.org>" # gpg: aka "Paolo Bonzini <pbonzini@redhat.com>" # Primary key fingerprint: 46F5 9FBD 57D6 12E7 BFD4 E2F7 7E15 100C CD36 69B1 # Subkey fingerprint: F133 3857 4B66 2389 866C 7682 BFFB D25F 78C7 AE83 * remotes/bonzini/tags/for-upstream-sev: (22 commits) sev/i386: add sev_get_capabilities() sev/i386: qmp: add query-sev-capabilities command sev/i386: qmp: add query-sev-launch-measure command sev/i386: hmp: add 'info sev' command cpu/i386: populate CPUID 0x8000_001F when SEV is active sev/i386: add migration blocker sev/i386: finalize the SEV guest launch flow sev/i386: add support to LAUNCH_MEASURE command target/i386: encrypt bios rom sev/i386: add command to encrypt guest memory region sev/i386: add command to create launch memory encryption context sev/i386: register the guest memory range which may contain encrypted data sev/i386: add command to initialize the memory encryption context include: add psp-sev.h header file sev/i386: qmp: add query-sev command target/i386: add Secure Encrypted Virtualization (SEV) object kvm: introduce memory encryption APIs kvm: add memory encryption context docs: add AMD Secure Encrypted Virtualization (SEV) machine: add memory-encryption option ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * KVM: x86: Add support for save/load MSR_SMI_COUNTLiran Alon2018-03-131-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This MSR returns the number of #SMIs that occurred on CPU since boot. KVM commit 52797bf9a875 ("KVM: x86: Add emulation of MSR_SMI_COUNT") introduced support for emulating this MSR. This commit adds support for QEMU to save/load this MSR for migration purposes. Signed-off-by: Liran Alon <liran.alon@oracle.com> Reviewed-by: Konrad Rzeszutek Wilk <konrad.wilk@oracle.com> Signed-off-by: Konrad Rzeszutek Wilk <konrad.wilk@oracle.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
* | i386: Add support to get/set/migrate Intel Processor Trace featureChao Peng2018-03-121-0/+22
| | | | | | | | | | | | | | | | | | | | Add Intel Processor Trace related definition. It also add corresponding part to kvm_get/set_msr and vmstate. Signed-off-by: Chao Peng <chao.p.peng@linux.intel.com> Signed-off-by: Luwei Kang <luwei.kang@intel.com> Message-Id: <1520182116-16485-2-git-send-email-luwei.kang@intel.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
* | i386: Add Intel Processor Trace feature supportChao Peng2018-03-121-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Expose Intel Processor Trace feature to guest. To make Intel PT live migration safe and get same CPUID information with same CPU model on diffrent host. CPUID[14] is constant in this patch. Intel PT use EPT is first supported in IceLake, the CPUID[14] get on this machine as default value. Intel PT would be disabled if any machine don't support this minial feature list. Signed-off-by: Chao Peng <chao.p.peng@linux.intel.com> Signed-off-by: Luwei Kang <luwei.kang@intel.com> Message-Id: <1520182116-16485-1-git-send-email-luwei.kang@intel.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
* | target-i386: add KVM_HINTS_DEDICATED performance hintWanpeng Li2018-03-121-0/+3
|/ | | | | | | | | | | | | | Add KVM_HINTS_DEDICATED performance hint, guest checks this feature bit to determine if they run on dedicated vCPUs, allowing optimizations such as usage of qspinlocks. Cc: Paolo Bonzini <pbonzini@redhat.com> Cc: Radim Krčmář <rkrcmar@redhat.com> Cc: Eduardo Habkost <ehabkost@redhat.com> Signed-off-by: Wanpeng Li <wanpengli@tencent.com> Message-Id: <1518185725-69559-1-git-send-email-wanpengli@tencent.com> [ehabkost: Renamed property to kvm-hint-dedicated] Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
* target/*/cpu.h: remove softfloat.hAlex Bennée2018-02-211-4/+0Star
| | | | | | | | | | | | | | | | | As cpu.h is another typically widely included file which doesn't need full access to the softfloat API we can remove the includes from here as well. Where they do need types it's typically for float_status and the rounding modes so we move that to softfloat-types.h as well. As a result of not having softfloat in every cpu.h call we now need to add it to various helpers that do need the full softfloat.h definitions. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> [For PPC parts] Acked-by: David Gibson <david@gibson.dropbear.id.au>
* accel/tcg: add size paremeter in tlb_fill()Laurent Vivier2018-01-251-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | The MC68040 MMU provides the size of the access that triggers the page fault. This size is set in the Special Status Word which is written in the stack frame of the access fault exception. So we need the size in m68k_cpu_unassigned_access() and m68k_cpu_handle_mmu_fault(). To be able to do that, this patch modifies the prototype of handle_mmu_fault handler, tlb_fill() and probe_write(). do_unassigned_access() already includes a size parameter. This patch also updates handle_mmu_fault handlers and tlb_fill() of all targets (only parameter, no code change). Signed-off-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: David Hildenbrand <david@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20180118193846.24953-2-laurent@vivier.eu>
* i386: Add FEAT_8000_0008_EBX CPUID feature wordEduardo Habkost2018-01-181-0/+3
| | | | | | | | | | Add the new feature word and the "ibpb" feature flag. Based on a patch by Paolo Bonzini. Signed-off-by: Eduardo Habkost <ehabkost@redhat.com> Message-Id: <20180109154519.25634-5-ehabkost@redhat.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
* i386: Add spec-ctrl CPUID bitEduardo Habkost2018-01-181-0/+1
| | | | | | | | Add the feature name and a CPUID_7_0_EDX_SPEC_CTRL macro. Signed-off-by: Eduardo Habkost <ehabkost@redhat.com> Message-Id: <20180109154519.25634-4-ehabkost@redhat.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
* i386: Add support for SPEC_CTRL MSRPaolo Bonzini2018-01-181-0/+3
| | | | | | Signed-off-by: Eduardo Habkost <ehabkost@redhat.com> Message-Id: <20180109154519.25634-3-ehabkost@redhat.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
* target/i386: move hflags update code to a functionTao Wu2018-01-161-0/+2
| | | | | | | | We will share the same code for hax/kvm. Signed-off-by: Tao Wu <lepton@google.com> Message-Id: <20180110195056.85403-1-lepton@google.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
* i386: hvf: unify register enums between HVF and the restPaolo Bonzini2017-12-221-24/+38
| | | | Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
generated by cgit v1.2.3-55-g7522 (git 2.39.0) at 2025-02-04 02:53:26 +0100