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* target/microblaze: Rename mmu structsRichard Henderson2020-09-071-1/+1
| | | | | | | | | | | Introduce typedefs and follow CODING_STYLE for naming. Rename struct microblaze_mmu to MicroBlazeMMU. Rename struct microblaze_mmu_lookup to MicroBlazeMMULookup. Tested-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* target/microblaze: Renumber D_FLAGRichard Henderson2020-09-071-1/+1
| | | | | | | | | | ESS[DS] is bit 19 in the manual, but the manual uses big-endian bit numbering. This corresponds to bit 12 in little-endian numbering. Let the comment about matching the ESR be true by renumbering it. Tested-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* target/microblaze: Collected fixes for env->iflagsRichard Henderson2020-09-071-1/+2
| | | | | | | | | | | | | | | | | | | There are several problems here that can result in soft lockup, depending on exactly where an interrupt or exception is delivered: Include BIMM_FLAG in IFLAGS_TB_MASK, since it needs to follow D_FLAG. Ensure that iflags is 0 when entering an interrupt/exception handler. Add mb_cpu_synchronize_from_tb to restore iflags from tb->flags. The change to t_sync_flags is cosmetic, but makes the code clearer. This fixes the reported regression in acceptance/replay_kernel.py. Fixes: 683a247ed7a4 ("target/microblaze: Store "current" iflags in insn_start") Tested-by: Thomas Huth <thuth@redhat.com> Reported-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20200904190842.2282109-2-richard.henderson@linaro.org> Signed-off-by: Thomas Huth <thuth@redhat.com>
* target/microblaze: Reduce linux-user address space to 32-bitRichard Henderson2020-09-011-1/+1
| | | | | | | | | | User-space programs cannot use the 64-bit lwea/swea instructions. We can improve code generation and runtime by restricting the user-only address space to 32-bit. Tested-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* target/microblaze: Reorganize branchingRichard Henderson2020-09-011-2/+2
| | | | | | | | | | | | | | | Remove the btaken variable, and simplify things by always computing the full branch destination into btarget. This avoids all need for sync_jmpstate(). Retain the direct branch behaviour by remembering the jump destination in jmp_dest, discarding btarget. In the normal case, where the branch delay slot cannot trap (e.g. arithmetic), tcg will remove the computation into btarget, leaving us with just the tcg direct branching at the end. Tested-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* target/microblaze: Convert brk and brki to decodetreeRichard Henderson2020-09-011-1/+1
| | | | | | | | | | | | | | | | | Split these out of the normal branch instructions, as they require special handling. Perform the entire operation inline, instead of raising EXCP_BREAK to do the work in mb_cpu_do_interrupt. This fixes a bug in that brki rd, imm, for imm != 0x18 is not supposed to set MSR_BIP. This fixes a bug in that imm == 0 is the reset vector and 0x18 is the debug vector, and neither should raise a tcg exception in system mode. Introduce EXCP_SYSCALL for microblaze-linux-user. Tested-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* target/microblaze: Use cc->do_unaligned_accessRichard Henderson2020-09-011-1/+9
| | | | | | | | | | | This fixes the problem in which unaligned stores succeeded, but then we raised the exception after modifying memory. Store the ESS for the unaligned data access in the iflags for the insn, so that it can be found during unwind. Tested-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* target/microblaze: Store "current" iflags in insn_startRichard Henderson2020-09-011-0/+2
| | | | | | | | | | | | | | | This data is available during exception unwinding, thus we can restore it from there directly, rather than saving it during the TB. Thus we may remove the t_sync_flags() calls in the load/store operations. Note that these calls were missing from the other places where runtime exceptions may be raised, such as idiv and the floating point operations. Tested-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* target/microblaze: Move bimm to BIMM_FLAGRichard Henderson2020-09-011-2/+2
| | | | | | | | | | | | | It makes sense to keep BIMM with D_FLAG, as they can be written back to iflags at the same time. BIMM_FLAG does not need to be added to IFLAGS_TB_MASK because it does not affect the next TB, only the exception path out of the current TB. Renumber IMM_FLAG, as the value 4 holds no particular significance; pack these two flags at the bottom of the bitfield. Tested-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* target/microblaze: Assert no overlap in flags making up tb_flagsRichard Henderson2020-09-011-2/+7
| | | | | | | | | Create MSR_TB_MASK. Use it in cpu_get_tb_cpu_state, and check that IFLAGS_TB_MASK does not overlap. Tested-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* target/microblaze: Replace MSR_EE_FLAG with MSR_EERichard Henderson2020-09-011-1/+3
| | | | | | | | | | There's no reason to define MSR_EE_FLAG; we can just use the original MSR_EE define. Document the other flags copied into tb_flags with iflag to reserve those bits. Tested-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* target/microblaze: Ensure imm constant is always availableRichard Henderson2020-09-011-1/+1
| | | | | | | | | | | | Include the env->imm value in the TB values when IMM_FLAG is set. This means that we can always reconstruct the complete 32-bit imm. Discard env_imm when its contents can no longer be accessed. Fix user-mode checks for BRK/BRKI, which depend on IMM. Tested-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* target/microblaze: Split out MSR[C] to its own variableRichard Henderson2020-09-011-1/+18
| | | | | | | | | | Having the MSR[C] bit separate will improve arithmetic that operates on the carry bit. Having mb_cpu_read_msr() populate MSR[CC] will prevent the carry copy not matching the carry bit. Tested-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* target/microblaze: Remove helper_debug and env->debugRichard Henderson2020-09-011-1/+0Star
| | | | | | | | This is not used, and seems redundant with -d cpu. Tested-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* target/microblaze: Fix width of EDRRichard Henderson2020-09-011-1/+1
| | | | | | | | | | | The exception data register is only 32-bits wide. Do not use a 64-bit type to represent it. Since cpu_edr is only used during MSR and MTR instructions, we can just as easily use an explicit load and store, so eliminate the variable. Tested-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* target/microblaze: Fix width of BTRRichard Henderson2020-09-011-1/+1
| | | | | | | | | | | The branch target register is only 32-bits wide. Do not use a 64-bit type to represent it. Since cpu_btr is only used during MSR and MTR instructions, we can just as easily use an explicit load and store, so eliminate the variable. Tested-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* target/microblaze: Fix width of FSRRichard Henderson2020-09-011-1/+1
| | | | | | | | | | | The exception status register is only 32-bits wide. Do not use a 64-bit type to represent it. Since cpu_fsr is only used during MSR and MTR instructions, we can just as easily use an explicit load and store, so eliminate the variable. Tested-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* target/microblaze: Fix width of ESRRichard Henderson2020-09-011-1/+1
| | | | | | | | | The exception status register is only 32-bits wide. Do not use a 64-bit type to represent it. Tested-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* target/microblaze: Fix width of MSRRichard Henderson2020-09-011-1/+1
| | | | | | | | | The machine status register is only 32-bits wide. Do not use a 64-bit type to represent it. Tested-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* target/microblaze: Fix width of PC and BTARGETRichard Henderson2020-09-011-2/+2
| | | | | | | | | | The program counter is only 32-bits wide. Do not use a 64-bit type to represent it. Since they are so closely related, fix btarget at the same time. Tested-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* target/microblaze: Split out EDR from env->sregsRichard Henderson2020-09-011-1/+1
| | | | | | | | | Finish eliminating the sregs array in favor of individual members. Does not correct the width of EDR, yet. Tested-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* target/microblaze: Split out BTR from env->sregsRichard Henderson2020-09-011-0/+1
| | | | | | | | | Continue eliminating the sregs array in favor of individual members. Does not correct the width of BTR, yet. Tested-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* target/microblaze: Split out FSR from env->sregsRichard Henderson2020-09-011-0/+1
| | | | | | | | | Continue eliminating the sregs array in favor of individual members. Does not correct the width of FSR, yet. Tested-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* target/microblaze: Split out ESR from env->sregsRichard Henderson2020-09-011-0/+1
| | | | | | | | | Continue eliminating the sregs array in favor of individual members. Does not correct the width of ESR, yet. Tested-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* target/microblaze: Split out EAR from env->sregsRichard Henderson2020-09-011-0/+1
| | | | | | | | Continue eliminating the sregs array in favor of individual members. Tested-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* target/microblaze: Split out MSR from env->sregsRichard Henderson2020-09-011-3/+4
| | | | | | | | | Continue eliminating the sregs array in favor of individual members. Does not correct the width of MSR, yet. Tested-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* target/microblaze: Split out PC from env->sregsRichard Henderson2020-09-011-1/+2
| | | | | | | | | Begin eliminating the sregs array in favor of individual members. Does not correct the width of pc, yet. Tested-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* target/microblaze: Add the pvr-user2 propertyEdgar E. Iglesias2020-04-301-0/+1
| | | | | | | | | Add the pvr-user2 property to control the user-defined PVR1 User2 register. Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Luc Michel <luc.michel@greensocs.com> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
* target/microblaze: Add the pvr-user1 propertyEdgar E. Iglesias2020-04-301-0/+1
| | | | | | | | | Add the pvr-user1 property to control the user-defined PVR0 User1 field. Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Luc Michel <luc.michel@greensocs.com> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
* target/microblaze: Add the unaligned-exceptions propertyEdgar E. Iglesias2020-04-301-0/+1
| | | | | | | | | Add the unaligned-exceptions property to control if the core traps unaligned memory accesses. Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Luc Michel <luc.michel@greensocs.com> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
* target/microblaze: Add the div-zero-exception propertyEdgar E. Iglesias2020-04-301-0/+1
| | | | | | | | | Add the div-zero-exception property to control if the core traps divizions by zero. Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Luc Michel <luc.michel@greensocs.com> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
* target/microblaze: Add the ill-opcode-exception propertyEdgar E. Iglesias2020-04-301-0/+1
| | | | | | | | | Add the ill-opcode-exception property to control if illegal instructions will raise exceptions. Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Luc Michel <luc.michel@greensocs.com> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
* target/microblaze: Add the opcode-0x0-illegal CPU propertyEdgar E. Iglesias2020-04-301-0/+1
| | | | | | | | | Add the opcode-0x0-illegal CPU property to control if the core should trap opcode zero as illegal. Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Luc Michel <luc.michel@greensocs.com> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
* gdbstub: extend GByteArray to read register helpersAlex Bennée2020-03-171-1/+1
| | | | | | | | | | | | | | | Instead of passing a pointer to memory now just extend the GByteArray to all the read register helpers. They can then safely append their data through the normal way. We don't bother with this abstraction for write registers as we have already ensured the buffer being copied from is the correct size. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Acked-by: David Gibson <david@gibson.dropbear.id.au> Reviewed-by: Damien Hedde <damien.hedde@greensocs.com> Message-Id: <20200316172155.971-15-alex.bennee@linaro.org>
* target/microblaze: Remove MMU_MODE{0,1,2}_SUFFIXRichard Henderson2020-01-161-3/+0Star
| | | | | | | | | The functions generated by these macros are unused. Cc: Edgar E. Iglesias <edgar.iglesias@gmail.com> Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* Include qemu-common.h exactly where neededMarkus Armbruster2019-06-121-1/+0Star
| | | | | | | | | | | | | | | | No header includes qemu-common.h after this commit, as prescribed by qemu-common.h's file comment. Signed-off-by: Markus Armbruster <armbru@redhat.com> Message-Id: <20190523143508.25387-5-armbru@redhat.com> [Rebased with conflicts resolved automatically, except for include/hw/arm/xlnx-zynqmp.h hw/arm/nrf51_soc.c hw/arm/msf2-soc.c block/qcow2-refcount.c block/qcow2-cluster.c block/qcow2-cache.c target/arm/cpu.h target/lm32/cpu.h target/m68k/cpu.h target/mips/cpu.h target/moxie/cpu.h target/nios2/cpu.h target/openrisc/cpu.h target/riscv/cpu.h target/tilegx/cpu.h target/tricore/cpu.h target/unicore32/cpu.h target/xtensa/cpu.h; bsd-user/main.c and net/tap-bsd.c fixed up]
* cpu: Remove CPU_COMMONRichard Henderson2019-06-101-2/+0Star
| | | | | | | | | | This macro is now always empty, so remove it. This leaves the entire contents of CPUArchState under the control of the guest architecture. Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* cpu: Introduce CPUNegativeOffsetStateRichard Henderson2019-06-101-2/+3
| | | | | | | | | Nothing in there so far, but all of the plumbing done within the target ArchCPU state. Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* cpu: Move ENV_OFFSET to exec/gen-icount.hRichard Henderson2019-06-101-1/+0Star
| | | | | | | | | Now that we have ArchCPU, we can define this generically, in the one place that needs it. Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* target/microblaze: Use env_cpu, env_archcpuRichard Henderson2019-06-101-20/+15Star
| | | | | | | | | | | | | | Cleanup in the boilerplate that each target must define. Replace mb_env_get_cpu with env_archcpu. The combination CPU(mb_env_get_cpu) should have used ENV_GET_CPU to begin; use env_cpu now. Move cpu_mmu_index below the include of "exec/cpu-all.h", so that the definition of env_archcpu is available. Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* cpu: Replace ENV_GET_CPU with env_cpuRichard Henderson2019-06-101-2/+0Star
| | | | | | | | | Now that we have both ArchCPU and CPUArchState, we can define this generically instead of via macro in each target's cpu.h. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Acked-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* cpu: Define ArchCPURichard Henderson2019-06-101-0/+1
| | | | | | | | For all targets, do this just before including exec/cpu-all.h. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Acked-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* cpu: Define CPUArchState with typedefRichard Henderson2019-06-101-3/+2Star
| | | | | | | | For all targets, do this just before including exec/cpu-all.h. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Acked-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg: Split out target/arch/cpu-param.hRichard Henderson2019-06-101-12/+2Star
| | | | | | | | | | | | | | | | For all targets, into this new file move TARGET_LONG_BITS, TARGET_PAGE_BITS, TARGET_PHYS_ADDR_SPACE_BITS, TARGET_VIRT_ADDR_SPACE_BITS, and NB_MMU_MODES. Include this new file from exec/cpu-defs.h. This now removes the somewhat odd requirement that target/arch/cpu.h defines TARGET_LONG_BITS before including exec/cpu-defs.h, so push the bulk of the includes within target/arch/cpu.h to the top. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Acked-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* target/microblaze: Convert to CPUClass::tlb_fillRichard Henderson2019-05-101-2/+3
| | | | | | Cc: Edgar E. Iglesias <edgar.iglesias@gmail.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* qom/cpu: Simplify how CPUClass:cpu_dump_state() printsMarkus Armbruster2019-04-181-2/+1Star
| | | | | | | | | | | | | | | | | | | | CPUClass method dump_statistics() takes an fprintf()-like callback and a FILE * to pass to it. Most callers pass fprintf() and stderr. log_cpu_state() passes fprintf() and qemu_log_file. hmp_info_registers() passes monitor_fprintf() and the current monitor cast to FILE *. monitor_fprintf() casts it right back, and is otherwise identical to monitor_printf(). The callback gets passed around a lot, which is tiresome. The type-punning around monitor_fprintf() is ugly. Drop the callback, and call qemu_fprintf() instead. Also gets rid of the type-punning, since qemu_fprintf() takes NULL instead of the current monitor cast to FILE *. Signed-off-by: Markus Armbruster <armbru@redhat.com> Reviewed-by: Dr. David Alan Gilbert <dgilbert@redhat.com> Message-Id: <20190417191805.28198-15-armbru@redhat.com>
* target/microblaze: Add props enabling exceptions on failed bus accessesEdgar E. Iglesias2019-01-221-0/+2
| | | | | | | | | Add MicroBlaze CPU properties to enable exceptions on failed bus accesses. Reviewed-by: Luc Michel <luc.michel@greensocs.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
* target/microblaze: Switch to transaction_failed hookPeter Maydell2019-01-221-3/+4
| | | | | | | | | | | | | | | | | Switch the microblaze target from the old unassigned_access hook to the transaction_failed hook. The notable difference is that rather than it being called for all physical memory accesses which fail (including those made by DMA devices or by the gdbstub), it is only called for those made by the CPU via its MMU. For microblaze this makes no difference because none of the target CPU code needs to make loads or stores by physical address. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> [EI: Add space in qemu_log()] Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
* target-microblaze: Consolidate MMU enabled checksEdgar E. Iglesias2018-05-291-1/+3
| | | | | | | | | | Consolidate MMU enabled checks to cpu_mmu_index(). No functional changes. Suggested-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
* target-microblaze: cpu_mmu_index: Fixup indentationEdgar E. Iglesias2018-05-291-7/+9
| | | | | | | | | | Fixup the indentation of cpu_mmu_index in preparation for future edits. No functional changes. Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
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