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* target/microblaze: Convert dec_fpu to decodetreeRichard Henderson2020-09-012-111/+60Star
| | | | | | | | | | The current dec_check_fpuv2 test, raising an FPU exception for an unimplemented instruction, appears to be contradictory to the manual. Drop that and merely check use_fpu == 2. Tested-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* target/microblaze: Convert dec_imm to decodetreeRichard Henderson2020-09-012-9/+11
| | | | | | Tested-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* target/microblaze: Convert dec_barrel to decodetreeRichard Henderson2020-09-012-59/+86
| | | | | | Tested-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* target/microblaze: Convert dec_bit to decodetreeRichard Henderson2020-09-012-73/+95
| | | | | | Tested-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* target/microblaze: Unwind properly when raising divide-by-zeroRichard Henderson2020-09-012-13/+14
| | | | | | | | | Restore the correct pc when raising divide-by-zero. Also, the MSR[DZO] bit is sticky -- it is not cleared with a successful divide. Tested-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* target/microblaze: Convert dec_div to decodetreeRichard Henderson2020-09-012-22/+16Star
| | | | | | Tested-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* target/microblaze: Convert dec_mul to decodetreeRichard Henderson2020-09-012-46/+37Star
| | | | | | Tested-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* target/microblaze: Convert dec_and, dec_or, dec_xor to decodetreeRichard Henderson2020-09-012-30/+28Star
| | | | | | Tested-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* target/microblaze: Convert dec_pattern to decodetreeRichard Henderson2020-09-012-49/+22Star
| | | | | | Tested-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* target/microblaze: Implement cmp and cmpu inlineRichard Henderson2020-09-013-24/+22Star
| | | | | | | | | These are simple enough operations; we do not need to call an out-of-line helper. Tested-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* target/microblaze: Convert dec_sub to decodetreeRichard Henderson2020-09-014-75/+65Star
| | | | | | | | | Use tcg_gen_add2_i32 for computing carry. This removes the last use of helper_carry, so remove that. Tested-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* target/microblaze: Convert dec_add to decodetreeRichard Henderson2020-09-012-41/+176
| | | | | | | | | | | | | Adds infrastrucure for translation of instructions, which could not be added before their first use. Cache a temporary which represents r0 as the immediate 0 value, or a sink. Move the special case of opcode_0_illegal from old_decode() into decodetree as well, lest this get interpreted as add. Tested-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* target/microblaze: Add decodetree infrastructureRichard Henderson2020-09-013-2/+30
| | | | | | | | | The new interface is a stub that recognizes no instructions. It falls back to the old decoder for all instructions. Tested-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* target/microblaze: Ensure imm constant is always availableRichard Henderson2020-09-012-46/+67
| | | | | | | | | | | | Include the env->imm value in the TB values when IMM_FLAG is set. This means that we can always reconstruct the complete 32-bit imm. Discard env_imm when its contents can no longer be accessed. Fix user-mode checks for BRK/BRKI, which depend on IMM. Tested-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* target/microblaze: Remove LOG_DISRichard Henderson2020-09-011-77/+1Star
| | | | | | | | | Also remove the related defines, DISAS_MB and DEBUG_DISAS. Rely on print_insn_microblaze. Tested-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* target/microblaze: Remove empty D macrosRichard Henderson2020-09-013-11/+4Star
| | | | | | | | | | This is never used in op_helper.c and translate.c. There are two trivial uses in helper.c which can be improved by always logging MMU_EXCP to CPU_LOG_INT. Tested-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* target/microblaze: Remove DISAS_GNURichard Henderson2020-09-011-1/+0Star
| | | | | | | | This is never used. Tested-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* target/microblaze: Remove SIM_COMPATRichard Henderson2020-09-011-4/+1Star
| | | | | | Tested-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* target/microblaze: Convert to translator_loopRichard Henderson2020-09-011-137/+146
| | | | | | | | Finish the conversion to the generic translator_loop. Tested-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* target/microblaze: Convert to DisasContextBaseRichard Henderson2020-09-011-51/+51
| | | | | | | | | Part one of conversion to the generic translator_loop is to use the DisasContextBase and the members therein. Tested-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* target/microblaze: Check singlestep_enabled in gen_goto_tbRichard Henderson2020-09-011-1/+6
| | | | | | | | Do not use goto_tb if we're single-stepping. Tested-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* target/microblaze: Use DISAS_NORETURNRichard Henderson2020-09-011-10/+7Star
| | | | | | | | | | Both exceptions and gen_goto_tb do not return. Use the official DISAS_NORETURN enumerator for this case. This eliminates all use of DISAS_TB_JUMP. Tested-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* target/microblaze: Split out MSR[C] to its own variableRichard Henderson2020-09-015-95/+81Star
| | | | | | | | | | Having the MSR[C] bit separate will improve arithmetic that operates on the carry bit. Having mb_cpu_read_msr() populate MSR[CC] will prevent the carry copy not matching the carry bit. Tested-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* target/microblaze: Tidy mb_tcg_initRichard Henderson2020-09-011-37/+29Star
| | | | | | | | | | All of the tcg globals can be recorded in the same table. Drop the "r" prefix from "rpc" and "rmsr". Obviates the need for regnames[], which was incorrectly not const. Tested-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* target/microblaze: Rename env_* tcg variables to cpu_*Richard Henderson2020-09-011-27/+27
| | | | | | | | | This is cpu_imm, cpu_btaken, cpu_iflags, cpu_res_addr and cpu_res_val. It is standard for these file-scope globals to begin with cpu_*. Tested-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* target/microblaze: Remove helper_debug and env->debugRichard Henderson2020-09-014-39/+2Star
| | | | | | | | This is not used, and seems redundant with -d cpu. Tested-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* target/microblaze: Mark raise_exception as noreturnRichard Henderson2020-09-011-1/+1
| | | | | | | | | This will allow tcg to remove any dead code that might follow an exception. Tested-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* target/microblaze: Tidy raising of exceptionsRichard Henderson2020-09-011-25/+37
| | | | | | | | | | | | | | Split out gen_raise_exception which does no cpu state sync. Rename t_gen_raise_exception to gen_raise_exception_sync to emphasize that it does a sync. Create gen_raise_hw_excp to simplify code raising EXCP_HW_EXCP. Since there is now only one use of cpu_esr, perform a store instead and remove the TCG variable. Tested-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* target/microblaze: Remove cpu_earRichard Henderson2020-09-011-8/+15
| | | | | | | | | | Since cpu_ear is only used during MSR and MTR instructions, we can just as easily use an explicit load and store, so eliminate the variable. Tested-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* target/microblaze: Fix width of EDRRichard Henderson2020-09-012-7/+6Star
| | | | | | | | | | | The exception data register is only 32-bits wide. Do not use a 64-bit type to represent it. Since cpu_edr is only used during MSR and MTR instructions, we can just as easily use an explicit load and store, so eliminate the variable. Tested-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* target/microblaze: Fix width of BTRRichard Henderson2020-09-012-8/+6Star
| | | | | | | | | | | The branch target register is only 32-bits wide. Do not use a 64-bit type to represent it. Since cpu_btr is only used during MSR and MTR instructions, we can just as easily use an explicit load and store, so eliminate the variable. Tested-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* target/microblaze: Fix width of FSRRichard Henderson2020-09-012-7/+6Star
| | | | | | | | | | | The exception status register is only 32-bits wide. Do not use a 64-bit type to represent it. Since cpu_fsr is only used during MSR and MTR instructions, we can just as easily use an explicit load and store, so eliminate the variable. Tested-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* target/microblaze: Fix width of ESRRichard Henderson2020-09-014-11/+11
| | | | | | | | | The exception status register is only 32-bits wide. Do not use a 64-bit type to represent it. Tested-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* target/microblaze: Fix width of MSRRichard Henderson2020-09-014-29/+17Star
| | | | | | | | | The machine status register is only 32-bits wide. Do not use a 64-bit type to represent it. Tested-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* target/microblaze: Fix width of PC and BTARGETRichard Henderson2020-09-015-63/+43Star
| | | | | | | | | | The program counter is only 32-bits wide. Do not use a 64-bit type to represent it. Since they are so closely related, fix btarget at the same time. Tested-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* target/microblaze: Split the cpu_SR arrayRichard Henderson2020-09-011-41/+65
| | | | | | | | | Similar to splitting the sregs array, this will allow further fixes and cleanups. Tested-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* target/microblaze: Split out EDR from env->sregsRichard Henderson2020-09-013-16/+6Star
| | | | | | | | | Finish eliminating the sregs array in favor of individual members. Does not correct the width of EDR, yet. Tested-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* target/microblaze: Split out BTR from env->sregsRichard Henderson2020-09-014-6/+9
| | | | | | | | | Continue eliminating the sregs array in favor of individual members. Does not correct the width of BTR, yet. Tested-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* target/microblaze: Split out FSR from env->sregsRichard Henderson2020-09-014-8/+11
| | | | | | | | | Continue eliminating the sregs array in favor of individual members. Does not correct the width of FSR, yet. Tested-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* target/microblaze: Split out ESR from env->sregsRichard Henderson2020-09-015-22/+24
| | | | | | | | | Continue eliminating the sregs array in favor of individual members. Does not correct the width of ESR, yet. Tested-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* target/microblaze: Split out EAR from env->sregsRichard Henderson2020-09-015-11/+14
| | | | | | | | Continue eliminating the sregs array in favor of individual members. Tested-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* target/microblaze: Split out MSR from env->sregsRichard Henderson2020-09-016-49/+51
| | | | | | | | | Continue eliminating the sregs array in favor of individual members. Does not correct the width of MSR, yet. Tested-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* target/microblaze: Split out PC from env->sregsRichard Henderson2020-09-017-27/+32
| | | | | | | | | Begin eliminating the sregs array in favor of individual members. Does not correct the width of pc, yet. Tested-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* target/microblaze: Tidy gdbstubRichard Henderson2020-09-011-90/+99
| | | | | | | | | | | Use an enumeration for the gdb register mapping. Use one switch statement for the entire dispatch. Drop sreg_map and simply enumerate those cases explicitly. Force r0 to have value 0 and ignore writes. Tested-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* target/microblaze: mbar: Trap sleeps from user-spaceEdgar E. Iglesias2020-08-241-0/+5
| | | | | | | | Trap mbar-sleeps from user-space. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reported-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
* target/microblaze: swx: Use atomic_cmpxchgEdgar E. Iglesias2020-08-241-8/+13
| | | | | | | | Use atomic_cmpxchg to implement the atomic cmpxchg sequence. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
* target/microblaze: mbar: Add support for data-access barriersEdgar E. Iglesias2020-08-241-0/+5
| | | | | | | | Add support for data-access barriers. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
* target/microblaze: mbar: Move LOG_DIS to before sleepEdgar E. Iglesias2020-08-241-1/+2
| | | | | | | | | Move LOG_DIS log to before sleeping handling so that it logs for sleep instructions aswell. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
* target/microblaze: mbar: Transfer dc->rd to mbar_immEdgar E. Iglesias2020-08-241-2/+4
| | | | | | | | | | | Transfer dc->rd to mbar_imm to improve the readability when comparing to the specs. No functional change. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
* meson: targetPaolo Bonzini2020-08-212-3/+14
| | | | | | | | | Similar to hw_arch, each architecture defines two sourceset which are placed in dictionaries target_arch and target_softmmu_arch. These are then picked up from there when building the per-emulator static_library. Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
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