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* target/mips: msa: Split helpers for MULV.<B|H|W|D>Aleksandar Markovic2020-06-151-1/+5
| | | | | | | | Achieves clearer code and slightly better performance. Reviewed-by: Aleksandar Rikalo <aleksandar.rikalo@syrmia.com> Signed-off-by: Aleksandar Markovic <aleksandar.qemu.devel@gmail.com> Message-Id: <20200613152133.8964-15-aleksandar.qemu.devel@gmail.com>
* target/mips: msa: Split helpers for SUBV.<B|H|W|D>Aleksandar Markovic2020-06-151-1/+5
| | | | | | | | Achieves clearer code and slightly better performance. Reviewed-by: Aleksandar Rikalo <aleksandar.rikalo@syrmia.com> Signed-off-by: Aleksandar Markovic <aleksandar.qemu.devel@gmail.com> Message-Id: <20200613152133.8964-14-aleksandar.qemu.devel@gmail.com>
* target/mips: msa: Split helpers for SUBSUU_S.<B|H|W|D>Aleksandar Markovic2020-06-151-1/+5
| | | | | | | | Achieves clearer code and slightly better performance. Reviewed-by: Aleksandar Rikalo <aleksandar.rikalo@syrmia.com> Signed-off-by: Aleksandar Markovic <aleksandar.qemu.devel@gmail.com> Message-Id: <20200613152133.8964-13-aleksandar.qemu.devel@gmail.com>
* target/mips: msa: Split helpers for SUBSUS_U.<B|H|W|D>Aleksandar Markovic2020-06-151-1/+5
| | | | | | | | Achieves clearer code and slightly better performance. Reviewed-by: Aleksandar Rikalo <aleksandar.rikalo@syrmia.com> Signed-off-by: Aleksandar Markovic <aleksandar.qemu.devel@gmail.com> Message-Id: <20200613152133.8964-12-aleksandar.qemu.devel@gmail.com>
* target/mips: msa: Split helpers for SUBS_U.<B|H|W|D>Aleksandar Markovic2020-06-151-1/+5
| | | | | | | | Achieves clearer code and slightly better performance. Reviewed-by: Aleksandar Rikalo <aleksandar.rikalo@syrmia.com> Signed-off-by: Aleksandar Markovic <aleksandar.qemu.devel@gmail.com> Message-Id: <20200613152133.8964-11-aleksandar.qemu.devel@gmail.com>
* target/mips: msa: Split helpers for SUBS_S.<B|H|W|D>Aleksandar Markovic2020-06-151-1/+5
| | | | | | | | Achieves clearer code and slightly better performance. Reviewed-by: Aleksandar Rikalo <aleksandar.rikalo@syrmia.com> Signed-off-by: Aleksandar Markovic <aleksandar.qemu.devel@gmail.com> Message-Id: <20200613152133.8964-10-aleksandar.qemu.devel@gmail.com>
* target/mips: msa: Split helpers for DOTP_U.<H|W|D>Aleksandar Markovic2020-06-151-1/+3
| | | | | | | | Achieves clearer code and slightly better performance. Reviewed-by: Aleksandar Rikalo <aleksandar.rikalo@syrmia.com> Signed-off-by: Aleksandar Markovic <aleksandar.qemu.devel@gmail.com> Message-Id: <20200613152133.8964-9-aleksandar.qemu.devel@gmail.com>
* target/mips: msa: Split helpers for DOTP_S.<H|W|D>Aleksandar Markovic2020-06-151-1/+4
| | | | | | | | Achieves clearer code and slightly better performance. Reviewed-by: Aleksandar Rikalo <aleksandar.rikalo@syrmia.com> Signed-off-by: Aleksandar Markovic <aleksandar.qemu.devel@gmail.com> Message-Id: <20200613152133.8964-8-aleksandar.qemu.devel@gmail.com>
* target/mips: msa: Split helpers for DPSUB_U.<H|W|D>Aleksandar Markovic2020-06-151-1/+3
| | | | | | | | Achieves clearer code and slightly better performance. Reviewed-by: Aleksandar Rikalo <aleksandar.rikalo@syrmia.com> Signed-off-by: Aleksandar Markovic <aleksandar.qemu.devel@gmail.com> Message-Id: <20200613152133.8964-7-aleksandar.qemu.devel@gmail.com>
* target/mips: msa: Split helpers for DPSUB_S.<H|W|D>Aleksandar Markovic2020-06-151-1/+3
| | | | | | | | Achieves clearer code and slightly better performance. Reviewed-by: Aleksandar Rikalo <aleksandar.rikalo@syrmia.com> Signed-off-by: Aleksandar Markovic <aleksandar.qemu.devel@gmail.com> Message-Id: <20200613152133.8964-6-aleksandar.qemu.devel@gmail.com>
* target/mips: msa: Split helpers for DPADD_U.<H|W|D>Aleksandar Markovic2020-06-151-1/+3
| | | | | | | | Achieves clearer code and slightly better performance. Reviewed-by: Aleksandar Rikalo <aleksandar.rikalo@syrmia.com> Signed-off-by: Aleksandar Markovic <aleksandar.qemu.devel@gmail.com> Message-Id: <20200613152133.8964-5-aleksandar.qemu.devel@gmail.com>
* target/mips: msa: Split helpers for DPADD_S.<H|W|D>Aleksandar Markovic2020-06-151-1/+3
| | | | | | | | Achieves clearer code and slightly better performance. Reviewed-by: Aleksandar Rikalo <aleksandar.rikalo@syrmia.com> Signed-off-by: Aleksandar Markovic <aleksandar.qemu.devel@gmail.com> Message-Id: <20200613152133.8964-4-aleksandar.qemu.devel@gmail.com>
* target/mips: msa: Split helpers for MSUBV.<B|H|W|D>Aleksandar Markovic2020-06-151-1/+5
| | | | | | | | Achieves clearer code and slightly better performance. Reviewed-by: Aleksandar Rikalo <aleksandar.rikalo@syrmia.com> Signed-off-by: Aleksandar Markovic <aleksandar.qemu.devel@gmail.com> Message-Id: <20200613152133.8964-3-aleksandar.qemu.devel@gmail.com>
* target/mips: msa: Split helpers for MADDV.<B|H|W|D>Aleksandar Markovic2020-06-151-1/+5
| | | | | | | | Achieves clearer code and slightly better performance. Reviewed-by: Aleksandar Rikalo <aleksandar.rikalo@syrmia.com> Signed-off-by: Aleksandar Markovic <aleksandar.qemu.devel@gmail.com> Message-Id: <20200613152133.8964-2-aleksandar.qemu.devel@gmail.com>
* target/mips: Add implementation of GINVT instructionYongbok Kim2020-01-291-0/+2
| | | | | | | | | | | | Implement emulation of GINVT instruction. As QEMU doesn't support caches and virtualization, this implementation covers only one instruction (GINVT - Global Invalidate TLB) among all TLB-related MIPS instructions. Reviewed-by: Aleksandar Rikalo <aleksandar.rikalo@rt-rk.com> Signed-off-by: Yongbok Kim <yongbok.kim@mips.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Message-Id: <1579883929-1517-5-git-send-email-aleksandar.markovic@rt-rk.com>
* target/mips: Amend CP0 WatchHi register implementationYongbok Kim2020-01-291-0/+3
| | | | | | | | | | | WatchHi is extended by the field MemoryMapID with the GINVT instruction. The field is accessible by MTHC0/MFHC0 in 32-bit architectures and DMTC0/ DMFC0 in 64-bit architectures. Reviewed-by: Aleksandar Rikalo <aleksandar.rikalo@rt-rk.com> Signed-off-by: Yongbok Kim <yongbok.kim@mips.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Message-Id: <1579883929-1517-4-git-send-email-aleksandar.markovic@rt-rk.com>
* target/mips: msa: Split helpers for ASUB_<S|U>.<B|H|W|D>Aleksandar Markovic2019-10-251-2/+10
| | | | | | | | Achieves clearer code and slightly better performance. Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Reviewed-by: Aleksandar Rikalo <aleksandar.rikalo@rt-rk.com> Message-Id: <1571826227-10583-13-git-send-email-aleksandar.markovic@rt-rk.com>
* target/mips: msa: Split helpers for HSUB_<S|U>.<H|W|D>Aleksandar Markovic2019-10-251-2/+8
| | | | | | | | Achieves clearer code and slightly better performance. Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Reviewed-by: Aleksandar Rikalo <aleksandar.rikalo@rt-rk.com> Message-Id: <1571826227-10583-12-git-send-email-aleksandar.markovic@rt-rk.com>
* target/mips: msa: Split helpers for PCK<EV|OD>.<B|H|W|D>Aleksandar Markovic2019-10-251-2/+9
| | | | | | | | Achieves clearer code and slightly better performance. Reviewed-by: Aleksandar Rikalo <aleksandar.rikalo@rt-rk.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Message-Id: <1571826227-10583-11-git-send-email-aleksandar.markovic@rt-rk.com>
* target/mips: msa: Split helpers for S<LL|RA|RAR|RL|RLR>.<B|H|W|D>Aleksandar Markovic2019-10-251-5/+25
| | | | | | | | Achieves clearer code and slightly better performance. Reviewed-by: Aleksandar Rikalo <aleksandar.rikalo@rt-rk.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Message-Id: <1571826227-10583-10-git-send-email-aleksandar.markovic@rt-rk.com>
* target/mips: msa: Split helpers for HADD_<S|U>.<H|W|D>Aleksandar Markovic2019-10-251-2/+8
| | | | | | | | Achieves clearer code and slightly better performance. Reviewed-by: Aleksandar Rikalo <aleksandar.rikalo@rt-rk.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Message-Id: <1571826227-10583-9-git-send-email-aleksandar.markovic@rt-rk.com>
* target/mips: msa: Split helpers for ADD<_A|S_A|S_S|S_U|V>.<B|H|W|D>Aleksandar Markovic2019-10-251-5/+25
| | | | | | | | Achieves clearer code and slightly better performance. Reviewed-by: Aleksandar Rikalo <aleksandar.rikalo@rt-rk.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Message-Id: <1571826227-10583-8-git-send-email-aleksandar.markovic@rt-rk.com>
* target/mips: msa: Split helpers for ILV<EV|OD|L|R>.<B|H|W|D>Aleksandar Markovic2019-10-251-4/+17
| | | | | | | | Achieves clearer code and slightly better performance. Reviewed-by: Aleksandar Rikalo <aleksandar.rikalo@rt-rk.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Message-Id: <1571826227-10583-7-git-send-email-aleksandar.markovic@rt-rk.com>
* target/mips: msa: Split helpers for <MAX|MIN>_<S|U>.<B|H|W|D>Aleksandar Markovic2019-10-251-4/+16
| | | | | | | | Achieves clearer code and slightly better performance. Reviewed-by: Aleksandar Rikalo <aleksandar.rikalo@rt-rk.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Message-Id: <1571826227-10583-6-git-send-email-aleksandar.markovic@rt-rk.com>
* target/mips: msa: Split helpers for <MAX|MIN>_A.<B|H|W|D>Aleksandar Markovic2019-10-251-2/+9
| | | | | | | | Achieves clearer code and slightly better performance. Reviewed-by: Aleksandar Rikalo <aleksandar.rikalo@rt-rk.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Message-Id: <1571826227-10583-5-git-send-email-aleksandar.markovic@rt-rk.com>
* target/mips: msa: Move helpers for <AND|NOR|OR|XOR>.VAleksandar Markovic2019-10-011-4/+5
| | | | | | | | Cosmetic reorganization. Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com> Message-Id: <1569415572-19635-21-git-send-email-aleksandar.markovic@rt-rk.com>
* target/mips: msa: Simplify and move helper for MOVE.VAleksandar Markovic2019-10-011-1/+1
| | | | | | | | Achieves clearer code and slightly better performance. Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com> Message-Id: <1569415572-19635-20-git-send-email-aleksandar.markovic@rt-rk.com>
* target/mips: msa: Split helpers for MOD_<S|U>.<B|H|W|D>Aleksandar Markovic2019-10-011-2/+10
| | | | | | | | Achieves clearer code and slightly better performance. Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com> Message-Id: <1569415572-19635-19-git-send-email-aleksandar.markovic@rt-rk.com>
* target/mips: msa: Split helpers for DIV_<S|U>.<B|H|W|D>Aleksandar Markovic2019-10-011-2/+10
| | | | | | | | Achieves clearer code and slightly better performance. Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com> Message-Id: <1569415572-19635-18-git-send-email-aleksandar.markovic@rt-rk.com>
* target/mips: msa: Split helpers for CLT_<S|U>.<B|H|W|D>Aleksandar Markovic2019-10-011-2/+10
| | | | | | | | Achieves clearer code and slightly better performance. Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com> Message-Id: <1569415572-19635-17-git-send-email-aleksandar.markovic@rt-rk.com>
* target/mips: msa: Split helpers for CLE_<S|U>.<B|H|W|D>Aleksandar Markovic2019-10-011-2/+10
| | | | | | | | Achieves clearer code and slightly better performance. Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com> Message-Id: <1569415572-19635-16-git-send-email-aleksandar.markovic@rt-rk.com>
* target/mips: msa: Split helpers for CEQ.<B|H|W|D>Aleksandar Markovic2019-10-011-1/+5
| | | | | | | | Achieves clearer code and slightly better performance. Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com> Message-Id: <1569415572-19635-15-git-send-email-aleksandar.markovic@rt-rk.com>
* target/mips: msa: Split helpers for AVER_<S|U>.<B|H|W|D>Aleksandar Markovic2019-10-011-2/+10
| | | | | | | | Achieves clearer code and slightly better performance. Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com> Message-Id: <1569415572-19635-14-git-send-email-aleksandar.markovic@rt-rk.com>
* target/mips: msa: Split helpers for AVE_<S|U>.<B|H|W|D>Aleksandar Markovic2019-10-011-2/+10
| | | | | | | | Achieves clearer code and slightly better performance. Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com> Message-Id: <1569415572-19635-13-git-send-email-aleksandar.markovic@rt-rk.com>
* target/mips: msa: Split helpers for B<CLR|NEG|SEL>.<B|H|W|D>Aleksandar Markovic2019-10-011-3/+15
| | | | | | | | Achieves clearer code and slightly better performance. Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com> Message-Id: <1569415572-19635-12-git-send-email-aleksandar.markovic@rt-rk.com>
* target/mips: msa: Unroll loops and demacro <BMNZ|BMZ|BSEL>.VAleksandar Markovic2019-10-011-3/+4
| | | | | | | | Achieves clearer code and slightly better performance. Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com> Message-Id: <1569415572-19635-11-git-send-email-aleksandar.markovic@rt-rk.com>
* target/mips: msa: Split helpers for BINS<L|R>.<B|H|W|D>Aleksandar Markovic2019-10-011-0/+10
| | | | | | | | Achieves clearer code and slightly better performance. Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com> Message-Id: <1569415572-19635-10-git-send-email-aleksandar.markovic@rt-rk.com>
* target/mips: msa: Split helpers for PCNT.<B|H|W|D>Aleksandar Markovic2019-10-011-1/+5
| | | | | | | | Achieves clearer code and slightly better performance. Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com> Message-Id: <1569415572-19635-9-git-send-email-aleksandar.markovic@rt-rk.com>
* target/mips: msa: Split helpers for <NLOC|NLZC>.<B|H|W|D>Aleksandar Markovic2019-10-011-2/+12
| | | | | | | | Achieves clearer code and slightly better performance. Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com> Message-Id: <1569415572-19635-8-git-send-email-aleksandar.markovic@rt-rk.com>
* Merge remote-tracking branch ↵Peter Maydell2019-05-281-0/+2
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 'remotes/stsquad/tags/pull-testing-next-280519-2' into staging Various testing updates - semihosting re-factor (used in system tests) - aarch64 and alpha system tests - editorconfig tweak for .S - some docker image updates - iotests clean-up (without make check inclusion) # gpg: Signature made Tue 28 May 2019 17:26:34 BST # gpg: using RSA key 6685AE99E75167BCAFC8DF35FBD0DB095A9E2A44 # gpg: Good signature from "Alex Bennée (Master Work Key) <alex.bennee@linaro.org>" [full] # Primary key fingerprint: 6685 AE99 E751 67BC AFC8 DF35 FBD0 DB09 5A9E 2A44 * remotes/stsquad/tags/pull-testing-next-280519-2: (27 commits) tests/qemu-iotests: re-format output to for make check-block tests/qemu-iotests/group: Re-use the "auto" group for tests that can always run Makefile.target: support per-target coverage reports Makefile: include per-target build directories in coverage report Makefile: fix coverage-report reference to BUILD_DIR .travis.yml: enable aarch64-softmmu and alpha-softmmu tcg tests tests/tcg/alpha: add system boot.S tests/tcg/multiarch: expand system memory test to cover more tests/tcg/minilib: support %c format char tests/tcg/multiarch: move the system memory test tests/tcg/aarch64: add system boot.S editorconfig: add settings for .s/.S files tests/tcg/multiarch: add hello world system test tests/tcg/multiarch: add support for multiarch system tests tests/docker: Test more components on the Fedora default image tests/docker: add ubuntu 18.04 MAINTAINERS: update for semihostings new home target/mips: convert UHI_plog to use common semihosting code target/mips: only build mips-semi for softmmu target/arm: correct return values for WRITE/READ in arm-semi ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * target/mips: only build mips-semi for softmmuAlex Bennée2019-05-281-0/+2
| | | | | | | | | | | | | | | | | | | | | | The is_uhi gates all semihosting calls and always returns false for CONFIG_USER_ONLY builds. There is no reason to build and link mips-semi for these builds so lets fix that. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
* | target/mips: Refactor and fix INSERT.<B|H|W|D> instructionsMateja Marjanovic2019-05-261-1/+4
| | | | | | | | | | | | | | | | | | | | | | The old version of the helper for the INSERT.<B|H|W|D> MSA instructions has been replaced with four helpers that don't use switch, and change the endianness of the given index, when executed on a big endian host. Signed-off-by: Mateja Marjanovic <mateja.marjanovic@rt-rk.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com> Message-Id: <1554212605-16457-6-git-send-email-mateja.marjanovic@rt-rk.com>
* | target/mips: Refactor and fix COPY_U.<B|H|W> instructionsMateja Marjanovic2019-05-261-1/+3
| | | | | | | | | | | | | | | | | | | | | | The old version of the helper for the COPY_U.<B|H|W> MSA instructions has been replaced with four helpers that don't use switch, and change the endianness of the given index, when executed on a big endian host. Signed-off-by: Mateja Marjanovic <mateja.marjanovic@rt-rk.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com> Message-Id: <1554212605-16457-5-git-send-email-mateja.marjanovic@rt-rk.com>
* | target/mips: Refactor and fix COPY_S.<B|H|W|D> instructionsMateja Marjanovic2019-05-261-1/+6
|/ | | | | | | | | | | The old version of the helper for the COPY_S.<B|H|W|D> MSA instructions has been replaced with four helpers that don't use switch, and change the endianness of the given index, when executed on a big endian host. Signed-off-by: Mateja Marjanovic <mateja.marjanovic@rt-rk.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com> Message-Id: <1554212605-16457-4-git-send-email-mateja.marjanovic@rt-rk.com>
* target/mips: reimplement SC instruction emulation and use cmpxchgLeon Alrae2019-02-141-2/+0Star
| | | | | | | | | | | | | | Completely rewrite conditional stores handling. Use cmpxchg. This eliminates need for separate implementations of SC instruction emulation for user and system emulation. Signed-off-by: Leon Alrae <leon.alrae@imgtec.com> Signed-off-by: Miodrag Dinic <miodrag.dinic@imgtec.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Acked-by: Alex Bennée <alex.bennee@linaro.org> Tested-by: Emilio G. Cota <cota@braap.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
* target/mips: Provide R/W access to SAARI and SAAR CP0 registersYongbok Kim2019-01-181-0/+6
| | | | | | | | Provide R/W access to SAARI and SAAR CP0 registers. Reviewed-by: Stefan Markovic <smarkovic@wavecomp.com> Signed-off-by: Yongbok Kim <yongbok.kim@mips.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
* target/mips: Add CP0 PWCtl registerYongbok Kim2018-10-181-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | Add PWCtl register (CP0 Register 5, Select 6). The PWCtl register configures hardware page table walking for TLB refills. This register is required for the hardware page walker feature. It exists only if Config3 PW bit is set to 1. It contains following fields: PWEn (31) - Hardware Page Table walker enable PWDirExt (30) - If 1, 4-th level implemented (MIPS64 only) XK (28) - If 1, walker handles xkseg (MIPS64 only) XS (27) - If 1, walker handles xsseg (MIPS64 only) XU (26) - If 1, walker handles xuseg (MIPS64 only) DPH (7) - Dual Page format of Huge Page support HugePg (6) - Huge Page PTE supported in Directory levels PSn (5..0) - Bit position of PTEvld in Huge Page PTE Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: Yongbok Kim <yongbok.kim@mips.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
* target/mips: Add CP0 PWSize registerYongbok Kim2018-10-181-0/+1
| | | | | | | | | | | | | | | | | | | | | | Add PWSize register (CP0 Register 5, Select 7). The PWSize register configures hardware page table walking for TLB refills. This register is required for the hardware page walker feature. It exists only if Config3 PW bit is set to 1. It contains following fields: BDW (37..32) Base Directory index width (MIPS64 only) GDW (29..24) Global Directory index width UDW (23..18) Upper Directory index width MDW (17..12) Middle Directory index width PTW (11..6 ) Page Table index width PTEW ( 5..0 ) Left shift applied to the Page Table index Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: Yongbok Kim <yongbok.kim@mips.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
* target/mips: Add CP0 PWField registerYongbok Kim2018-10-181-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add PWField register (CP0 Register 5, Select 6). The PWField register configures hardware page table walking for TLB refills. This register is required for the hardware page walker feature. It exists only if Config3 PW bit is set to 1. It contains following fields: MIPS64: BDI (37..32) - Base Directory index GDI (29..24) - Global Directory index UDI (23..18) - Upper Directory index MDI (17..12) - Middle Directory index PTI (11..6 ) - Page Table index PTEI ( 5..0 ) - Page Table Entry shift MIPS32: GDW (29..24) - Global Directory index UDW (23..18) - Upper Directory index MDW (17..12) - Middle Directory index PTW (11..6 ) - Page Table index PTEW ( 5..0 ) - Page Table Entry shift Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: Yongbok Kim <yongbok.kim@mips.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
* target/mips: Implement emulation of nanoMIPS ROTX instructionMatthew Fortune2018-08-241-0/+2
| | | | | | | | | | | | Added a helper for ROTX based on the pseudocode from the architecture spec. This instraction was not present in previous MIPS instruction sets. Signed-off-by: Yongbok Kim <yongbok.kim@mips.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: Stefan Markovic <smarkovic@wavecomp.com> Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
generated by cgit v1.2.3-55-g7522 (git 2.39.0) at 2025-01-30 05:24:56 +0100