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* target/mips: Provide R/W access to SAARI and SAAR CP0 registersYongbok Kim2019-01-181-0/+1
* target/mips: Implement hardware page table walker for MIPS32Yongbok Kim2018-10-181-0/+1
* target/mips: Improve DSP R2/R3-related namingStefan Markovic2018-10-181-11/+19
* target/mips: Add availability control for DSP R3 ASEStefan Markovic2018-10-181-3/+8
* target/mips: Increase 'supported ISAs/ASEs' flag holder sizePhilippe Mathieu-Daudé2018-10-181-1/+1
* accel/tcg: add size paremeter in tlb_fill()Laurent Vivier2018-01-251-1/+1
* mips: MIPSCPU model subclassesIgor Mammedov2017-09-211-0/+59
* mips: split cpu_mips_realize_env() out of cpu_mips_init()Philippe Mathieu-Daudé2017-09-211-0/+1
* mips: introduce internal.h and cleanup cpu.hPhilippe Mathieu-Daudé2017-09-211-0/+362