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| * target/mips: Convert MSA 3RF instruction format to decodetree (DF_WORD)Philippe Mathieu-Daudé2021-11-022-176/+76Star
| * target/mips: Convert MSA 3RF instruction format to decodetree (DF_HALF)Philippe Mathieu-Daudé2021-11-022-39/+38Star
| * target/mips: Convert MSA VEC instruction format to decodetreePhilippe Mathieu-Daudé2021-11-022-75/+31Star
| * target/mips: Convert MSA 2R instruction format to decodetreePhilippe Mathieu-Daudé2021-11-022-75/+19Star
| * target/mips: Convert MSA FILL opcode to decodetreePhilippe Mathieu-Daudé2021-11-022-12/+21
| * target/mips: Convert MSA 2RF instruction format to decodetreePhilippe Mathieu-Daudé2021-11-022-85/+53Star
| * target/mips: Convert MSA load/store instruction format to decodetreePhilippe Mathieu-Daudé2021-11-022-59/+36Star
| * target/mips: Convert MSA I8 instruction format to decodetreePhilippe Mathieu-Daudé2021-11-022-56/+27Star
| * target/mips: Convert MSA SHF opcode to decodetreePhilippe Mathieu-Daudé2021-11-022-17/+22
| * target/mips: Convert MSA BIT instruction format to decodetreePhilippe Mathieu-Daudé2021-11-022-97/+101
| * target/mips: Convert MSA I5 instruction format to decodetreePhilippe Mathieu-Daudé2021-11-022-77/+41Star
| * target/mips: Convert MSA LDI opcode to decodetreePhilippe Mathieu-Daudé2021-11-022-9/+21
| * target/mips: Rename sa16 -> sa, bz_df -> bz -> bz_vPhilippe Mathieu-Daudé2021-11-022-18/+17Star
| * target/mips: Use enum definitions from CPUMIPSMSADataFormat enumPhilippe Mathieu-Daudé2021-11-021-3/+3
| * target/mips: Have check_msa_access() return a booleanPhilippe Mathieu-Daudé2021-11-021-7/+18
| * target/mips: Use dup_const() to simplifyPhilippe Mathieu-Daudé2021-11-021-20/+3Star
| * target/mips: Adjust style in msa_translate_init()Philippe Mathieu-Daudé2021-11-021-1/+3
| * target/mips: Fix MSA MSUBV.B opcodePhilippe Mathieu-Daudé2021-11-021-16/+16
| * target/mips: Fix MSA MADDV.B opcodePhilippe Mathieu-Daudé2021-11-021-16/+16
* | target/mips: Make mips_cpu_tlb_fill sysemu onlyRichard Henderson2021-11-024-68/+4Star
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* target/mips: Remove unused TCG temporary in gen_mipsdsp_accinsn()Philippe Mathieu-Daudé2021-10-181-4/+0Star
* target/mips: Fix DEXTRV_S.H DSP opcodePhilippe Mathieu-Daudé2021-10-181-2/+1Star
* target/mips: Use tcg_constant_tl() in gen_compute_compact_branch()Philippe Mathieu-Daudé2021-10-181-3/+1Star
* target/mips: Use explicit extract32() calls in gen_msa_i5()Philippe Mathieu-Daudé2021-10-181-7/+4Star
* target/mips: Use tcg_constant_i32() in gen_msa_3rf()Philippe Mathieu-Daudé2021-10-181-9/+14
* target/mips: Use tcg_constant_i32() in gen_msa_2r()Philippe Mathieu-Daudé2021-10-181-3/+2Star
* target/mips: Use tcg_constant_i32() in gen_msa_2rf()Philippe Mathieu-Daudé2021-10-181-2/+1Star
* target/mips: Use tcg_constant_i32() in gen_msa_elm_df()Philippe Mathieu-Daudé2021-10-181-2/+1Star
* target/mips: Remove unused register from MSA 2R/2RF instruction formatPhilippe Mathieu-Daudé2021-10-181-6/+0Star
* target/mips: Check nanoMIPS DSP MULT[U] accumulator with Release 6Philippe Mathieu-Daudé2021-10-171-0/+6
* target/mips: Drop exit checks for singlestep_enabledRichard Henderson2021-10-161-32/+18Star
* target/mips: Fix single steppingRichard Henderson2021-10-161-9/+16
* target/mips: Use 8-byte memory ops for msa load/storeRichard Henderson2021-10-131-130/+71Star
* target/mips: Use cpu_*_data_ra for msa load/storeRichard Henderson2021-10-131-285/+135Star
* tcg: Rename TCGMemOpIdx to MemOpIdxRichard Henderson2021-10-061-3/+3
* hw/core: Make do_unaligned_access noreturnRichard Henderson2021-09-221-2/+2
* target/mips: Restrict cpu_exec_interrupt() handler to sysemuPhilippe Mathieu-Daudé2021-09-144-25/+21Star
* accel/tcg: Add DisasContextBase argument to translator_ld*Ilya Leoshkevich2021-09-144-9/+9
* target/mips: Replace TARGET_WORDS_BIGENDIAN by cpu_is_bigendian()Philippe Mathieu-Daudé2021-08-253-45/+50
* target/mips: Store CP0_Config0 in DisasContextPhilippe Mathieu-Daudé2021-08-252-0/+2
* target/mips: Replace GET_LMASK64() macro by get_lmask(64) functionPhilippe Mathieu-Daudé2021-08-251-19/+16Star
* target/mips: Replace GET_LMASK() macro by get_lmask(32) functionPhilippe Mathieu-Daudé2021-08-251-11/+21
* target/mips: Call cpu_is_bigendian & inline GET_OFFSET in ld/st helpersPhilippe Mathieu-Daudé2021-08-251-22/+33
* target/mips: Define gen_helper() macros in translate.hPhilippe Mathieu-Daudé2021-08-252-12/+12
* target/mips: Use tcg_constant_i32() in generate_exception_err()Philippe Mathieu-Daudé2021-08-251-5/+2Star
* target/mips: Inline gen_helper_0e0i()Philippe Mathieu-Daudé2021-08-251-6/+2Star
* target/mips: Inline gen_helper_1e1i() call in op_ld_INSN() macrosPhilippe Mathieu-Daudé2021-08-251-5/+1Star
* target/mips: Simplify gen_helper() macros by using tcg_constant_i32()Philippe Mathieu-Daudé2021-08-251-15/+5Star
* target/mips: Use tcg_constant_i32() in gen_helper_0e2i()Philippe Mathieu-Daudé2021-08-251-12/+2Star
* target/mips: Remove gen_helper_1e2i()Philippe Mathieu-Daudé2021-08-251-6/+0Star