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Experimental fork of QEMU with video encoding patches
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mips
Commit message (
Expand
)
Author
Age
Files
Lines
*
target/mips: Extract trap code into env->error_code
Richard Henderson
2022-01-11
3
-8
/
+24
*
target/mips: Extract break code into env->error_code
Richard Henderson
2022-01-11
4
-5
/
+16
*
exec/memop: Adding signedness to quad definitions
Frédéric Pétrot
2022-01-08
3
-38
/
+38
*
Merge remote-tracking branch 'remotes/philmd/tags/mips-20211102' into staging
Richard Henderson
2021-11-02
4
-2087
/
+845
|
\
|
*
target/mips: Remove obsolete FCR0_HAS2008 comment on P5600 CPU
Philippe Mathieu-Daudé
2021-11-02
1
-1
/
+0
|
*
target/mips: Fix Loongson-3A4000 MSAIR config register
Philippe Mathieu-Daudé
2021-11-02
1
-0
/
+1
|
*
target/mips: Remove one MSA unnecessary decodetree overlap group
Philippe Mathieu-Daudé
2021-11-02
1
-182
/
+180
|
*
target/mips: Remove generic MSA opcode
Philippe Mathieu-Daudé
2021-11-02
2
-9
/
+0
|
*
target/mips: Convert CTCMSA opcode to decodetree
Philippe Mathieu-Daudé
2021-11-02
2
-58
/
+16
|
*
target/mips: Convert CFCMSA opcode to decodetree
Philippe Mathieu-Daudé
2021-11-02
2
-9
/
+23
|
*
target/mips: Convert MSA MOVE.V opcode to decodetree
Philippe Mathieu-Daudé
2021-11-02
2
-6
/
+20
|
*
target/mips: Convert MSA COPY_S and INSERT opcodes to decodetree
Philippe Mathieu-Daudé
2021-11-02
2
-88
/
+19
|
*
target/mips: Convert MSA COPY_U opcode to decodetree
Philippe Mathieu-Daudé
2021-11-02
2
-26
/
+41
|
*
target/mips: Convert MSA ELM instruction format to decodetree
Philippe Mathieu-Daudé
2021-11-02
2
-13
/
+52
|
*
target/mips: Convert MSA 3R instruction format to decodetree (part 4/4)
Philippe Mathieu-Daudé
2021-11-02
2
-863
/
+106
|
*
target/mips: Convert MSA 3R instruction format to decodetree (part 3/4)
Philippe Mathieu-Daudé
2021-11-02
2
-34
/
+9
|
*
target/mips: Convert MSA 3R instruction format to decodetree (part 2/4)
Philippe Mathieu-Daudé
2021-11-02
2
-158
/
+35
|
*
target/mips: Convert MSA 3R instruction format to decodetree (part 1/4)
Philippe Mathieu-Daudé
2021-11-02
2
-12
/
+11
|
*
target/mips: Convert MSA 3RF instruction format to decodetree (DF_WORD)
Philippe Mathieu-Daudé
2021-11-02
2
-176
/
+76
|
*
target/mips: Convert MSA 3RF instruction format to decodetree (DF_HALF)
Philippe Mathieu-Daudé
2021-11-02
2
-39
/
+38
|
*
target/mips: Convert MSA VEC instruction format to decodetree
Philippe Mathieu-Daudé
2021-11-02
2
-75
/
+31
|
*
target/mips: Convert MSA 2R instruction format to decodetree
Philippe Mathieu-Daudé
2021-11-02
2
-75
/
+19
|
*
target/mips: Convert MSA FILL opcode to decodetree
Philippe Mathieu-Daudé
2021-11-02
2
-12
/
+21
|
*
target/mips: Convert MSA 2RF instruction format to decodetree
Philippe Mathieu-Daudé
2021-11-02
2
-85
/
+53
|
*
target/mips: Convert MSA load/store instruction format to decodetree
Philippe Mathieu-Daudé
2021-11-02
2
-59
/
+36
|
*
target/mips: Convert MSA I8 instruction format to decodetree
Philippe Mathieu-Daudé
2021-11-02
2
-56
/
+27
|
*
target/mips: Convert MSA SHF opcode to decodetree
Philippe Mathieu-Daudé
2021-11-02
2
-17
/
+22
|
*
target/mips: Convert MSA BIT instruction format to decodetree
Philippe Mathieu-Daudé
2021-11-02
2
-97
/
+101
|
*
target/mips: Convert MSA I5 instruction format to decodetree
Philippe Mathieu-Daudé
2021-11-02
2
-77
/
+41
|
*
target/mips: Convert MSA LDI opcode to decodetree
Philippe Mathieu-Daudé
2021-11-02
2
-9
/
+21
|
*
target/mips: Rename sa16 -> sa, bz_df -> bz -> bz_v
Philippe Mathieu-Daudé
2021-11-02
2
-18
/
+17
|
*
target/mips: Use enum definitions from CPUMIPSMSADataFormat enum
Philippe Mathieu-Daudé
2021-11-02
1
-3
/
+3
|
*
target/mips: Have check_msa_access() return a boolean
Philippe Mathieu-Daudé
2021-11-02
1
-7
/
+18
|
*
target/mips: Use dup_const() to simplify
Philippe Mathieu-Daudé
2021-11-02
1
-20
/
+3
|
*
target/mips: Adjust style in msa_translate_init()
Philippe Mathieu-Daudé
2021-11-02
1
-1
/
+3
|
*
target/mips: Fix MSA MSUBV.B opcode
Philippe Mathieu-Daudé
2021-11-02
1
-16
/
+16
|
*
target/mips: Fix MSA MADDV.B opcode
Philippe Mathieu-Daudé
2021-11-02
1
-16
/
+16
*
|
target/mips: Make mips_cpu_tlb_fill sysemu only
Richard Henderson
2021-11-02
5
-69
/
+5
|
/
*
target/mips: Remove unused TCG temporary in gen_mipsdsp_accinsn()
Philippe Mathieu-Daudé
2021-10-18
1
-4
/
+0
*
target/mips: Fix DEXTRV_S.H DSP opcode
Philippe Mathieu-Daudé
2021-10-18
1
-2
/
+1
*
target/mips: Use tcg_constant_tl() in gen_compute_compact_branch()
Philippe Mathieu-Daudé
2021-10-18
1
-3
/
+1
*
target/mips: Use explicit extract32() calls in gen_msa_i5()
Philippe Mathieu-Daudé
2021-10-18
1
-7
/
+4
*
target/mips: Use tcg_constant_i32() in gen_msa_3rf()
Philippe Mathieu-Daudé
2021-10-18
1
-9
/
+14
*
target/mips: Use tcg_constant_i32() in gen_msa_2r()
Philippe Mathieu-Daudé
2021-10-18
1
-3
/
+2
*
target/mips: Use tcg_constant_i32() in gen_msa_2rf()
Philippe Mathieu-Daudé
2021-10-18
1
-2
/
+1
*
target/mips: Use tcg_constant_i32() in gen_msa_elm_df()
Philippe Mathieu-Daudé
2021-10-18
1
-2
/
+1
*
target/mips: Remove unused register from MSA 2R/2RF instruction format
Philippe Mathieu-Daudé
2021-10-18
1
-6
/
+0
*
target/mips: Check nanoMIPS DSP MULT[U] accumulator with Release 6
Philippe Mathieu-Daudé
2021-10-17
1
-0
/
+6
*
target/mips: Drop exit checks for singlestep_enabled
Richard Henderson
2021-10-16
1
-32
/
+18
*
target/mips: Fix single stepping
Richard Henderson
2021-10-16
1
-9
/
+16
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